Pixel circuit and display device

Abstract

The utility model provides a pixel circuit and a display device. The pixel circuit comprises a driving circuit, a first control circuit, a second control circuit and a first initialization circuit. The first control circuit controls the connection between the first node and the fourth node under the control of a first control signal; the second control circuit controls the fourth node to be communicated with the third node under the control of a second control signal; the first initialization circuit writes the first initial voltage into the fourth node under the control of the first initial control signal. The embodiment of the utility model provides a pixel circuit with a new structure, which can work normally under the condition that a GOA (Gate On Array) module arranged on an array substrate is not added, and can improve the hysteresis phenomenon of a driving transistor included in the driving circuit and the residual image.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0002] AMOLED (active-matrix organic light-emitting diode) display panels are still widely used in screen products due to their lower cost and shorter production time, but they have defects such as poor afterimage. Utility Model Content

[0003] The main purpose of the present invention is to provide a pixel circuit and a display device to solve the problem in the prior art that a pixel circuit with a new structure cannot be provided and cannot work normally without adding a GOA (Gate On Array, a gate drive circuit provided on an array substrate) module.

[0004] In one aspect, an embodiment of the present invention provides a pixel circuit, comprising a driving circuit, a first control circuit, a second control circuit, and a first initialization circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node, and the driving circuit is configured to generate a driving current under the control of the potential of the first node;

[0006] The first control circuit is electrically connected to the first control terminal, the first node, and the fourth node respectively, and is configured to control the connection between the first node and the fourth node under the control of a first control signal provided by the first control terminal;

[0007] The second control circuit is electrically connected to the second control terminal, the fourth node and the third node respectively, and is used to control the fourth node to be connected to the third node under the control of the second control signal provided by the second control terminal;

[0008] The first initialization circuit is electrically connected to the first initial control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the fourth node, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal.

[0009] Optionally, the pixel circuit described in at least one embodiment of the present utility model further includes a second initialization circuit;

[0010] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second initial control signal provided by the second initial control terminal.

[0011] Optionally, the pixel circuit described in at least one embodiment of the present utility model further includes a second initialization circuit;

[0012] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the fourth node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the fourth node under the control of the second initial control signal provided by the second initial control terminal.

[0013] Optionally, the pixel circuit described in at least one embodiment of the present utility model further includes a light-emitting element, a first light-emitting control circuit, and a second initialization circuit;

[0014] The first light-emitting control circuit is electrically connected to the first light-emitting control signal terminal, the third node, and the first electrode of the light-emitting element, respectively, and is configured to control the connection between the third node and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control signal terminal; and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0015] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0016] Optionally, the pixel circuit described in at least one embodiment of the present utility model further includes a voltage control circuit;

[0017] The voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, and is used to control the potential of the fourth node according to the control voltage provided by the control voltage terminal; or,

[0018] The voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; or,

[0019] The pixel circuit also includes a light-emitting element and a first light-emitting control circuit. The voltage control circuit is electrically connected to the fourth node and the first light-emitting control signal terminal, respectively, and is used to control the potential of the fourth node according to the first light-emitting control signal provided by the first light-emitting control signal terminal.

[0020] Optionally, the first control terminal is an n-th level scanning terminal, the second control terminal is an n-th level gate driving terminal, the first initial control terminal is an n+y-th level gate driving terminal, and the second initial voltage terminal is an nx-th level scanning terminal;

[0021] n, x, and y are all positive integers.

[0022] Optionally, the first control end is an n-th level gate driving end, the second control end includes an n-th level scanning end and an n+y-th level scanning end, the first initial control end is an n+y-th level scanning end, and the second initial control end is an nx-th level scanning end;

[0023] n, x, and y are all positive integers.

[0024] Optionally, the first control end includes an n-th level scanning end and an nx-th level scanning end, the second control end is an n-th level gate driving end, the first initial control end is an n+y-th level gate driving end, and the second initial control end is an nx-th level scanning end;

[0025] n, x, and y are all positive integers.

[0026] Optionally, the first control end is the nth level second light-emitting control end, the second control end is the nath level third light-emitting control end, the first initial control end is the nth level third light-emitting control end, and the second initial control end is the nbth level gate driving end;

[0027] n, a, and b are all positive integers.

[0028] Optionally, the first control end is the nath level second light emitting control end, the second control end is the nth level second light emitting control end, the first initial control end is the n+bth level gate driving end, and the second initial control end is the ncth level second light emitting control end;

[0029] n, a, b, and c are all positive integers.

[0030] Optionally, the first control terminal is the second light-emitting control terminal of the nth level, the second control terminal is the third light-emitting control terminal of the nath level, the first initial control terminal is the third light-emitting control terminal of the nth level, the first light-emitting control signal terminal is the first light-emitting control terminal of the n+bth level, and the second initial control terminal is the gate driving terminal of the ncth level;

[0031] n, a, b, and c are all positive integers.

[0032] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0033] The gate of the first transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0034] The gate of the second transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0035] The gate of the third transistor is electrically connected to the n+yth stage gate driving terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node;

[0036] A gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.

[0037] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor and a fifth transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0038] The gate of the first transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0039] The gate of the second transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0040] The gate of the fifth transistor is electrically connected to the n+y-th stage scanning terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the third node;

[0041] The gate of the third transistor is electrically connected to the n+y-th stage scanning terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node;

[0042] The gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node or the first node.

[0043] Optionally, the first control circuit includes a first transistor and a sixth transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0044] The gate of the first transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0045] The gate of the sixth transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0046] The gate of the second transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0047] The gate of the third transistor is electrically connected to the n+y-th stage gate scanning terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node;

[0048] The gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first node or the fourth node.

[0049] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first initialization circuit includes a third transistor;

[0050] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0051] The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0052] A gate of the third transistor is electrically connected to the first initial control terminal, a first electrode of the third transistor is electrically connected to the first initial voltage terminal, and a second electrode of the third transistor is electrically connected to the fourth node.

[0053] Optionally, the first light emitting control circuit includes an eighth transistor, and the second initialization circuit includes a fourth transistor;

[0054] The gate of the eighth transistor is electrically connected to the first light-emitting control signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element;

[0055] The gate of the fourth transistor is electrically connected to the second initial control terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0056] Optionally, the voltage control circuit includes a first capacitor;

[0057] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the control voltage terminal; or,

[0058] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the third node; or,

[0059] A first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the first light-emitting control signal end.

[0060] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0061] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is configured to control the connection between the third node and the first electrode of the light-emitting element under the control of a light-emitting control signal provided by the light-emitting control terminal; and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0062] The second light emitting control circuit is electrically connected to the light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light emitting control signal;

[0063] The data writing circuit is electrically connected to the n-th level scanning terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the n-th level scanning signal provided by the n-th level scanning terminal; n is a positive integer;

[0064] The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the DC voltage end, and the energy storage circuit is used to store electrical energy.

[0065] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the control voltage terminal; the energy storage circuit includes a storage capacitor; a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the DC voltage terminal;

[0066] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1 fF.

[0067] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a light-emitting element, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0068] The second light-emitting control circuit is electrically connected to the second light-emitting control signal terminal, the power supply voltage terminal, and the second node, respectively, and is configured to control the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal provided by the second light-emitting control signal terminal;

[0069] The data writing circuit is electrically connected to the n-th level gate driving terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the n-th level gate driving signal provided by the n-th level gate driving terminal; n is a positive integer;

[0070] The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the DC voltage end, and the energy storage circuit is used to store electrical energy.

[0071] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the third node; the energy storage circuit includes a storage capacitor; a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the DC voltage terminal;

[0072] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1 fF.

[0073] Optionally, the pixel circuit described in at least one embodiment of the present utility model further includes a third initialization circuit;

[0074] The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.

[0075] Optionally, the second light emitting control circuit includes a seventh transistor, the first light emitting control circuit includes an eighth transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor;

[0076] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node;

[0077] The gate of the eighth transistor is electrically connected to the light emitting control terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element;

[0078] The gate of the ninth transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the ninth transistor is electrically connected to the data line, and the second electrode of the ninth transistor is electrically connected to the second node;

[0079] A first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to a DC voltage end.

[0080] Optionally, the second light emitting control circuit includes a seventh transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor;

[0081] The gate of the seventh transistor is electrically connected to the second light emitting control signal terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node;

[0082] The gate of the ninth transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the ninth transistor is electrically connected to the data line, and the second electrode of the ninth transistor is electrically connected to the second node;

[0083] A first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to a DC voltage end.

[0084] Optionally, the third initialization circuit includes a tenth transistor;

[0085] The gate of the tenth transistor is electrically connected to the third initial control terminal, the first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0086] In a second aspect, an embodiment of the present invention provides a display device comprising the above-mentioned pixel circuit.

[0087] At least one embodiment of the present invention provides a pixel circuit with a new structure, which can operate normally without adding a GOA (Gate On Array, a gate driving circuit arranged on an array substrate) module, and can improve the hysteresis phenomenon of the driving transistor included in the driving circuit and improve afterimage. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0089] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0090] Figure 3A is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0091] Figure 3B is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0092] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0093] Figure 5A is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0094] Figure 5B is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0095] Figure 5C is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0096] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0097] Figure 7A is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0098] Figure 7B is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0099] Figure 7C is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0100] Figure 7D is a structural diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0101] Figure 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0102] Figure 9 yes Figure 8 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0103] Figure 10 yes Figure 8 The working timing diagram of at least one embodiment of the pixel circuit shown in the holding frame;

[0104] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0105] Figure 12 yes Figure 11 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0106] Figure 13 yes Figure 11 The working timing diagram of at least one embodiment of the pixel circuit shown in the holding frame;

[0107] Figure 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0108] Figure 15 yes Figure 14 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0109] Figure 16 yes Figure 14 The working timing diagram of at least one embodiment of the pixel circuit shown in the holding frame;

[0110] Figure 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0111] Figure 18 yes Figure 17 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0112] Figure 19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0113] Figure 20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0114] Figure 21 yes Figure 20 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0115] Figure 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0116] Figure 23 yes Figure 22 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0117] Figure 24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

[0118] Figure 25 yes Figure 24 FIG. 1 is a timing diagram showing the operation of at least one embodiment of a pixel circuit in a refresh frame. DETAILED DESCRIPTION

[0119] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0120] The transistors used in all embodiments of the present invention can be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0121] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0122] The pixel circuit described in the embodiment of the present utility model includes a driving circuit, a first control circuit, a second control circuit and a first initialization circuit;

[0123] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node, and the driving circuit is configured to generate a driving current under the control of the potential of the first node;

[0124] The first control circuit is electrically connected to the first control terminal, the first node, and the fourth node respectively, and is configured to control the connection between the first node and the fourth node under the control of a first control signal provided by the first control terminal;

[0125] The second control circuit is electrically connected to the second control terminal, the fourth node and the third node respectively, and is used to control the fourth node to be connected to the third node under the control of the second control signal provided by the second control terminal;

[0126] The first initialization circuit is electrically connected to the first initial control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the fourth node, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal.

[0127] When the pixel circuit of the embodiment of the present invention is in operation,

[0128] During the compensation phase, the first control circuit controls the first node and the fourth node to be connected under the control of the first control signal, and the second control circuit controls the fourth node and the third node to be connected under the control of the second control signal, thereby controlling the first node and the third node to be connected;

[0129] In the first hysteresis improvement stage, the first initialization circuit writes the first initial voltage to the fourth node under the control of the first initial control signal, and the second control circuit controls the connection between the fourth node and the third node under the control of the second control signal to write the first initial voltage to the third node to improve the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0130] At least one embodiment of the present invention provides a pixel circuit with a new structure, which can operate normally without adding a GOA (Gate On Array, a gate driving circuit arranged on an array substrate) module, and can improve the hysteresis phenomenon of the driving transistor included in the driving circuit and improve afterimage.

[0131] At least one embodiment of the present invention can conveniently switch between the refresh frame and the hold frame by controlling the first control signal provided by the first control terminal, thereby enabling high-precision frequency conversion. Figure 1 As shown, the pixel circuit according to at least one embodiment of the present invention includes a driving circuit 10, a first control circuit 11, a second control circuit 12 and a first initialization circuit 13;

[0132] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is configured to generate a driving current under the control of the potential of the first node N1;

[0133] The first control circuit 11 is electrically connected to the first control terminal TC1, the first node N1, and the fourth node N4, respectively, and is configured to control the connection between the first node N1 and the fourth node N4 under the control of a first control signal provided by the first control terminal TC1;

[0134] The second control circuit 12 is electrically connected to the second control terminal TC2, the fourth node N4, and the third node N3, respectively, and is configured to control the fourth node N4 to be connected to the third node N3 under the control of a second control signal provided by the second control terminal TC2;

[0135] The first initialization circuit 13 is electrically connected to the first initial control terminal TI1, the first initial voltage terminal I1 and the fourth node N4, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the first initial control signal provided by the first initial control terminal TI1.

[0136] This utility model Figure 1 When at least one embodiment of the pixel circuit shown is in operation, a refresh frame may include a compensation phase and a first hysteresis improvement phase that are arranged in sequence;

[0137] During the compensation phase, the first control circuit 11 controls the first node N1 and the fourth node N4 to be connected under the control of the first control signal, and the second control circuit 12 controls the fourth node N4 and the third node N3 to be connected under the control of the second control signal, thereby controlling the first node N1 and the third node N3 to be connected.

[0138] In the first hysteresis improvement stage, the first initialization circuit 13 writes the first initial voltage Vi1 into the fourth node N4 under the control of the first initial control signal, and the second control circuit 12 controls the connection between the fourth node N4 and the third node N3 under the control of the second control signal to write the first initial voltage Vi1 into the third node N3 to improve the hysteresis phenomenon of the driving transistor included in the driving circuit 10.

[0139] This utility model Figure 1When at least one embodiment of the pixel circuit shown is in operation, in the first hysteresis improvement stage, the driving circuit 10 controls the connection between the second node N2 and the third node N3 under the control of the potential of the first node N1, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit 10.

[0140] This utility model Figure 1 In operation of at least one embodiment of the illustrated pixel circuit, the holding frame may include a second hysteresis improvement phase;

[0141] In the second hysteresis improvement stage, the first initialization circuit 13 writes the first initial voltage Vi1 into the fourth node N4 under the control of the first initial control signal, and the second control circuit 12 controls the connection between the fourth node N4 and the third node N3 under the control of the second control signal to write the first initial voltage Vi1 into the third node N3 to improve the hysteresis phenomenon of the driving transistor included in the driving circuit 10.

[0142] This utility model Figure 1 When at least one embodiment of the pixel circuit shown is in operation, in the second hysteresis improvement stage, the driving circuit 10 controls the connection between the second node N2 and the third node N3 under the control of the potential of the first node N1, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit 10.

[0143] like Figure 2 As shown, in Figure 1 In at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment further includes a second initialization circuit 21;

[0144] The second initialization circuit 21 is electrically connected to the second initial control terminal TI2, the second initial voltage terminal I2 and the first node N1 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second initial control signal provided by the second initial control terminal TI2.

[0145] The pixel circuit according to the embodiment of the present invention further includes a second initialization circuit;

[0146] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the fourth node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the fourth node under the control of the second initial control signal provided by the second initial control terminal.

[0147] In a specific implementation, the pixel circuit may further include a second initialization circuit, and the refresh frame may include an initialization phase and a compensation phase set successively; in the initialization phase, the first control circuit controls the connection between the first node and the fourth node under the control of the first control signal, and the second initialization circuit writes the second initial voltage to the fourth node under the control of the second initial control signal to write the second initial voltage to the first node, so that at the beginning of the compensation phase, the driving circuit controls the connection between the second node and the third node under the control of the potential of the first node.

[0148] like Figure 3A As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to the embodiment of the present invention further includes a second initialization circuit 21;

[0149] The second initialization circuit 21 is electrically connected to the second initial control terminal TI2, the second initial voltage terminal I2 and the fourth node N4, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the fourth node N4 under the control of the second initial control signal provided by the second initial control terminal TI2.

[0150] The pixel circuit according to at least one embodiment of the present invention may further include a light-emitting element, a first light-emitting control circuit and a second initialization circuit;

[0151] The first light-emitting control circuit is electrically connected to the first light-emitting control signal terminal, the third node, and the first electrode of the light-emitting element, respectively, and is configured to control the connection between the third node and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control signal terminal; and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0152] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0153] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit and a second initialization circuit, wherein the first light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of a first light-emitting control signal; and the second initialization circuit writes the second initial voltage into the first pole of the light-emitting element under the control of the second initial control signal.

[0154] Optionally, the first light-emitting control signal terminal may be the n+bth level first light-emitting control terminal, but is not limited thereto; n and b are both positive integers.

[0155] like Figure 3B As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention may further include a first light emitting control circuit 61 and a second initialization circuit 21;

[0156] The first light emitting control circuit 61 is electrically connected to the n+b-th first light emitting control terminal EM1(n+b), the third node N3, and the first electrode of the light emitting element E1, respectively, and is configured to control the connection between the third node N3 and the first electrode of the light emitting element E1 under the control of the n+b-th first light emitting control signal provided by the n+b-th first light emitting control terminal EM1(n+b); and the second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1.

[0157] The second initialization circuit 21 is electrically connected to the second initial control terminal TI2, the second initial voltage terminal I2 and the first electrode of the light-emitting element E1, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second initial control signal provided by the second initial control terminal TI2.

[0158] This utility model Figure 3B When at least one embodiment of the illustrated pixel circuit is in operation, a refresh frame may include an initialization phase;

[0159] During the initialization stage, the second initialization circuit 21 writes the second initial voltage Vi2 into the first pole of the light-emitting element E1 under the control of the second initial control signal, and the first light-emitting control circuit 61 controls the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the first light-emitting control signal of the n+bth level. The second control circuit 12 controls the connection between the fourth node N4 and the third node N3 under the control of the second control signal; the first control circuit 11 controls the connection between the first node N1 and the fourth node N4 under the control of the first control signal to write the second initial voltage Vi2 into the first node N1.

[0160] In at least one embodiment of the present invention, the pixel circuit further includes a voltage control circuit;

[0161] The voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, and is used to control the potential of the fourth node according to the control voltage provided by the control voltage terminal; or,

[0162] The voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; or,

[0163] The pixel circuit also includes a light-emitting element and a first light-emitting control circuit. The voltage control circuit is electrically connected to the fourth node and the first light-emitting control signal terminal, respectively, and is used to control the potential of the fourth node according to the first light-emitting control signal provided by the first light-emitting control signal terminal.

[0164] In a specific implementation, the pixel circuit may further include a voltage control circuit;

[0165] The voltage control circuit changes the potential of the fourth node according to the control voltage to improve the leakage phenomenon of the first node; or,

[0166] The voltage control circuit controls the potential of the fourth node according to the potential of the third node to improve the leakage phenomenon of the first node.

[0167] When the pixel circuit according to at least one embodiment of the present invention is in operation, when the voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, and is configured to control the potential of the fourth node according to the control voltage provided by the control voltage terminal,

[0168] The refresh frame may include a first hysteresis improvement stage and a first light-emitting stage, which are sequentially arranged. In a first voltage control stage between the first hysteresis improvement stage and the first light-emitting stage, the potential of the control voltage provided by the control voltage terminal decreases to correspondingly lower the potential of the fourth node, so that the voltage difference between the fourth node and the first node is small, thereby improving leakage of the first node.

[0169] The holding frame may include a second hysteresis improvement stage and a second light-emitting stage that are set successively. In the second voltage control stage between the second hysteresis improvement stage and the second light-emitting stage, the potential of the control voltage provided by the control voltage end decreases to correspondingly lower the potential of the fourth node, so that the voltage difference between the fourth node and the first node is smaller, thereby improving the leakage phenomenon of the first node.

[0170] In the first voltage control stage and the second voltage control stage, the potential of the control voltage may be pulled down to a greater extent, but is not limited thereto.

[0171] When the pixel circuit according to at least one embodiment of the present invention is in operation, when the voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node,

[0172] The refresh frame may include a first light-emitting phase provided after the first hysteresis improvement phase; at the beginning of the first light-emitting phase, the voltage control circuit controls the potential of the fourth node to be lowered according to the potential of the third node, so that the voltage difference between the fourth node and the first node is smaller, thereby improving leakage of the first node;

[0173] The holding frame may include a second light-emitting stage set after the second hysteresis improvement stage; at the beginning of the second light-emitting stage, the voltage control circuit controls the potential of the fourth node to become lower according to the potential of the third node, so that the voltage difference between the fourth node and the first node is smaller, thereby improving the leakage phenomenon of the first node.

[0174] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a voltage control circuit 41;

[0175] The voltage control circuit 41 is electrically connected to the fourth node N4 and the control voltage terminal VJ, and is configured to control the potential of the fourth node N4 according to the control voltage Vj provided by the control voltage terminal VJ.

[0176] like Figure 5A As shown, in Figure 3A Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a voltage control circuit 41;

[0177] The voltage control circuit 41 is electrically connected to the fourth node N4 and the control voltage terminal VJ, and is configured to control the potential of the fourth node N4 according to the control voltage Vj provided by the control voltage terminal VJ.

[0178] like Figure 5B As shown, in Figure 3A Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a voltage control circuit 41;

[0179] The voltage control circuit 41 is electrically connected to the fourth node N4 and the third node N3 , respectively, and is configured to control the potential of the fourth node N4 according to the potential of the third node N3 .

[0180] like Figure 5C As shown, in Figure 3B Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a voltage control circuit 41;

[0181] The voltage control circuit 41 is electrically connected to the fourth node N4 and the third node N3 , respectively, and is configured to control the potential of the fourth node N4 according to the potential of the third node N3 .

[0182] Optionally, the first control terminal is an n-th level scanning terminal, the second control terminal is an n-th level gate driving terminal, the first initial control terminal is an n+y-th level gate driving terminal, and the second initial voltage terminal is an nx-th level scanning terminal;

[0183] n, x, and y are all positive integers.

[0184] In a specific implementation, the first driving module can provide the nth level scanning signal to the first control terminal and the nxth level scanning signal to the second initial voltage terminal, and the second driving module can provide the nth level gate driving signal to the second control terminal and the n+yth level gate driving signal to the first initial control terminal, so as to reduce the number of driving modules used in the display device and facilitate the realization of a narrow frame.

[0185] Optionally, the first control end is an n-th level gate driving end, the second control end includes an n-th level scanning end and an n+y-th level scanning end, the first initial control end is an n+y-th level scanning end, and the second initial control end is an nx-th level scanning end;

[0186] n, x, and y are all positive integers.

[0187] In a specific implementation, the first driving module can provide the nth level scanning signal to the first second control terminal, the n+yth level scanning signal to the first initial control terminal, and the nxth level scanning signal to the second initial control terminal. The second driving module can provide the nth level gate driving signal to the first control terminal and the n+yth level scanning signal to the second second control terminal, so as to reduce the number of driving modules used in the display device and facilitate the realization of a narrow frame.

[0188] Optionally, the first control end includes an n-th level scanning end and an nx-th level scanning end, the second control end is an n-th level gate driving end, the first initial control end is an n+y-th level gate driving end, and the second initial control end is an nx-th level scanning end;

[0189] n, x, and y are all positive integers.

[0190] In a specific implementation, the first driving module can provide the nth level scanning signal to the first first control terminal, the nxth level scanning signal to the second first control terminal, and the nxth level scanning signal to the second initial control terminal. The second driving module can provide the nth level gate driving signal to the second control terminal, and the n+yth level gate driving signal to the first initial control terminal, so as to reduce the number of driving modules used in the display device and facilitate the realization of a narrow frame.

[0191] In at least one embodiment of the present invention, x can be at least 1. For example, x can be an integer greater than or equal to 2, and y can be an integer greater than or equal to 2. Moreover, considering the duty cycle of the signal and the convenience of wiring, the values ​​of x and y should generally not be greater than 20.

[0192] Optionally, the first control end is the nth level second light-emitting control end, the second control end is the nath level third light-emitting control end, the first initial control end is the nth level third light-emitting control end, and the second initial control end is the nbth level gate driving end;

[0193] n, a, and b are all positive integers.

[0194] Optionally, the first control end is the nath level second light emitting control end, the second control end is the nth level second light emitting control end, the first initial control end is the n+bth level gate driving end, and the second initial control end is the ncth level second light emitting control end;

[0195] n, a, b, and c are all positive integers.

[0196] Optionally, the first control terminal is the second light-emitting control terminal of the nth level, the second control terminal is the third light-emitting control terminal of the nath level, the first initial control terminal is the third light-emitting control terminal of the nth level, the first light-emitting control signal terminal is the first light-emitting control terminal of the n+bth level, and the second initial control terminal is the gate driving terminal of the ncth level;

[0197] n, a, b, and c are all positive integers.

[0198] In at least one embodiment of the present invention, the first control circuit includes a first transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0199] The gate of the first transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0200] The gate of the second transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0201] The gate of the third transistor is electrically connected to the n+yth stage gate driving terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node;

[0202] A gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.

[0203] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor and a fifth transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0204] The gate of the first transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0205] The gate of the second transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0206] The gate of the fifth transistor is electrically connected to the n+y-th stage scanning terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the third node;

[0207] The gate of the third transistor is electrically connected to the n+y-th stage scanning terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node;

[0208] The gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node or the first node.

[0209] Optionally, the first control circuit includes a first transistor and a sixth transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0210] The gate of the first transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0211] The gate of the sixth transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0212] The gate of the second transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0213] The gate of the third transistor is electrically connected to the n+y-th stage gate scanning terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node;

[0214] The gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first node or the fourth node.

[0215] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first initialization circuit includes a third transistor;

[0216] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;

[0217] The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0218] The gate of the third transistor is electrically connected to the first initial control terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node or the third node.

[0219] Optionally, the first light emitting control circuit includes an eighth transistor, and the second initialization circuit includes a fourth transistor;

[0220] The gate of the eighth transistor is electrically connected to the first light-emitting control signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element;

[0221] The gate of the fourth transistor is electrically connected to the second initial control terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0222] Optionally, the voltage control circuit includes a first capacitor;

[0223] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the control voltage terminal; or,

[0224] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the third node; or,

[0225] A first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the first light-emitting control signal end.

[0226] The pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0227] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is configured to control the connection between the third node and the first electrode of the light-emitting element under the control of a light-emitting control signal provided by the light-emitting control terminal; and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0228] The second light emitting control circuit is electrically connected to the light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light emitting control signal;

[0229] The data writing circuit is electrically connected to the n-th level scanning terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the n-th level scanning signal provided by the n-th level scanning terminal; n is a positive integer;

[0230] The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the DC voltage end, and the energy storage circuit is used to store electrical energy.

[0231] In a specific implementation, the pixel circuit may further include a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit and an energy storage circuit; the second light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal; the first light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the light-emitting control signal; the data writing circuit writes the data voltage provided by the data line into the second node under the control of the n-th level scanning signal; and the energy storage circuit maintains the potential of the first node.

[0232] Optionally, the first voltage terminal may be a low voltage terminal, and the DC voltage terminal may be a power supply voltage terminal, but is not limited thereto.

[0233] The pixel circuit of at least one embodiment of the present invention may further include a voltage control circuit; the voltage control circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the control voltage terminal; the energy storage circuit includes a storage capacitor; a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the DC voltage terminal;

[0234] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1 fF.

[0235] In at least one embodiment of the present invention, considering that if the equivalent capacitance value of the fourth node is too large, it will affect the compensation speed of the driving transistor, therefore, the capacitance value of the first capacitor should be less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and considering that when the potential of the control voltage provided by the control voltage terminal decreases, the potential of the fourth node needs to be pulled down by a larger amount, the capacitance value of the first capacitor should be greater than or equal to 1fF.

[0236] The pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0237] The second light-emitting control circuit is electrically connected to the second light-emitting control signal terminal, the power supply voltage terminal, and the second node, respectively, and is configured to control the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal provided by the second light-emitting control signal terminal;

[0238] The data writing circuit is electrically connected to the n-th level gate driving terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the n-th level gate driving signal provided by the n-th level gate driving terminal; n is a positive integer;

[0239] The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the DC voltage end, and the energy storage circuit is used to store electrical energy.

[0240] Optionally, the second light-emitting control signal terminal may be the n-th level first light-emitting control terminal, but is not limited thereto; n is a positive integer.

[0241] In at least one embodiment of the present invention, the pixel circuit may further include a voltage control circuit; the voltage control circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the third node; the energy storage circuit includes a storage capacitor; a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the DC voltage terminal;

[0242] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1 fF.

[0243] In at least one embodiment of the present invention, considering that if the equivalent capacitance value of the fourth node is too large, it will affect the compensation speed of the driving transistor, therefore, the capacitance value of the first capacitor should be less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and considering that when the potential of the third node decreases, the potential of the fourth node needs to be pulled down by a larger amount, the capacitance value of the first capacitor should be greater than or equal to 1fF.

[0244] In at least one embodiment of the present invention, the pixel circuit further includes a third initialization circuit;

[0245] The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.

[0246] In a specific implementation, the pixel circuit may further include a third initialization circuit, which, under the control of the third initial control signal, writes the third initial voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.

[0247] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element E1, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60 and a third initialization circuit 64;

[0248] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, and the third node N3 is electrically connected to the first electrode of the light emitting element E1, and is configured to control the third node N3 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal; and the second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0249] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal ELVDD and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0250] The data writing circuit 63 is electrically connected to the n-th level scanning terminal S(n), the data line DT and the second node N2, and is used to write the data voltage provided by the data line DT into the second node under the control of the n-th level scanning signal provided by the n-th level scanning terminal S(n); n is a positive integer;

[0251] A first terminal of the energy storage circuit 60 is electrically connected to the first node N1, a second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD, and the energy storage circuit 60 is used to store electrical energy;

[0252] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3 and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0253] like Figure 7A As shown, in Figure 5A Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element E1, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60 and a third initialization circuit 64;

[0254] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, and the third node N3 is electrically connected to the first electrode of the light emitting element E1, and is configured to control the third node N3 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal; and the second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0255] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal ELVDD and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0256] The data writing circuit 63 is electrically connected to the n-th level scanning terminal S(n), the data line DT and the second node N2, and is used to write the data voltage provided by the data line DT into the second node under the control of the n-th level scanning signal provided by the n-th level scanning terminal S(n); n is a positive integer;

[0257] A first terminal of the energy storage circuit 60 is electrically connected to the first node N1, a second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD, and the energy storage circuit 60 is used to store electrical energy;

[0258] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3 and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0259] like Figure 7B As shown, in Figure 5B Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element E1, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60 and a third initialization circuit 64;

[0260] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, and the third node N3 is electrically connected to the first electrode of the light emitting element E1, and is configured to control the third node N3 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal; and the second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0261] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal ELVDD and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0262] The data writing circuit 63 is electrically connected to the n-th gate driving terminal G(n), the data line DT and the second node N2, and is configured to write the data voltage provided by the data line DT into the second node under the control of the n-th gate driving signal provided by the n-th gate driving terminal G(n); n is a positive integer;

[0263] A first terminal of the energy storage circuit 60 is electrically connected to the first node N1, a second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD, and the energy storage circuit 60 is used to store electrical energy;

[0264] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3 and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0265] like Figure 7C As shown, in Figure 3B In at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element E1, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60 and a third initialization circuit 64;

[0266] The second light emitting control circuit 62 is electrically connected to the n-th first light emitting control terminal EM1(n), the power supply voltage terminal ELVDD, and the second node N2, respectively, and is configured to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the n-th first light emitting control signal provided by the n-th first light emitting control terminal EM1(n);

[0267] The data writing circuit 63 is electrically connected to the n-th gate driving terminal G(n), the data line DT and the second node N2, respectively, and is configured to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the n-th gate driving signal provided by the n-th gate driving terminal G(n); n is a positive integer;

[0268] A first terminal of the energy storage circuit 60 is electrically connected to the first node N1, a second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD, and the energy storage circuit 60 is used to store electrical energy;

[0269] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3 and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0270] Figure 7D At least one embodiment of the pixel circuit shown is similar to Figure 7C The differences of at least one embodiment of the pixel circuit shown are as follows:

[0271] The second initialization circuit 21 is not electrically connected to the first electrode of the light emitting element E1, and the second initialization circuit 21 is electrically connected to the third node N3;

[0272] The second initialization circuit 21 is configured to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the third node N3 under the control of a second initial control signal provided by the second initial control terminal TI2.

[0273] Optionally, the second light emitting control circuit includes a seventh transistor, the first light emitting control circuit includes an eighth transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor;

[0274] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node;

[0275] The gate of the eighth transistor is electrically connected to the light emitting control terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element;

[0276] The gate of the ninth transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the ninth transistor is electrically connected to the data line, and the second electrode of the ninth transistor is electrically connected to the second node;

[0277] A first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to a DC voltage end.

[0278] Optionally, the second light emitting control circuit includes a seventh transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor;

[0279] The gate of the seventh transistor is electrically connected to the second light emitting control signal terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node;

[0280] The gate of the ninth transistor is electrically connected to the n-th stage gate driving terminal, the first electrode of the ninth transistor is electrically connected to the data line, and the second electrode of the ninth transistor is electrically connected to the second node;

[0281] A first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to a DC voltage end.

[0282] Optionally, the third initialization circuit includes a tenth transistor;

[0283] The gate of the tenth transistor is electrically connected to the third initial control terminal, the first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0284] Optionally, the light-emitting element may be an organic light-emitting diode, but is not limited thereto; in a specific implementation, the light-emitting element may be other types of light-emitting diodes.

[0285] like Figure 8 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3, and the second initialization circuit includes a fourth transistor T4; the light-emitting element is an organic light-emitting diode O1; and the driving circuit includes a driving transistor T0;

[0286] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0287] The gate of the first transistor T1 is electrically connected to the n-th stage scanning terminal S(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;

[0288] The gate of the second transistor T2 is electrically connected to the n-th stage gate driving terminal G(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0289] The gate of the third transistor T3 is electrically connected to the n+y-th stage gate driving terminal G(n+y), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0290] The gate of the fourth transistor T4 is electrically connected to the nx-th stage scanning terminal S(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the first node N1; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0291] The voltage control circuit includes a first capacitor C1;

[0292] A first end of the first capacitor C1 is electrically connected to the fourth node N4, and a second end of the first capacitor C1 is electrically connected to the control voltage terminal VJ;

[0293] The second light emitting control circuit includes a seventh transistor T7, the first light emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst;

[0294] The gate of the seventh transistor T7 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2;

[0295] The gate of the eighth transistor T8 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of O1 is electrically connected to the low voltage terminal ELVSS;

[0296] The gate of the ninth transistor T9 is electrically connected to the n-th stage scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2;

[0297] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0298] The third initialization circuit includes a tenth transistor T10;

[0299] The gate of the tenth transistor T10 is electrically connected to the n+yth stage gate driving terminal G(n+y), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1.

[0300] exist Figure 8 In at least one embodiment of the pixel circuit shown, the light emitting control terminal may be an n-th level light emitting control terminal.

[0301] exist Figure 8 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0302] exist Figure 8 In at least one embodiment of the pixel circuit shown, the second end of C1 may be electrically connected to N3 instead, or the second end of C1 may be electrically connected to EM(n) instead.

[0303] exist Figure 8 In at least one embodiment of the pixel circuit shown, T4 is controlled by S(nx), T1 and T9 are controlled by S(n), T3 and T10 are controlled by G(n+y), T2 is controlled by G(n), T7 and T8 are controlled by EM(n), and scanning signals are provided for S(nx) and S(n) by the same GOA module, and gate drive signals are provided for G(n+y) and G(n) by the same GOA module, so that the number of GOA modules used can be reduced.

[0304] like Figure 9 As shown, the utility model Figure 8 In at least one embodiment of the pixel circuit shown, the refresh frame FX may include an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10, and a first light emitting phase t14, which are arranged in sequence;

[0305] In the initialization phase t11, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a low voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T4 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1, so that T0 can be turned on when the compensation phase t2 begins;

[0306] In the compensation phase t12, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a low voltage signal, G(n+y) provides a high voltage signal, T9 is turned on, DT provides a data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 is connected to N3;

[0307] At the beginning of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T2, and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth. T0 is turned off, and Vth is the threshold voltage of T0.

[0308] In the first hysteresis improvement phase t13, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, G(n+y) provides a low voltage signal, T3 is turned on, T2 is turned on, and I1 provides a first initial voltage Vi1 to the third node N3 to improve the hysteresis phenomenon of T0;

[0309] In the first hysteresis improvement stage t13, T0 is turned on to write Vi1 into the second node N2 to improve the hysteresis phenomenon of T0;

[0310] In the first hysteresis improvement stage t13, T10 is turned on, and I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0311] In the first voltage control stage t10, the potential of the control voltage provided by VJ decreases to control the potential of N4 to decrease, reduce the voltage difference between N1 and N4, improve the leakage of N1, and improve the flicker phenomenon;

[0312] In the first light-emitting stage t14, EM(n) provides a low voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0313] exist Figure 8 In at least one embodiment shown, T4 and T1 may be dual-gate transistors, but the present invention is not limited thereto.

[0314] like Figure 10 As shown, the utility model Figure 8 When at least one embodiment of the pixel circuit shown is in operation, the holding frame FB may include a second hysteresis improvement phase t23, a second voltage control phase t20, and a second light emitting phase t24, which are arranged in sequence;

[0315] In the second hysteresis improvement phase t23, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, G(n+y) provides a low voltage signal, T3 is turned on, T2 is turned on, and I1 provides a first initial voltage Vi1 to the third node N3 to improve the hysteresis phenomenon of T0 and improve the afterimage;

[0316] In the second hysteresis improvement stage t23, T0 is turned on to write Vi1 into the second node N2 to improve the hysteresis phenomenon of T0;

[0317] In the second hysteresis improvement stage t23, T10 is turned on, and I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0318] In the second voltage control stage t20, the potential of the control voltage provided by VJ decreases to control the potential of N4 to decrease, reduce the voltage difference between N1 and N4, improve the leakage of N1, and improve the flicker phenomenon;

[0319] In the second light-emitting stage t24, EM(n) provides a low voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0320] This utility model Figure 8 In at least one embodiment of the pixel circuit shown, during operation, during the second voltage supply phase, or at the moment when the light-emitting phase begins, the potential of the control voltage Vj provided by the control voltage terminal VJ is significantly lowered and is relatively stable during the light-emitting phase.

[0321] Considering that if the equivalent capacitance value of the fourth node N4 is too large, it will affect the compensation speed of the driving transistor T0, therefore, the capacitance value of C1 should be less than or equal to 1 / 5 of the capacitance value of the storage capacitor Cst. In addition, considering that when the potential of Vj decreases, the potential of N4 needs to be pulled down by a larger amount, the capacitance value of C1 should be greater than or equal to 1fF.

[0322] The pixel circuit described in at least one embodiment of the present invention can operate normally without increasing the number of GOA (Gate On Array, a gate driving circuit provided on an array substrate) modules, and supports high-precision frequency conversion, afterimage improvement, and low-frequency display.

[0323] like Figure 11 As shown, in Figure 7A Based on at least one embodiment of the pixel circuit shown, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2 and a fifth transistor T5, the first initialization circuit includes a third transistor T3, and the second initialization circuit includes a fourth transistor T4; the driving circuit includes a driving transistor T0, the light-emitting element includes an organic light-emitting diode O1; and the voltage control circuit includes a first capacitor C1;

[0324] A first end of the first capacitor C1 is electrically connected to the fourth node N4, and a second end of the first capacitor C1 is electrically connected to the control voltage terminal VJ;

[0325] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3;

[0326] The gate of the first transistor T1 is electrically connected to the n-th stage gate driving terminal G(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;

[0327] The gate of the second transistor T2 is electrically connected to the n-th stage scanning terminal S(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0328] The gate of the fifth transistor T5 is electrically connected to the n+y-th stage scanning terminal S(n+y), the source of the fifth transistor T5 is electrically connected to the fourth node N4, and the drain of the fifth transistor T5 is electrically connected to the third node N3;

[0329] The gate of the third transistor T3 is electrically connected to the n+y-th stage scanning terminal S(n+y), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4;

[0330] The gate of the fourth transistor T4 is electrically connected to the nx-th stage scanning terminal S(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4;

[0331] The second light emitting control circuit includes a seventh transistor T7, the first light emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst;

[0332] The gate of the seventh transistor T7 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2;

[0333] The gate of the eighth transistor T8 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of O1 is electrically connected to the low voltage terminal ELVSS;

[0334] The gate of the ninth transistor T9 is electrically connected to the n-th stage scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2;

[0335] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0336] The third initialization circuit includes a tenth transistor T10;

[0337] The gate of the tenth transistor T10 is electrically connected to the nth stage scanning terminal S(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1.

[0338] exist Figure 11 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0339] exist Figure 11 In at least one embodiment of the pixel circuit shown, the second end of C1 may be electrically connected to N3 instead, or the second end of C1 may be electrically connected to EM(n) instead.

[0340] exist Figure 11 In at least one embodiment of the pixel circuit shown, T3 and T5 are controlled by S(n+y), T2, T9, and T10 are controlled by S(n), T4 is controlled by S(nx), and T7 and T8 are controlled by EM(n). The same GOA module can be used to provide scanning signals for S(n+y), S(n), and S(nx), so as to reduce the number of GOA modules used.

[0341] like Figure 12 As shown, the utility model Figure 11 When at least one embodiment of the pixel circuit shown is in operation, a refresh frame FX may include an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10, and a first light-emitting phase t14, which are arranged in sequence;

[0342] In the initialization phase t11, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a low voltage signal, S(n) provides a high voltage signal, S(n+y) provides a high voltage signal, T4 and T1 are turned on, and I2 provides a second initial voltage Vi2 to the first node N1, so that T0 can be turned on when the compensation phase t12 begins;

[0343] In the compensation phase t12, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a low voltage signal, S(n+y) provides a high voltage signal, T1 is turned on, T2 is turned on, T9 is turned on, T10 is turned on, DT provides a data voltage Vdata to the second node N2, I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge at the anode of O1;

[0344] At the beginning of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T2, and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth. T0 is turned off, and Vth is the threshold voltage of T0.

[0345] In the first hysteresis improvement stage t13, EM(n) provides a high voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 is turned on, T5 is turned on, I1 provides a first initial voltage Vi1 to the third node N3, T0 is turned on, and Vi is written to the second node N2, thereby improving the hysteresis phenomenon of T0 and improving the afterimage;

[0346] In the first voltage control stage t10, the potential of the control voltage provided by VJ decreases to control the potential of N4 to decrease, reduce the voltage difference between N1 and N4, improve the leakage of N1, and improve the flicker phenomenon;

[0347] In the first light-emitting stage t14, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0348] like Figure 13 As shown, the utility model Figure 11 When at least one embodiment of the pixel circuit shown is in operation, the holding frame FB may include a second hysteresis improvement phase t23, a second voltage control phase t20, and a second light emitting phase t24, which are arranged in sequence;

[0349] In the second hysteresis improvement stage t23, EM(n) provides a high voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 and T5 are turned on, I1 provides a first initial voltage Vi1 to the third node N3, T0 is turned on, and Vi1 is written to the second node N2, thereby improving the hysteresis phenomenon of T0 and improving the afterimage;

[0350] In the second voltage control stage t20, the potential of the control voltage provided by VJ decreases to control the potential of N4 to decrease, reduce the voltage difference between N1 and N4, improve the leakage of N1, and improve the flicker phenomenon;

[0351] In the second light-emitting stage t24, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0352] like Figure 14 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2 and a fifth transistor T5, the first initialization circuit includes a third transistor T3, and the second initialization circuit includes a fourth transistor T4; the driving circuit includes a driving transistor T0, the light-emitting element includes an organic light-emitting diode O1; and the voltage control circuit includes a first capacitor C1;

[0353] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3;

[0354] A first end of the first capacitor C1 is electrically connected to the fourth node N4, and a second end of the first capacitor C1 is electrically connected to the control voltage terminal VJ;

[0355] The gate of the first transistor T1 is electrically connected to the n-th stage gate driving terminal G(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;

[0356] The gate of the second transistor T2 is electrically connected to the n-th stage scanning terminal S(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0357] The gate of the fifth transistor T5 is electrically connected to the n+y-th stage scanning terminal S(n+y), the source of the fifth transistor T5 is electrically connected to the fourth node N4, and the drain of the fifth transistor T5 is electrically connected to the third node N3;

[0358] The gate of the third transistor T3 is electrically connected to the n+y-th stage scanning terminal S(n+y), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4;

[0359] The gate of the fourth transistor T4 is electrically connected to the nx-th stage gate driving terminal G(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4;

[0360] The second light emitting control circuit includes a seventh transistor T7, the first light emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst;

[0361] The gate of the seventh transistor T7 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2;

[0362] The gate of the eighth transistor T8 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of O1 is electrically connected to the low voltage terminal ELVSS;

[0363] The gate of the ninth transistor T9 is electrically connected to the n-th stage scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2;

[0364] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0365] The third initialization circuit includes a tenth transistor T10;

[0366] The gate of the tenth transistor T10 is electrically connected to the nth stage scanning terminal S(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1.

[0367] exist Figure 14 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0368] exist Figure 14 In at least one embodiment of the pixel circuit shown, the second end of C1 may be electrically connected to N3 instead, or the second end of C1 may be electrically connected to EM(n) instead.

[0369] exist Figure 14 In at least one embodiment of the pixel circuit shown, T4 is controlled by G(nx), T1 is controlled by G(n), T3 and T5 are controlled by S(n+y), T2, T9 and T10 are controlled by S(n), and T7 and T8 are controlled by EM(n). The same GOA module can be used to provide gate drive signals for G(nx) and G(n), and the same GOA module can be used to provide scan signals for S(n+y) and S(n), so as to reduce the number of GOA modules used.

[0370] like Figure 15 As shown, the utility model Figure 14 At least one embodiment of the pixel circuit shown is in operation.

[0371] The refresh frame FX may include an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10 and a first light emitting phase t14 which are arranged in sequence;

[0372] In the initialization phase t11, EM(n) provides a high voltage signal, G(nx) provides a low voltage signal, G(n) provides a low voltage signal, S(n) provides a high voltage signal, S(n+y) provides a high voltage signal, T4 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1, so that T0 can be turned on when the compensation phase t12 begins;

[0373] In the compensation phase t12, EM(n) provides a high voltage signal, G(nx) provides a high voltage signal, G(n) provides a low voltage signal, S(n) provides a low voltage signal, S(n+y) provides a high voltage signal, T1 is turned on, T9 and T1 are turned on, T2 is turned on, DT provides a data voltage Vdata to the second node N2, N1 and N3 are connected, I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge at the anode of O1;

[0374] At the beginning of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T2, and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0;

[0375] In the first hysteresis improvement stage t13, EM(n) provides a high voltage signal, G(nx) provides a high voltage signal, G(n) provides a high voltage signal, S(n) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 and T5 are turned on, I1 provides a first initial voltage Vi1 to the third node N3, T0 is turned on, and Vi1 is written to the second node N2, thereby improving the hysteresis phenomenon of T0 and improving the afterimage;

[0376] In the first voltage holding stage t10, the potential of the control voltage provided by VJ decreases to control the potential of N4 to decrease, reduce the voltage difference between N1 and N4, improve the leakage of N1, and improve the flicker phenomenon;

[0377] In the first light-emitting stage t14, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0378] like Figure 16 As shown, the utility model Figure 14 When at least one embodiment of the pixel circuit shown is in operation, the holding frame FB may include a second hysteresis improvement phase t23, a second voltage control phase t20, and a second light emitting phase t24, which are arranged in sequence;

[0379] In the second hysteresis improvement stage t23, EM(n) provides a high voltage signal, G(nx) provides a high voltage signal, G(n) provides a high voltage signal, S(n) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 and T5 are turned on, I1 provides a first initial voltage Vi1 to the third node N3, T0 is turned on, and Vi1 is written to the second node N2, thereby improving the hysteresis phenomenon of T0 and improving the afterimage;

[0380] In the second voltage control stage t20, the potential of the control voltage provided by VJ decreases to control the potential of N4 to decrease, reduce the voltage difference between N1 and N4, improve the leakage of N1, and improve the flicker phenomenon;

[0381] In the second light-emitting stage t24, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0382] like Figure 17 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the first control circuit includes a first transistor T1 and a sixth transistor T6, the second control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3, and the second initialization circuit includes a fourth transistor T4; the driving circuit includes a driving transistor T0; and the voltage control circuit includes a first capacitor C1;

[0383] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3;

[0384] A first end of the first capacitor C1 is electrically connected to the fourth node N4, and a second end of the first capacitor C1 is electrically connected to the control voltage terminal VJ;

[0385] The gate of the first transistor T1 is electrically connected to the nx-th stage scanning terminal S(nx), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;

[0386] The gate of the sixth transistor T6 is electrically connected to the n-th stage scanning terminal S(n), the source of the sixth transistor T6 is electrically connected to the first node N1, and the drain of the sixth transistor T6 is electrically connected to the fourth node N4;

[0387] The gate of the second transistor T2 is electrically connected to the n-th stage gate driving terminal G(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0388] The gate of the third transistor T3 is electrically connected to the n+y-th stage gate scanning terminal G(n+y), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0389] The gate of the fourth transistor T4 is electrically connected to the nx-th stage scanning terminal S(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the first node N1; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0390] The second light emitting control circuit includes a seventh transistor T7, the first light emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst;

[0391] The gate of the seventh transistor T7 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2;

[0392] The gate of the eighth transistor T8 is electrically connected to the n-th stage light emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of O1 is electrically connected to the low voltage terminal ELVSS;

[0393] The gate of the ninth transistor T9 is electrically connected to the n-th stage scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2;

[0394] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0395] The third initialization circuit includes a tenth transistor T10;

[0396] The gate of the tenth transistor T10 is electrically connected to the n+yth stage gate driving terminal G(n+y), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1.

[0397] exist Figure 17 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0398] exist Figure 17 In at least one embodiment of the pixel circuit shown, the second end of C1 may be electrically connected to N3 instead, or the second end of C1 may be electrically connected to EM(n) instead.

[0399] exist Figure 17 In at least one embodiment of the pixel circuit shown, T1 and T4 are controlled by S(nx), T6 and T9 are controlled by S(n), T3 and T10 are controlled by G(n+y), T2 is controlled by G(n), T7 and T8 are controlled by EM(n), scanning signals are provided for S(nx) and S(n) by the same GOA module, and gate drive signals are provided for G(n+y) and G(n) by the same GOA module, so that the number of GOA modules used can be reduced.

[0400] like Figure 18 As shown, the utility model Figure 17 When at least one embodiment of the pixel circuit shown is in operation, a refresh frame FX may include an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10, and a first light-emitting phase t14, which are arranged in sequence;

[0401] In the initialization phase t11, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a low voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T4 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1, so that T0 can be turned on when the compensation phase t12 begins;

[0402] In the compensation phase t12, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a low voltage signal, G(n+y) provides a high voltage signal, T9 is turned on, DT provides a data voltage Vdata to the second node N2, T6 is turned on, and T2 is turned on, so that N1 and N3 are connected;

[0403] At the beginning of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T2, and T6, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, and T0 is turned off; Vth is the threshold voltage of T0;

[0404] In the first hysteresis improvement phase t13, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, G(n+y) provides a low voltage signal, T10 is turned on, I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1; T3 and T2 are turned on, I1 provides a first initial voltage Vi1 to the third node N3, and T0 is turned on to write Vi1 to the second node N2, thereby improving the hysteresis phenomenon of T0 and improving the afterimage;

[0405] In the first voltage holding stage t10, the potential of the control voltage provided by VJ decreases to control the potential of N4 to decrease, reduce the voltage difference between N1 and N4, improve the leakage of N1, and improve the flicker phenomenon;

[0406] In the first light-emitting stage t14, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0407] This utility model Figure 19 At least one embodiment of the pixel circuit shown is consistent with the present invention Figure 17 The difference of at least one embodiment of the pixel circuit shown is that:

[0408] The drain of T4 is electrically connected to the fourth node N4.

[0409] like Figure 20 As shown, in Figure 7BBased on at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1;

[0410] The first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3; the driving circuit includes a driving transistor T0;

[0411] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3;

[0412] The gate of the first transistor T1 is electrically connected to the n-th stage second light emitting control terminal EM2(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;

[0413] The gate of the second transistor T2 is electrically connected to the n-4th stage third light emitting control terminal EM3 (n-4), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0414] The gate of the third transistor T3 is electrically connected to the n-th stage third light-emitting control terminal EM3(n), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0415] The first light emitting control circuit includes an eighth transistor T8, and the second initialization circuit includes a fourth transistor T4;

[0416] The gate of the eighth transistor T8 is electrically connected to the n-th stage first light emitting control terminal EM1(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0417] The gate of the fourth transistor T4 is electrically connected to the n-1th stage gate driving terminal G(n-1), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0418] The second light emitting control circuit includes a seventh transistor T7; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst;

[0419] The gate of the seventh transistor T7 is electrically connected to the n-th stage first light emitting control terminal EM1(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2;

[0420] The gate of the ninth transistor T9 is electrically connected to the n-th stage gate driving terminal G(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2;

[0421] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0422] The voltage control circuit includes a first capacitor C1;

[0423] A first end of the first capacitor C1 is electrically connected to the fourth node N4, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0424] The third initialization circuit includes a tenth transistor T10;

[0425] The gate of the tenth transistor T10 is electrically connected to the n-th gate driving terminal G(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1; the third initial voltage terminal I3 is used to provide a third initial voltage Vi3.

[0426] exist Figure 20 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0427] exist Figure 20 In at least one embodiment of the pixel circuit shown, the second terminal of C1 may be electrically connected to the control voltage terminal VJ instead.

[0428] exist Figure 20 In at least one embodiment of the pixel circuit shown, T7 and T8 are controlled by EM1(n), T9 and T10 are controlled by G(n), T4 is controlled by G(n-1), T2 is controlled by EM3(n-4), and T3 is controlled by EM3(n). The same GOA module provides gate drive signals for G(n) and G(n-1), and the same GOA module provides a third light-emitting control signal for EM3(n-4) and EM3(n), so as to reduce the number of GOA modules used.

[0429] In this utility model Figure 20 、 Figure 22 、 Figure 24 In at least one embodiment of the pixel circuit shown, only T1 is electrically connected to the first node N1. In this way, it is only necessary to control the leakage between N4 and N1 to improve the high-brightness brightness attenuation problem of the LTPS (low-temperature polysilicon) pixel circuit in low-frequency display.

[0430] like Figure 21 As shown, the utility model Figure 20 When at least one embodiment of the pixel circuit shown is in operation, a refresh frame includes an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10, and a first light-emitting phase t4, which are arranged in sequence;

[0431] In the initialization phase t11, EM1(n) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a low voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T1 is turned on, T4 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1, so that T0 can be turned on when the compensation phase t12 begins; T2 is turned on, and I2 writes Vi2 to the third node N3 to improve the hysteresis of T0;

[0432] In the compensation phase t12, EM1(n) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a high voltage signal, G(n) provides a low voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T9 is turned on, DT provides a data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 and N3 are connected; T10 is turned on, I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0433] At the beginning of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T1, and T2 until T0 is turned off. The potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0434] In the first hysteresis improvement stage t13, EM1(n) provides a high voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a low voltage signal, T3 is turned on, T2 is turned on, I1 provides a first initial voltage Vi1 to the third node N3, T0 is turned on, and Vi1 is written to the second node N2, thereby improving the hysteresis phenomenon of T0 and improving the afterimage;

[0435] In the first voltage control stage t10, the potential of the n-th level first light-emitting control signal provided by EM1(n) drops from a high voltage to a low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage of N1 and the flicker phenomenon;

[0436] In the first light-emitting stage t14, EM1(n) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0437] This utility model Figure 20 At least one embodiment of the pixel circuit shown in the figure does not perform data writing and data compensation during operation while maintaining a frame;

[0438] The holding frame may include a second initialization phase, a third initialization phase, a second hysteresis improvement phase, a second voltage control phase, and a second light emitting phase that are sequentially arranged;

[0439] In the second initialization phase, T4 is turned on, T2 is turned on, I2 provides a second initial voltage Vi2 to the third node N3, T0 is turned on, and Vi2 is written into the second node N2 to improve the hysteresis phenomenon of T0;

[0440] In the third initialization stage, T10 is turned on, and I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0441] In the second hysteresis improvement stage, T3 is turned on, T2 is turned on, I1 provides the first initial voltage Vi1 to the fourth node N4, T2 is turned on, Vi1 is written to the third node N3, T0 is turned on, Vi1 is written to the second node N2, and the hysteresis phenomenon of T0 is improved;

[0442] In the second voltage control stage, the potential of the n-th level first light-emitting control signal provided by EM1(n) drops from a high voltage to a low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage of N1 and the flicker phenomenon;

[0443] In the second light-emitting stage, EM1(n) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0444] like Figure 22 As shown, in Figure 7D Based on at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1;

[0445] The first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the first initialization circuit includes a third transistor T3;

[0446] The gate of the first transistor T1 is electrically connected to the n-th stage second light emitting control terminal EM2(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;

[0447] The gate of the second transistor T2 is electrically connected to the n-4th stage third light emitting control terminal EM3 (n-4), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0448] The gate of the third transistor T3 is electrically connected to the n-th stage third light-emitting control terminal EM3(n), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0449] The first light emitting control circuit includes an eighth transistor T8, and the second initialization circuit includes a fourth transistor T4;

[0450] The gate of the eighth transistor T8 is electrically connected to the first light emitting control terminal EM1(n+b) of the n+bth stage, the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal ELVSS; b is a positive integer;

[0451] The gate of the fourth transistor T4 is electrically connected to the n-1th stage gate driving terminal G(n-1), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the third node N3; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0452] The driving circuit includes a driving transistor T0;

[0453] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0454] The second light emitting control circuit includes a seventh transistor T7; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst;

[0455] The gate of the seventh transistor T7 is electrically connected to the n-th stage first light emitting control terminal EM1(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2;

[0456] The gate of the ninth transistor T9 is electrically connected to the n-th stage gate driving terminal G(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2;

[0457] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0458] The voltage control circuit includes a first capacitor C1;

[0459] A first end of the first capacitor C1 is electrically connected to the fourth node N4, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0460] The third initialization circuit includes a tenth transistor T10;

[0461] The gate of the tenth transistor T10 is electrically connected to the n-th gate driving terminal G(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1; the third initial voltage terminal I3 is used to provide a third initial voltage Vi3.

[0462] exist Figure 22 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0463] exist Figure 22 In at least one embodiment of the pixel circuit shown, the second terminal of C1 may be electrically connected to the control voltage terminal VJ instead.

[0464] exist Figure 22In at least one embodiment of the pixel circuit shown, T7 is controlled by EM1(n), T8 is controlled by EM1(n+b), T2 is controlled by EM3(n-4), T3 is controlled by EM3(n), T4 is controlled by G(n-1), T9 and T10 are controlled by G(n), a third light-emitting control signal is provided to EM3(n-4) and EM3(n) by the same GOA module, and a gate drive signal is provided to G(n-1) and G(n) by the same GOA module, so as to reduce the number of GOA modules used.

[0465] like Figure 23 As shown, the utility model Figure 22 When at least one embodiment of the pixel circuit shown is in operation, a refresh frame may include an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10, and a first light-emitting phase t4, which are arranged in sequence;

[0466] In the initialization phase t11, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a low voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T8 is turned on, T4 is turned on, T2 is turned on, T1 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1, so that T0 can be turned on when the compensation phase t12 begins;

[0467] In the compensation phase t12, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a high voltage signal, G(n) provides a low voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T9 is turned on, DT provides a data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 is connected to N3; T10 is turned on, I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0468] At the beginning of the compensation phase t12, T0 is turned on and Cst is charged through Vdata until T0 is turned off and the potential of the first node N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0.

[0469] In the first hysteresis improvement phase t13, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a low voltage signal, T3 and T2 are turned on, I1 provides a first initial voltage Vi1 to N3, T0 is turned on, and Vi1 is written to the second node N2 to improve the hysteresis phenomenon of T0;

[0470] In the first voltage control stage t10, the potential of the n+b-th level first light-emitting control signal provided by EM1(n+b) drops from a high voltage to a low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage of N1 and the flicker phenomenon;

[0471] In the first light-emitting stage t14, EM1(n) provides a low voltage signal, EM(n+b) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0472] This utility model Figure 22 When at least one embodiment of the pixel circuit shown is in operation, a holding frame may include a second hysteresis improvement phase, a second voltage control phase, and a second light emitting phase that are sequentially arranged;

[0473] In the second hysteresis improvement stage, T3 and T2 are turned on, I1 provides the first initial voltage Vi1 to N3, T0 is turned on, and Vi1 is written to the second node N2 to improve the hysteresis phenomenon of T0;

[0474] In the second voltage control stage, the potential of the n+b-th level first light-emitting control signal provided by EM1(n+b) drops from a high voltage to a low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage of N1 and the flicker phenomenon;

[0475] In the second light-emitting stage, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0476] like Figure 24 As shown, in Figure 7C Based on at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1;

[0477] The first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the first initialization circuit includes a third transistor T3;

[0478] The gate of the first transistor T1 is electrically connected to the n-th stage second light emitting control terminal EM2(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;

[0479] The gate of the second transistor T2 is electrically connected to the n-4th stage third light emitting control terminal EM3 (n-4), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3;

[0480] The gate of the third transistor T3 is electrically connected to the n-th stage third light-emitting control terminal EM3(n), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0481] The first light emitting control circuit includes an eighth transistor T8, and the second initialization circuit includes a fourth transistor T4;

[0482] The gate of the eighth transistor T8 is electrically connected to the first light emitting control terminal EM1(n+b) of the n+bth stage, the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal ELVSS; b is a positive integer;

[0483] The gate of the fourth transistor T4 is electrically connected to the n-1th stage gate driving terminal G(n-1), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0484] The driving circuit includes a driving transistor T0;

[0485] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0486] The second light emitting control circuit includes a seventh transistor T7; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst;

[0487] The gate of the seventh transistor T7 is electrically connected to the n-th stage first light emitting control terminal EM1(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2;

[0488] The gate of the ninth transistor T9 is electrically connected to the n-th stage gate driving terminal G(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2;

[0489] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0490] The voltage control circuit includes a first capacitor C1;

[0491] A first end of the first capacitor C1 is electrically connected to the fourth node N4, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0492] The third initialization circuit includes a tenth transistor T10;

[0493] The gate of the tenth transistor T10 is electrically connected to the n-th gate driving terminal G(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1; the third initial voltage terminal I3 is used to provide a third initial voltage Vi3.

[0494] exist Figure 24 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0495] exist Figure 24 In at least one embodiment of the pixel circuit shown, the second terminal of C1 may be electrically connected to the control voltage terminal VJ instead.

[0496] exist Figure 24 In at least one embodiment of the pixel circuit shown, T7 is controlled by EM1(n), T8 is controlled by EM1(n+b), T2 is controlled by EM3(n-4), T3 is controlled by EM3(n), T4 is controlled by G(n-1), T9 and T10 are controlled by G(n), a third light-emitting control signal is provided to EM3(n-4) and EM3(n) by the same GOA module, and a gate drive signal is provided to G(n-1) and G(n) by the same GOA module, so as to reduce the number of GOA modules used.

[0497] like Figure 25 As shown, the utility model Figure 24 When at least one embodiment of the pixel circuit shown is in operation, a refresh frame may include an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10, and a first light-emitting phase t4, which are arranged in sequence;

[0498] In the initialization phase t11, EM1(n) provides a high voltage signal, EM1(n+b) provides a low voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a low voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T8 is turned on, T4 is turned on, T2 is turned on, T1 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1, so that T0 can be turned on when the compensation phase t12 begins;

[0499] In the compensation phase t12, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a high voltage signal, G(n) provides a low voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T9 is turned on, DT provides a data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 is connected to N3; T10 is turned on, I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0500] At the beginning of the compensation phase t12, T0 is turned on and Cst is charged through Vdata until T0 is turned off and the potential of the first node N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0.

[0501] In the first hysteresis improvement phase t13, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a low voltage signal, T3 and T2 are turned on, I1 provides a first initial voltage Vi1 to N3, T0 is turned on, and Vi1 is written to the second node N2 to improve the hysteresis phenomenon of T0;

[0502] In the first voltage control stage t10, the potential of the n+b-th level first light-emitting control signal provided by EM1(n+b) drops from a high voltage to a low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage of N1 and the flicker phenomenon;

[0503] In the first light-emitting stage t14, EM1(n) provides a low voltage signal, EM(n+b) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0504] This utility model Figure 24 When at least one embodiment of the pixel circuit shown is in operation, a holding frame may include a second hysteresis improvement phase, a second voltage control phase, and a second light emitting phase that are sequentially arranged;

[0505] In the second hysteresis improvement stage, T3 and T2 are turned on, I1 provides the first initial voltage Vi1 to N3, T0 is turned on, and Vi1 is written to the second node N2 to improve the hysteresis phenomenon of T0;

[0506] In the second voltage control stage, the potential of the n+b-th level first light-emitting control signal provided by EM1(n+b) drops from a high voltage to a low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage of N1 and the flicker phenomenon;

[0507] In the second light-emitting stage, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0508] The refresh frame includes a compensation phase and a first hysteresis improvement phase which are arranged in sequence; the driving method applied to the above pixel circuit includes:

[0509] During the compensation phase, the first control circuit controls the first node and the fourth node to be connected under the control of the first control signal; and the second control circuit controls the fourth node and the third node to be connected under the control of the second control signal.

[0510] In the first hysteresis improvement stage, the first initialization circuit writes the first initial voltage to the fourth node under the control of the first initial control signal, and the second control circuit controls the connection between the fourth node and the third node under the control of the second control signal; or, in the first hysteresis improvement stage, the first initialization circuit writes the first initial voltage to the third node under the control of the first initial control signal.

[0511] Optionally, the driving method further includes:

[0512] In the first hysteresis improvement stage, the driving circuit controls the connection between the second node and the third node under the control of the potential of the first node.

[0513] Optionally, the refresh frame further includes a first voltage control stage and a first light-emitting stage, which are successively provided after the first hysteresis improvement stage; the pixel circuit further includes a voltage control circuit, a light-emitting element, a first light-emitting control circuit and a second light-emitting control circuit; and the driving method further includes:

[0514] In the first voltage control stage, the potential of the control voltage provided by the control voltage terminal is pulled down, and the voltage control circuit controls the potential of the fourth node to become low according to the control voltage;

[0515] In the first light-emitting stage, the second light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal; the first light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the light-emitting control signal.

[0516] Optionally, the pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node, respectively, and is configured to control the potential of the fourth node according to the potential of the third node; the refresh frame further includes a first light-emitting phase provided after the first hysteresis improvement phase; and the driving method further includes:

[0517] When the first light emitting phase starts, the voltage control circuit controls the potential of the fourth node to become low according to the potential of the third node.

[0518] Optionally, the holding frame includes a second hysteresis improvement phase; and the driving method includes:

[0519] In the second hysteresis improvement stage, the first initialization circuit writes the first initial voltage into the fourth node under the control of the first initial control signal, and the second control circuit controls the fourth node to be connected to the third node under the control of the second control signal.

[0520] Optionally, the holding frame further includes a second voltage control stage and a second light-emitting stage, which are successively arranged after the second hysteresis improvement stage; the pixel circuit further includes a voltage control circuit, a light-emitting element, a first light-emitting control circuit and a second light-emitting control circuit; and the driving method further includes:

[0521] In the second voltage control stage, the potential of the control voltage provided by the control voltage terminal decreases, and the voltage control circuit controls the potential of the fourth node to become lower according to the control voltage;

[0522] In the second light-emitting stage, the second light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal; the first light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the light-emitting control signal.

[0523] Optionally, the pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node, respectively, and is configured to control the potential of the fourth node according to the potential of the third node; the holding frame further includes a second light-emitting stage provided after the second hysteresis improvement stage; and the driving method further includes:

[0524] When the second light emitting phase starts, the voltage control circuit controls the potential of the fourth node to become low according to the potential of the third node.

[0525] The display device described in the embodiment of the present invention includes the above-mentioned pixel circuit.

[0526] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a driving circuit, a first control circuit, a second control circuit and a first initialization circuit; The control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, the second end of the driving circuit is electrically connected to the third node, and the driving circuit is used to generate a driving current under the control of the potential of the first node; The first control circuit is electrically connected to the first control terminal, the first node and the fourth node respectively, and is used to control the connection between the first node and the fourth node under the control of the first control signal provided by the first control terminal; The second control circuit is electrically connected to the second control terminal, the fourth node and the third node respectively, and is used to control the fourth node to be connected to the third node under the control of the second control signal provided by the second control terminal; The first initialization circuit is electrically connected to the first initial control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the fourth node and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal.

2. The pixel circuit according to claim 1, wherein: Also comprising a second initialization circuit; The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of a second initial control signal provided by the second initial control terminal.

3. The pixel circuit according to claim 1, wherein: Also comprising a second initialization circuit; The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the fourth node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the fourth node under the control of the second initial control signal provided by the second initial control terminal.

4. The pixel circuit according to claim 1, wherein: Also includes a light emitting element, a first light emitting control circuit and a second initialization circuit; The first light-emitting control circuit is electrically connected to the first light-emitting control signal terminal, the third node and the first electrode of the light-emitting element respectively, and is used to control the third node to be connected to the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control signal terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first pole of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that: Also included is a voltage control circuit; The voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, and is used to control the potential of the fourth node according to the control voltage provided by the control voltage terminal; or, The voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; or, The pixel circuit also includes a light-emitting element and a first light-emitting control circuit. The voltage control circuit is electrically connected to the fourth node and the first light-emitting control signal terminal, respectively, and is used to control the potential of the fourth node according to the first light-emitting control signal provided by the first light-emitting control signal terminal.

6. The pixel circuit according to claim 2, characterized in that: The first control terminal is an n-th level scanning terminal, the second control terminal is an n-th level gate driving terminal, the first initial control terminal is an n+y-th level gate driving terminal, and the second initial voltage terminal is an nx-th level scanning terminal; n, x and y are all positive integers.

7. The pixel circuit according to claim 2 or 3, characterized in that: The first control end is an n-th level gate driving end, the second control end includes an n-th level scanning end and an n+y-th level scanning end, the first initial control end is an n+y-th level scanning end, and the second initial control end is an nx-th level scanning end; n, x and y are all positive integers.

8. The pixel circuit according to claim 2 or 3, characterized in that: The first control end includes an n-th level scanning end and an nx-th level scanning end, the second control end is an n-th level gate driving end, the first initial control end is an n+y-th level gate driving end, and the second initial control end is an nx-th level scanning end; n, x and y are all positive integers.

9. The pixel circuit according to claim 3, characterized in that: The first control end is the nth level second light emitting control end, the second control end is the nath level third light emitting control end, the first initial control end is the nth level third light emitting control end, and the second initial control end is the nbth level gate driving end; n, a and b are all positive integers.

10. The pixel circuit according to claim 3, characterized in that: The first control end is the nath level second light emitting control end, the second control end is the nth level second light emitting control end, the first initial control end is the n+bth level gate driving end, and the second initial control end is the ncth level second light emitting control end; n, a, b and c are all positive integers.

11. The pixel circuit according to claim 4, characterized in that: The first control terminal is the nth level second light-emitting control terminal, the second control terminal is the nath level third light-emitting control terminal, the first initial control terminal is the nth level third light-emitting control terminal, the first light-emitting control signal terminal is the n+bth level first light-emitting control terminal, and the second initial control terminal is the ncth level gate driving terminal; n, a, b and c are all positive integers.

12. The pixel circuit according to claim 6, characterized in that: The first control circuit includes a first transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor; The gate of the first transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node; The gate of the second transistor is electrically connected to the nth stage gate driving terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node; The gate of the third transistor is electrically connected to the n+yth stage gate driving terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node; A gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, a first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.

13. The pixel circuit according to claim 7, characterized in that: The first control circuit includes a first transistor, the second control circuit includes a second transistor and a fifth transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor; The gate of the first transistor is electrically connected to the nth gate driving terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node; The gate of the second transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node; The gate of the fifth transistor is electrically connected to the n+yth stage scanning terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the third node; The gate of the third transistor is electrically connected to the n+yth level scanning terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node; The gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node or the first node.

14. The pixel circuit according to claim 8, characterized in that: The first control circuit includes a first transistor and a sixth transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor; The gate of the first transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node; The gate of the sixth transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the fourth node; The gate of the second transistor is electrically connected to the nth stage gate driving terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node; The gate of the third transistor is electrically connected to the n+yth stage gate scanning terminal, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node; The gate of the fourth transistor is electrically connected to the nx-th stage scanning terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first node or the fourth node.

15. The pixel circuit according to any one of claims 1 to 4, characterized in that: The first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first initialization circuit includes a third transistor; The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node; The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node; A gate of the third transistor is electrically connected to the first initial control terminal, a first electrode of the third transistor is electrically connected to the first initial voltage terminal, and a second electrode of the third transistor is electrically connected to the fourth node.

16. The pixel circuit according to claim 4, characterized in that: The first light emitting control circuit includes an eighth transistor, and the second initialization circuit includes a fourth transistor; The gate of the eighth transistor is electrically connected to the first light-emitting control signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element; The gate of the fourth transistor is electrically connected to the second initial control terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

17. The pixel circuit according to claim 5, characterized in that: The voltage control circuit includes a first capacitor; The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the control voltage terminal; or, The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the third node; or, The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the first light emitting control signal end.

18. The pixel circuit according to claim 1, wherein: It also includes a light emitting element, a first light emitting control circuit, a second light emitting control circuit, a data writing circuit and an energy storage circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node and the first electrode of the light-emitting element respectively, and is used to control the third node to be connected to the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light emitting control signal; The data writing circuit is electrically connected to the n-th level scanning terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the n-th level scanning signal provided by the n-th level scanning terminal; n is a positive integer; The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the DC voltage end, and the energy storage circuit is used to store electrical energy.

19. The pixel circuit according to claim 18, characterized in that: It also includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the control voltage terminal; the energy storage circuit includes a storage capacitor; a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the DC voltage terminal; The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1 fF.

20. The pixel circuit according to claim 4, characterized in that: It also includes a light emitting element, a second light emitting control circuit, a data writing circuit and an energy storage circuit; The second light-emitting control circuit is electrically connected to the second light-emitting control signal terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal provided by the second light-emitting control signal terminal; The data writing circuit is electrically connected to the n-th level gate driving terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the n-th level gate driving signal provided by the n-th level gate driving terminal; n is a positive integer; The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the DC voltage end, and the energy storage circuit is used to store electrical energy.

21. The pixel circuit according to claim 20, characterized in that: It also includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the third node; the energy storage circuit includes a storage capacitor; a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to the DC voltage terminal; The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1 fF.

22. The pixel circuit according to claim 18 or 20, characterized in that: Also comprising a third initialization circuit; The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.

23. The pixel circuit according to claim 18, characterized in that: The second light emitting control circuit includes a seventh transistor, the first light emitting control circuit includes an eighth transistor; the data writing circuit includes a ninth transistor; the energy storage circuit includes a storage capacitor; The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node; The gate of the eighth transistor is electrically connected to the light emitting control terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element; The gate of the ninth transistor is electrically connected to the n-th stage scanning terminal, the first electrode of the ninth transistor is electrically connected to the data line, and the second electrode of the ninth transistor is electrically connected to the second node; The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage end.

24. The pixel circuit according to claim 20, characterized in that: The second light emitting control circuit includes a seventh transistor; the data writing circuit includes a ninth transistor; the energy storage circuit includes a storage capacitor; The gate of the seventh transistor is electrically connected to the second light emitting control signal terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node; The gate of the ninth transistor is electrically connected to the nth gate driving terminal, the first electrode of the ninth transistor is electrically connected to the data line, and the second electrode of the ninth transistor is electrically connected to the second node; The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a DC voltage end.

25. The pixel circuit according to claim 22, characterized in that: The third initialization circuit includes a tenth transistor; The gate of the tenth transistor is electrically connected to the third initial control terminal, the first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

26. A display device, characterized in that: Comprising a pixel circuit as claimed in any one of claims 1 to 25.

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