Display device

Abstract

A display device is provided. The display device includes: a pixel; a first scan driving circuit that transmits a first scan signal to the pixel based on a first gate voltage, a second gate voltage having a lower level than that of the first gate voltage, and a first clock signal; and a second scan driving circuit that transmits a second scan signal to the pixel based on a third gate voltage having a level different from that of the first gate voltage, a fourth gate voltage having a level lower than that of the third gate voltage, and a second clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0039033 filed in the Korean Intellectual Property Office (KIPO) on March 24, 2023, and Korean Patent Application No. 10-2023-0066477 filed in the Korean Intellectual Property Office on May 23, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display device. Background Art

[0004] The display device is configured to visually display data. The display device can be used as a display for a small product such as a mobile phone or a large product such as a television.

[0005] The display device includes a substrate divided into a display area and a non-display area. The gate line and the data line are insulated from each other in the display area. A plurality of pixel areas are included in the display area, and a plurality of pixels arranged in the plurality of pixel areas receive electrical signals from the gate lines and data lines that cross each other and emit light to display an image to the outside. A thin film transistor and a pixel electrode electrically connected to the thin film transistor are provided in each of the plurality of pixel areas, and a relative electrode is provided in common to the plurality of pixel areas. Various lines configured to transmit electrical signals to pixels in the display area, pads to which gate drivers, data drivers, and controllers are connected, etc. may be provided in the non-display area.

[0006] Recently, the use of display devices has been diversified. In addition, as display devices become thinner and lighter, their use has also been further expanded. Recently, as the use of display devices has been diversified, various attempts have been made to improve the quality of display devices. Utility Model Content

[0007] Embodiments include a display device with reduced power consumption.

[0008] The technical objectives to be achieved by the present disclosure are not limited to the above-mentioned technical objectives, and other technical objectives will be clearly understood by a person of ordinary skill in the art from the following description.

[0009] Additional aspects will be set forth in part in the detailed description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments presented in the disclosure.

[0010] According to an embodiment, a display device may include: a substrate including a display area and a peripheral area adjacent to the display area; a pixel in the display area; a first conductive line extending in a first direction on one side of the peripheral area and a first gate voltage being applied to the first conductive line; a second conductive line extending in the first direction on one side of the peripheral area and a second gate voltage having a level lower than that of the first gate voltage being applied to the second conductive line; a first clock signal line extending in the first direction on one side of the peripheral area and a first clock signal being applied to the first clock signal line; a third conductive line extending in the first direction on one side of the peripheral area and a third gate voltage having a level different from that of the first gate voltage being applied to the third conductive line; and a fourth conductive line extending in the first direction on one side of the peripheral area and a third gate voltage having a level different from that of the first gate voltage being applied to the third conductive line. A fourth conductor extending in the first direction on one side of the peripheral area, and a fourth gate voltage having a level lower than that of the third gate voltage is applied to the fourth conductor; a second clock signal line extending in the first direction on one side of the peripheral area, and a second clock signal is applied to the second clock signal line; a first scan drive circuit, which is arranged on one side of the peripheral area, is electrically connected to the first conductor, the second conductor and the first clock signal line, and transmits a first scan signal to the pixel based on the first gate voltage, the second gate voltage and the first clock signal; and a second scan drive circuit, which is arranged on one side of the peripheral area, is electrically connected to the third conductor, the fourth conductor and the second clock signal line, and transmits a second scan signal to the pixel based on the third gate voltage, the fourth gate voltage and the second clock signal.

[0011] According to an embodiment, a pixel may include: a display element including an anode and a cathode; a first transistor, which controls the amount of driving current flowing to the display element according to a gate-source voltage of the first transistor; a first capacitor, which includes a first electrode and a second electrode, the first electrode being connected to the gate of the first transistor; a second transistor, which transmits a data voltage to the second electrode of the first capacitor in response to a first scan signal; and a third transistor, which transmits a first initialization voltage to the anode of the display element in response to a second scan signal.

[0012] According to an embodiment, a level of the first gate voltage may be higher than a level of the third gate voltage.

[0013] According to an embodiment, the first transistor and the third transistor may each be a p-type metal oxide semiconductor field effect transistor (MOSFET), and the second transistor may be an n-type MOSFET.

[0014] According to an embodiment, the pixel may further include a fourth transistor applying the first voltage to a source of the first transistor in response to the second scan signal.

[0015] According to an embodiment, a level of the fourth gate voltage may be different from a level of the second gate voltage.

[0016] According to an embodiment, the display device may further include: a third clock signal line, the third clock signal line extending in the first direction on one side of the peripheral area, and the third clock signal is applied to the third clock signal line; a fourth clock signal line, the fourth clock signal line extending in the first direction on one side of the peripheral area, and the fourth clock signal is applied to the fourth clock signal line; a fifth clock signal line, the fifth clock signal line extending in the first direction on one side of the peripheral area, and the fifth clock signal is applied to the fifth clock signal line; a sixth clock signal line, the sixth clock signal line extending in the first direction on one side of the peripheral area, and the sixth clock signal is applied to the sixth clock signal line; a third scan drive circuit, the third scan drive circuit being arranged on one side of the peripheral area, being electrically connected to the first conductive wire, the second conductive wire, and the third clock signal line, and based on the first gate voltage, the second gate voltage, and the third gate voltage, a first emission control driving circuit, the first emission control driving circuit being arranged on one side of the peripheral area, being electrically connected to the third wire, the fourth wire and the fifth clock signal line, and transmitting the first emission control signal to the pixel based on the third gate voltage, the fourth gate voltage and the fifth clock signal; and a second emission control driving circuit, the second emission control driving circuit being arranged on one side of the peripheral area, being electrically connected to the third wire, the fourth wire and the sixth clock signal line, and transmitting the second emission control signal to the pixel based on the third gate voltage, the fourth gate voltage and the sixth clock signal.

[0017] According to an embodiment, a pixel may include: a display element including an anode and a cathode; a first transistor, the first transistor controlling the amount of driving current flowing to the display element according to a gate-source voltage of the first transistor; a first capacitor, the first capacitor including a first electrode and a second electrode, the first electrode being connected to the gate of the first transistor; a second transistor, the second transistor transmitting a data voltage to the second electrode of the first capacitor in response to a first scan signal; a third transistor, the third transistor transmitting a first initialization voltage to the anode of the display element in response to a second scan signal; and a fourth transistor, the fourth transistor transmitting the first voltage to the anode of the display element in response to the second scan signal. applied to the source of the first transistor; a fifth transistor, which applies a second voltage to the second electrode of the first capacitor in response to a third scan signal; a sixth transistor, which connects the source of the first transistor to the drain of the first transistor in response to the third scan signal; a seventh transistor, which transmits a second initialization voltage to the gate of the first transistor in response to the fourth scan signal; an eighth transistor, which applies a driving voltage to the source of the first transistor in response to the first emission control signal; and a ninth transistor, which connects the drain of the first transistor to the anode of the display element in response to the second emission control signal.

[0018] According to an embodiment, the pixel may further include a second capacitor including a third electrode connected to the second electrode of the first capacitor and a fourth electrode to which the driving voltage is applied.

[0019] According to an embodiment, the first transistor, the third transistor, the fourth transistor, the eighth transistor, and the ninth transistor may each be a p-type MOSFET, and the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor may each be an n-type MOSFET.

[0020] According to an embodiment, the first transistor may include a first upper gate connected to the first electrode of the first capacitor and a first lower gate to which a driving voltage is applied, the second transistor may include a second upper gate and a second lower gate connected to each other and to which a first scan signal is applied, the fifth transistor may include a third upper gate and a third lower gate connected to each other and to which a third scan signal is applied, the sixth transistor may include a fourth upper gate and a fourth lower gate connected to each other and to which a third scan signal is applied, and the seventh transistor may include a fifth upper gate and a fifth lower gate connected to each other and to which a fourth scan signal is applied.

[0021] According to an embodiment, the fifth clock signal and the sixth clock signal may be substantially consistent, the first emission control driving circuit may also receive a first start signal, and based on the third gate voltage, the fourth gate voltage, the fifth clock signal and the first start signal, transmit the first emission control signal to the pixel, and the second emission control driving circuit may also receive a second start signal different from the first start signal, and based on the third gate voltage, the fourth gate voltage, the sixth clock signal and the second start signal, transmit the second emission control signal to the pixel.

[0022] According to an embodiment, a display device may include: a pixel connected to: a first scan line to a fourth scan line that transmits a first scan signal to a fourth scan signal to the pixel, respectively; a first emission control line and a second emission control line that transmits a first emission control signal and a second emission control signal to the pixel, respectively; a data line that transmits a data voltage to the pixel; a power line that transmits a driving voltage to the pixel; a first voltage line and a second voltage line that transmits a first initialization voltage and a second initialization voltage to the pixel, respectively; and a third voltage line and a fourth voltage line that transmits the first voltage and the second voltage to the pixel, respectively. The pixel may include: a display element including an anode and a cathode; a first capacitor including a first electrode and a second electrode; a second capacitor including a third electrode connected to the second electrode of the first capacitor and a fourth electrode connected to a power line; a first transistor including a gate connected to the first electrode of the first capacitor, a source connected to the power line, and a drain; a second transistor including a gate connected to a first scan line and connecting a data line to the second electrode of the first capacitor in response to a first scan signal; a third transistor including a gate connected to a third scan line and connecting the gate of the first transistor to the drain of the first transistor in response to the third scan signal; and a fourth transistor including a gate connected to a fourth scan line and connecting the first voltage line to the drain of the first transistor in response to the fourth scan signal. to the gate of the first transistor; a fifth transistor, the fifth transistor including a gate connected to the third scan line, and connecting the third voltage line to the second electrode of the first capacitor in response to the third scan signal; a sixth transistor, the sixth transistor including a gate connected to the first emission control line, and connecting the power line to the source of the first transistor in response to the first emission control signal; a seventh transistor, the seventh transistor including a gate connected to the second emission control line, and connecting the drain of the first transistor to the anode of the display element in response to the second emission control signal; an eighth transistor, the eighth transistor including a gate connected to the second scan line, and connecting the second voltage line to the anode of the display element in response to the second scan signal; and a ninth transistor, the ninth transistor including a gate connected to the second scan line, and connecting the fourth voltage line to the source of the first transistor in response to the second scan signal.

[0023] According to an embodiment, the first, sixth, seventh, eighth and ninth transistors may be p-type metal oxide semiconductor field effect transistors (MOSFETs), and the second, third, fourth and fifth transistors may be n-type MOSFETs.

[0024] According to an embodiment, the display device may further include: a substrate including a display area and a peripheral area adjacent to the display area, wherein the pixels are arranged in the display area; a first scan drive circuit, which is arranged on one side of the peripheral area, receives a first gate voltage, a second gate voltage having a level lower than that of the first gate voltage, and a first clock signal, and outputs a first scan signal based on the first gate voltage, the second gate voltage, and the first clock signal; a second scan drive circuit, which is arranged on one side of the peripheral area, receives a third gate voltage having a level different from that of the first gate voltage, a fourth gate voltage having a level lower than that of the third gate voltage, and a second clock signal, and outputs a second scan signal based on the third gate voltage, the fourth gate voltage, and the second clock signal; a third scan drive circuit, which is arranged on one side of the peripheral area, receives the first gate voltage, a first emission control driving circuit, the first emission control driving circuit being arranged on one side of the peripheral area, receiving the third gate voltage, the fourth gate voltage and the fourth clock signal, and outputting the first emission control signal based on the third gate voltage, the fourth gate voltage and the fourth clock signal; a second emission control driving circuit, the second emission control driving circuit being arranged on one side of the peripheral area, receiving the third gate voltage, the fourth gate voltage and the fifth clock signal, and outputting the third scanning signal based on the first gate voltage, the second gate voltage and the third clock signal; a fourth scanning driving circuit, the fourth scanning driving circuit being arranged on one side of the peripheral area, receiving the first gate voltage, the second gate voltage and the fourth clock signal, and outputting the fourth scanning signal based on the first gate voltage, the second gate voltage and the fourth clock signal; a first emission control driving circuit, the first emission control driving circuit being arranged on one side of the peripheral area, receiving the third gate voltage, the fourth gate voltage and the fifth clock signal, and outputting the first emission control signal based on the third gate voltage, the fourth gate voltage and the fifth clock signal; and a second emission control driving circuit, the second emission control driving circuit being arranged on one side of the peripheral area, receiving the third gate voltage, the fourth gate voltage and the sixth clock signal, and outputting the second emission control signal based on the third gate voltage, the fourth gate voltage and the sixth clock signal.

[0025] According to an embodiment, a level of the first gate voltage may be higher than a level of the third gate voltage.

[0026] According to an embodiment, a level of the fourth gate voltage may be different from a level of the second gate voltage.

[0027] According to an embodiment, the fifth clock signal and the sixth clock signal may be substantially consistent, the first emission control driving circuit may also receive a first start signal, and output a first emission control signal based on the third gate voltage, the fourth gate voltage, the fifth clock signal and the first start signal, and the second emission control driving circuit may also receive a second start signal different from the first start signal, and output a second emission control signal based on the third gate voltage, the fourth gate voltage, the sixth clock signal and the second start signal.

[0028] According to an embodiment, the first transistor may further include a lower gate connected to the power line.

[0029] According to an embodiment, a gate of each of the second to fifth transistors may include an upper gate and a lower gate connected to each other.

[0030] Other aspects, features, and advantages of the present disclosure will become better understood from the detailed description, claims, and accompanying drawings.

[0031] These general and specific aspects may be practiced using a system, a method, a computer program, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a schematic block diagram of a display device according to an embodiment;

[0034] Figure 2 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0035] Figure 3 is a schematic block diagram of a wiring portion and a gate driver according to an embodiment;

[0036] Figure 4 is a schematic block diagram of a wiring portion and a gate driver according to another embodiment; and

[0037] Figure 5 is a schematic diagram of an equivalent circuit of a pixel according to another embodiment. DETAILED DESCRIPTION

[0038] With reference now to embodiments in detail, examples of embodiments are illustrated in the accompanying drawings, wherein, throughout this disclosure, similar reference numerals refer to similar elements. In this regard, embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described below only with reference to the figures to explain the various aspects of description. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0039] Since the present description allows various changes and many embodiments, specific embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the present disclosure and methods for achieving them will become clear with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0040] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. When the embodiments are described with reference to the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals.

[0041] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0042] Throughout the following embodiments, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0043] It will be further understood that the terms “include” and / or “comprise” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0044] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intervening elements.

[0045] In addition, the size of the elements in the drawings may be enlarged or reduced for the convenience of explanation. For example, since the size and thickness of the elements in the drawings are arbitrarily illustrated for the convenience of explanation, the present disclosure is not limited thereto.

[0046] When a specific embodiment can be implemented in different ways, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially at the same time or in the reverse order of the described order.

[0047] Throughout the present disclosure, the expression “A and / or B” means only A, only B, or both A and B. In the present specification, the expression “at least one of A and B” means only A, only B, or both A and B.

[0048] It will be further understood that when layers, regions, or elements are referred to as being connected to each other, they may be directly connected to each other or indirectly connected to each other with intervening layers, regions, or elements therebetween. For example, when layers, regions, or elements are referred to as being electrically connected to each other, they may be directly electrically connected to each other or indirectly electrically connected to each other with intervening layers, regions, or elements therebetween.

[0049] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0050] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined in this specification, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0051] Figure 1 is a schematic block diagram of a display device 1 according to an embodiment.

[0052] refer to Figure 1 , the display device 1 may include a substrate 100 , a gate driver 200 , a wiring portion 210 , a printed circuit board (PCB) 300 , a flexible PCB (FPCB) 310 , and a data driver 320 .

[0053] The substrate 100 may include a display area DA and a peripheral area PA arranged adjacent to the display area DA. The display area DA may be an area in which an image is displayed. Pixels PX including at least one thin film transistor and a display element may be arranged in the display area DA. The peripheral area PA may be an area in which an image is not displayed. The gate line GL, the data line DL, the gate driver 200, and the wiring portion 210 may be arranged in the peripheral area PA so that voltages and signals are applied to the pixels PX of the display area DA.

[0054] One side of the peripheral area PA may be bonded to the FPCB 310 and connected to the PCB 300. The data driver 320 mounted on the FPCB 310 may be configured to transmit data signals (or data voltages) to the pixels PX of the display area DA through the data lines DL. Figure 1 As shown in the figure, the data line DL may extend in a first direction (e.g., ±y direction) and may be connected to the pixel PX of the display area DA, and the gate line GL may extend in a second direction (e.g., ±x direction) and may be connected to the pixel PX of the display area DA.

[0055] The gate driver 200 may be arranged on one side of the peripheral area PA in the second direction (e.g., ±x direction). The gate driver 200 may be integrated in the peripheral area PA. The gate driver 200 may include a plurality of stages ST configured to sequentially output gate signals to the gate lines GL. Each of the plurality of stages ST is connected to at least one gate line GL and is configured to transmit the gate signal to the pixel PX.

[0056] In an embodiment, each of the plurality of stages ST may include a plurality of driving circuits. For example, as described below Figure 3 As shown in FIG. 1 , the stage ST may include at least one scan driving circuit and at least one emission control driving circuit. The gate line GL connected to the scan driving circuit may be referred to as a scan line. The gate line GL connected to the emission control driving circuit may be referred to as an emission control line. The gate signal may include a scan signal and an emission control signal. The scan driving circuit may be connected to the scan line and configured to transmit the scan signal to the pixel PX, and the emission control driving circuit may be connected to the emission control line and configured to transmit the emission control signal to the pixel PX.

[0057] The wiring portion 210 may be arranged on one side of the peripheral area PA in the second direction (e.g., ±x direction). The wiring portion 210 may be integrated in the peripheral area PA. The wiring portion 210 may be configured to transmit a gate voltage and / or a clock signal to the stage ST of the gate driver 200. For example, as described below Figure 3As shown in FIG. 2 , the wiring portion 210 may include at least one conductive line and at least one clock signal line. The at least one conductive line may be configured to transmit a gate voltage to the stage ST of the gate driver 200, and the clock signal line may be configured to transmit a clock signal to the stage ST of the gate driver 200.

[0058] The PCB 300 located on one side of the FPCB 310 may include a signal controller (not shown). The signal controller may be configured to generate various signals for displaying an image in the display area DA. In order to control the gate driver 200, the wiring portion 210, and the data driver 320, the signal controller may be configured to transmit a control signal to the gate driver 200, the wiring portion 210, and the data driver 320.

[0059] Figure 2 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment.

[0060] refer to Figure 2 , the pixel PX may include a pixel circuit PC and a display element LED electrically connected to the pixel circuit PC. The pixel circuit PC may be connected to a first scan line GWL configured to transmit a first scan signal GW, a second scan line GBL configured to transmit a second scan signal GB, a third scan line GCL configured to transmit a third scan signal GC, a fourth scan line GIL configured to transmit a fourth scan signal GI, a first emission control line EML1 configured to transmit a first emission control signal EM1, and a second emission control line EML2 configured to transmit a second emission control signal EM2. The pixel circuit PC may be connected to a data line DL configured to transmit a data voltage Dm, a first voltage line VL1 configured to transmit a first initialization voltage VINT, a second voltage line VL2 configured to transmit a second initialization voltage VAINT, a third voltage line VL3 configured to transmit a first voltage VREF, a fourth voltage line VL4 configured to transmit a second voltage VOBS, and a power line PL configured to transmit a first driving voltage ELVDD. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, and a first capacitor C1 and a second capacitor C2. The display element LED may be an organic light emitting diode (OLED). The cathode of the display element LED may be a common electrode to which the second driving voltage ELVSS is applied.

[0061] The first transistor T1 may be a driving transistor in which the amount of drain current is determined according to the gate-source voltage, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may all be switch transistors configured to be turned on / off according to the gate-source voltage (substantially the gate voltage). The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may all be thin film transistors.

[0062] In an embodiment, if Figure 2 As shown in the figure, the first transistor T1, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 can all be provided as p-channel metal oxide semiconductor field effect transistors (MOSFET) (PMOS). The second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can all be provided as n-channel MOSFET (NMOS).

[0063] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 can all be oxide semiconductor thin film transistors including a semiconductor layer formed of an oxide semiconductor or silicon semiconductor thin film transistors including a semiconductor layer formed of polycrystalline silicon.

[0064] The first capacitor C1 may be connected between the gate of the first transistor T1 and the second transistor T2. The first capacitor C1 may have a first electrode CE1 connected to the gate of the first transistor T1 and a second electrode CE2 connected to the second transistor T2.

[0065] The second capacitor C2 may be connected between the first capacitor C1 and the power line PL. The second capacitor C2 may have a third electrode CE3 connected to the second electrode CE2 of the first capacitor C1 and a fourth electrode CE4 connected to the power line PL.

[0066] The first transistor T1 may be configured to control the amount of the driving current Id flowing from the power line PL to the display element LED according to the gate-source voltage of the first transistor T1. The display element LED may be configured to emit light with a specific brightness according to the driving current Id. The first transistor T1 may have a gate connected to the first electrode CE1 of the first capacitor C1, a source S connected to the power line PL, and a drain D electrically connected to the display element LED.

[0067] The second transistor T2 may have a gate connected to the first scan line GWL and may be configured to connect the data line DL to the second electrode CE2 of the first capacitor C1 in response to the first scan signal GW. The second transistor T2 may be configured to transmit the data voltage Dm to the second electrode CE2 of the first capacitor C1 in response to the first scan signal GW.

[0068] The third transistor T3 may have a gate connected to the third scan line GCL, and may be configured to connect the gate and the drain D of the first transistor T1 to each other in response to a third scan signal GC.

[0069] The fourth transistor T4 may have a gate connected to the fourth scan line GIL and may be configured to connect the first voltage line VL1 to the gate of the first transistor T1 in response to the fourth scan signal GI. The fourth transistor T4 may be configured to transmit the first initialization voltage VINT to the gate of the first transistor T1 in response to the fourth scan signal GI.

[0070] The fifth transistor T5 may have a gate connected to the third scan line GCL and may be configured to connect the third voltage line VL3 to the second electrode CE2 of the first capacitor C1 in response to the third scan signal GC. The fifth transistor T5 may be configured to transmit the first voltage VREF to the second electrode CE2 of the first capacitor C1 in response to the third scan signal GC.

[0071] The sixth transistor T6 may have a gate connected to the first emission control line EML1 and may be configured to connect the power line PL to the source S of the first transistor T1 in response to the first emission control signal EM1. The sixth transistor T6 may be configured to transmit the first driving voltage ELVDD to the source S of the first transistor T1 in response to the first emission control signal EM1.

[0072] The seventh transistor T7 may have a gate connected to the second emission control line EML2 and may be configured to connect the drain D of the first transistor T1 to the anode of the display element LED in response to the second emission control signal EM2.

[0073] The eighth transistor T8 may have a gate connected to the second scan line GBL and may be configured to connect the second voltage line VL2 to the anode of the display element LED in response to the second scan signal GB. The eighth transistor T8 may be configured to transmit the second initialization voltage VAINT to the anode of the display element LED in response to the second scan signal GB.

[0074] The ninth transistor T9 may have a gate connected to the second scan line GBL and may be configured to connect the fourth voltage line VL4 to the source S of the first transistor T1 in response to the second scan signal GB. The ninth transistor T9 may be configured to transmit the second voltage VOBS to the source S of the first transistor T1 in response to the second scan signal GB.

[0075] In an embodiment, the fourth scan signal GI may be substantially synchronized with the third scan signal GC of another row. For example, the fourth scan signal GI may be substantially synchronized with the third scan signal GC of a previous row.

[0076] Figure 2 It is illustrated that the sixth transistor T6 and the seventh transistor T7 are respectively controlled by the first emission control signal EM1 and the second emission control signal EM2 which are different from each other, however, the present disclosure is not limited thereto, and in another embodiment, the sixth transistor T6 and the seventh transistor T7 may be controlled together by the same emission control signal.

[0077] Figure 3 is a schematic block diagram of a wiring portion 210 and a gate driver 200 according to an embodiment.

[0078] refer to Figure 3 The wiring portion 210 may include first, second, third, and fourth conductive lines CL1, CL2, CL3, and CL4, and first, second, third, fourth, and fifth clock signal lines CSL1, CSL2, CSL3, CSL4, and CSL5. The stage ST of the gate driver 200 may include first, second, third, and fourth scan driving circuits SDC1, SDC2, SDC3, and SDC4, and first and second emission control driving circuits EDC1 and EDC2.

[0079] The first wire CL1, the second wire CL2, the third wire CL3, and the fourth wire CL4, and the first clock signal line CSL1, the second clock signal line CSL2, the third clock signal line CSL3, the fourth clock signal line CSL4, and the fifth clock signal line CSL5 may all extend in the first direction (e.g., ±y direction). The first wire CL1, the second wire CL2, the third wire CL3, and the fourth wire CL4, and the first clock signal line CSL1, the second clock signal line CSL2, the third clock signal line CSL3, the fourth clock signal line CSL4, and the fifth clock signal line CSL5 may be sequentially arranged in the second direction (e.g., ±x direction). The positions of the first wire CL1, the second wire CL2, the third wire CL3, and the fourth wire CL4, and the first clock signal line CSL1, the second clock signal line CSL2, the third clock signal line CSL3, the fourth clock signal line CSL4, and the fifth clock signal line CSL5 may be changed according to the embodiment.

[0080] although Figure 3 It is illustrated that the wiring portion 210 includes one first clock signal line CSL1 , one second clock signal line CSL2 , one third clock signal line CSL3 , one fourth clock signal line CSL4 , and one fifth clock signal line CSL5 , but the present disclosure is not limited thereto, and the number of clock signal lines may be variously implemented.

[0081] The first gate voltage VGHO may be applied to the first wire CL1, and the second gate voltage VGLO may be applied to the second wire CL2. The first gate voltage VGHO and the second gate voltage VGLO may control the switching transistor of the pixel PX. When the first gate voltage VGHO is applied to the gate of the switching transistor, the switching transistor may be turned on. When the second gate voltage VGLO is applied to the gate of the switching transistor, the switching transistor may be turned off. The first gate voltage VGHO may be a gate-on voltage, and the second gate voltage VGLO may be a gate-off voltage. The switching transistor of the pixel PX may be an n-type MOSFET, and the level of the second gate voltage VGLO may be lower than the level of the first gate voltage VGHO.

[0082] The third gate voltage VGH may be applied to the third wire CL3, and the fourth gate voltage VGL may be applied to the fourth wire CL4. The third gate voltage VGH and the fourth gate voltage VGL may control the switching transistor of the pixel PX. When the third gate voltage VGH is applied to the gate of the switching transistor, the switching transistor is turned off. When the fourth gate voltage VGL is applied to the gate of the switching transistor, the switching transistor may be turned on. The third gate voltage VGH may be a gate-off voltage, and the fourth gate voltage VGL may be a gate-on voltage. The switching transistor of the pixel PX may be a p-type MOSFET, and the level of the fourth gate voltage VGL may be lower than the level of the third gate voltage VGH.

[0083] In an embodiment, the level of the first gate voltage VGHO may be different from the level of the third gate voltage VGH. For example, the level of the first gate voltage VGHO may be higher than the level of the third gate voltage VGH. The level of the first gate voltage VGHO may be higher than the level of the third gate voltage VGH by the threshold voltage (Vth) of the n-type MOSFET.

[0084] In an embodiment, a level of the second gate voltage VGLO and a level of the fourth gate voltage VGL may be different from each other.

[0085] As referenced above Figure 2 As described, the pixel PX according to the embodiment may include an n-type MOSFET and a p-type MOSFET. In the case where the data voltage Dm and the first voltage VREF respectively applied to the second transistor T2 and the fifth transistor T5 are positive, it may be necessary to increase the gate turn-on voltage for turning on the n-type MOSFET by the threshold voltage (Vth) of the n-type MOSFET compared to the p-type MOSFET. In the case where the same gate voltage is used to control the n-type MOSFET and the p-type MOSFET, unnecessary power consumption may occur when controlling the p-type MOSFET. Therefore, as in the embodiment, in the case where the gate voltages for controlling the n-type MOSFET and the p-type MOSFET are separated from each other, the display device (see Figure 1 The power consumption of the display device 1).

[0086] The first conductive line CL1 may be electrically connected to a first connection line 211 extending in a second direction (e.g., ±x direction). The first connection line 211 may be connected to the first, third, and fourth scan driving circuits SDC1, SDC3, and SDC4, and is configured to transmit a first gate voltage VGHO from the first conductive line CL1 to the first, third, and fourth scan driving circuits SDC1, SDC3, and SDC4.

[0087] The second conductive line CL2 may be electrically connected to a second connection line 212 extending in a second direction (e.g., ±x direction). The second connection line 212 may be connected to the first, third, and fourth scan driving circuits SDC1, SDC3, and SDC4, and is configured to transmit the second gate voltage VGLO from the second conductive line CL2 to the first, third, and fourth scan driving circuits SDC1, SDC3, and SDC4.

[0088] The third conductive line CL3 may be electrically connected to a third connection line 213 extending in a second direction (e.g., ±x direction). The third connection line 213 may be connected to the second scan driving circuit SDC2, the first emission control driving circuit EDC1, and the second emission control driving circuit EDC2, and is configured to transmit the third gate voltage VGH from the third conductive line CL3 to the second scan driving circuit SDC2, the first emission control driving circuit EDC1, and the second emission control driving circuit EDC2.

[0089] The fourth conductive line CL4 may be electrically connected to a fourth connection line 214 extending in the second direction (e.g., ±x direction). The fourth connection line 214 may be connected to the second scan driving circuit SDC2, the first emission control driving circuit EDC1, and the second emission control driving circuit EDC2, and is configured to transmit the fourth gate voltage VGL from the fourth conductive line CL4 to the second scan driving circuit SDC2, the first emission control driving circuit EDC1, and the second emission control driving circuit EDC2.

[0090] The first clock signal GW_CLK may be applied to the first clock signal line CSL1, the second clock signal GB_CLK may be applied to the second clock signal line CSL2, and the third clock signal GC_CLK may be applied to the third clock signal line CSL3. The fourth clock signal GI_CLK may be applied to the fourth clock signal line CSL4, and the fifth clock signal EM_CLK may be applied to the fifth clock signal line CSL5.

[0091] The first clock signal line CSL1 may be electrically connected to a fifth connection line 215 extending in a second direction (eg, ±x direction). The fifth connection line 215 may be connected to the first scan driving circuit SDC1 and configured to transmit the first clock signal GW_CLK from the first clock signal line CSL1 to the first scan driving circuit SDC1.

[0092] The second clock signal line CSL2 may be electrically connected to a sixth connection line 216 extending in a second direction (eg, ±x direction). The sixth connection line 216 may be connected to the second scan driving circuit SDC2 and configured to transmit the second clock signal GB_CLK from the second clock signal line CSL2 to the second scan driving circuit SDC2.

[0093] The third clock signal line CSL3 may be electrically connected to a seventh connection line 217 extending in the second direction (eg, ±x direction). The seventh connection line 217 may be connected to the third scan driving circuit SDC3 and configured to transmit the third clock signal GC_CLK from the third clock signal line CSL3 to the third scan driving circuit SDC3.

[0094] The fourth clock signal line CSL4 may be electrically connected to an eighth connection line 218 extending in the second direction (eg, ±x direction). The eighth connection line 218 may be connected to the fourth scan driving circuit SDC4 and configured to transmit the fourth clock signal GI_CLK from the fourth clock signal line CSL4 to the fourth scan driving circuit SDC4.

[0095] The fifth clock signal line CSL5 may be electrically connected to a ninth connection line 219 extending in the second direction (e.g., ±x direction). The ninth connection line 219 may be connected to the first emission control driving circuit EDC1 and the second emission control driving circuit EDC2, respectively, and is configured to transmit the fifth clock signal EM_CLK from the fifth clock signal line CSL5 to the first emission control driving circuit EDC1 and the second emission control driving circuit EDC2.

[0096] The first scan driving circuit SDC1 may be configured to receive the first gate voltage VGHO, the second gate voltage VGLO, the first clock signal GW_CLK and the first start signal GW_FLM and output the first scan signal GW based on the first gate voltage VGHO, the second gate voltage VGLO, the first clock signal GW_CLK and the first start signal GW_FLM. Figure 2 The first scan line GWL may be configured to connect the first scan driving circuit SDC1 to the pixel PX, and the first scan driving circuit SDC1 may be configured to transmit the first scan signal GW to the pixel PX through the first scan line GWL.

[0097] The second scan driving circuit SDC2 may be configured to receive the third gate voltage VGH, the fourth gate voltage VGL, the second clock signal GB_CLK and the second start signal GB_FLM, and output the second scan signal GB based on the third gate voltage VGH, the fourth gate voltage VGL, the second clock signal GB_CLK and the second start signal GB_FLM. Figure 2 The second scan line GBL may be configured to connect the second scan driving circuit SDC2 to the pixel PX, and the second scan driving circuit SDC2 may be configured to transmit the second scan signal GB to the pixel PX through the second scan line GBL.

[0098] The third scan driving circuit SDC3 may be configured to receive the first gate voltage VGHO, the second gate voltage VGLO, the third clock signal GC_CLK and the third start signal GC_FLM and output a third scan signal GC based on the first gate voltage VGHO, the second gate voltage VGLO, the third clock signal GC_CLK and the third start signal GC_FLM. Figure 2 The third scan line GCL may be configured to connect the third scan driving circuit SDC3 to the pixel PX, and the third scan driving circuit SDC3 may be configured to transmit the third scan signal GC to the pixel PX through the third scan line GCL.

[0099] The fourth scan driving circuit SDC4 may be configured to receive the first gate voltage VGHO, the second gate voltage VGLO, the fourth clock signal GI_CLK and the fourth start signal GI_FLM and output a fourth scan signal GI based on the first gate voltage VGHO, the second gate voltage VGLO, the fourth clock signal GI_CLK and the fourth start signal GI_FLM. Figure 2 The fourth scan line GIL may be configured to connect the fourth scan driving circuit SDC4 to the pixel PX, and the fourth scan driving circuit SDC4 may be configured to transmit the fourth scan signal GI to the pixel PX through the fourth scan line GIL.

[0100] The first emission control driving circuit EDC1 may be configured to receive the third gate voltage VGH, the fourth gate voltage VGL, the fifth clock signal EM_CLK and the fifth start signal EM1_FLM and output the first emission control signal EM1 based on the third gate voltage VGH, the fourth gate voltage VGL, the fifth clock signal EM_CLK and the fifth start signal EM1_FLM. Figure 2 The first emission control line EML1 may be configured to connect the first emission control driving circuit EDC1 to the pixel PX, and the first emission control driving circuit EDC1 may be configured to transmit a first emission control signal EM1 to the pixel PX through the first emission control line EML1.

[0101] The second emission control driving circuit EDC2 may be configured to receive the third gate voltage VGH, the fourth gate voltage VGL, the fifth clock signal EM_CLK and the sixth start signal EM2_FLM, and output the second emission control signal EM2 based on the third gate voltage VGH, the fourth gate voltage VGL, the fifth clock signal EM_CLK and the sixth start signal EM2_FLM. Figure 2The second emission control line EML2 may be configured to connect the second emission control driving circuit EDC2 to the pixel PX, and the second emission control driving circuit EDC2 may be configured to transmit a second emission control signal EM2 to the pixel PX through the second emission control line EML2.

[0102] In an embodiment, the first start signal GW_FLM may be the first scan signal GW of the previous row. The second start signal GB_FLM may be the second scan signal GB of the previous row. The third start signal GC_FLM may be the third scan signal GC of the previous row. The fourth start signal GI_FLM may be the fourth scan signal GI of the previous row. The fifth start signal EM1_FLM may be the first emission control signal EM1 of the previous row. The sixth start signal EM2_FLM may be the second emission control signal EM2 of the previous row.

[0103] In another embodiment, the first start signal GW_FLM may be the first scan signal GW of the next row. The second start signal GB_FLM may be the second scan signal GB of the next row. The third start signal GC_FLM may be the third scan signal GC of the next row. The fourth start signal GI_FLM may be the fourth scan signal GI of the next row. The fifth start signal EM1_FLM may be the first emission control signal EM1 of the next row. The sixth start signal EM2_FLM may be the second emission control signal EM2 of the next row.

[0104] Figure 4 is a schematic block diagram of a wiring portion 210 and a gate driver 200 according to another embodiment. Figure 4 yes Figure 3 's modifications, and with Figure 3 The difference lies in the structure of the wiring portion 210. Figure 3 The description given and the differences are described.

[0105] refer to Figure 4 , the wiring portion 210 may include a fifth clock signal line CSL5' and a sixth clock signal line CSL6'. The fifth clock signal line CSL5' and the sixth clock signal line CSL6' may both extend in the first direction (eg, ±y direction). Figure 4 It is illustrated that the wiring portion 210 includes one fifth clock signal line CSL5 ′ and one sixth clock signal line CSL6 ′, but the present disclosure is not limited thereto, and the number of clock signal lines may be variously implemented.

[0106] The fifth clock signal EM1_CLK may be applied to the fifth clock signal line CSL5', and the sixth clock signal EM2_CLK may be applied to the sixth clock signal line CSL6'. The fifth clock signal line CSL5' may be electrically connected to the tenth connection line 220 extending in the second direction (e.g., the ±x direction). The tenth connection line 220 may be connected to the first emission control driving circuit EDC1, and is configured to transmit the fifth clock signal EM1_CLK from the fifth clock signal line CSL5' to the first emission control driving circuit EDC1. The sixth clock signal line CSL6' may be electrically connected to the eleventh connection line 221 extending in the second direction (e.g., the ±x direction). The eleventh connection line 221 may be connected to the second emission control driving circuit EDC2, and is configured to transmit the sixth clock signal EM2_CLK from the sixth clock signal line CSL6' to the second emission control driving circuit EDC2.

[0107] The first emission control driving circuit EDC1 may be configured to receive the third gate voltage VGH, the fourth gate voltage VGL, the fifth clock signal EM1_CLK and the seventh start signal EM_FLM and output the first emission control signal EM1 based on the third gate voltage VGH, the fourth gate voltage VGL, the fifth clock signal EM1_CLK and the seventh start signal EM_FLM. Figure 2 The first emission control line EML1 may be configured to connect the first emission control driving circuit EDC1 to the pixel PX, and the first emission control driving circuit EDC1 may be configured to transmit a first emission control signal EM1 to the pixel PX through the first emission control line EML1.

[0108] The second emission control driving circuit EDC2 may be configured to receive the third gate voltage VGH, the fourth gate voltage VGL, the sixth clock signal EM2_CLK and the seventh start signal EM_FLM, and output a second emission control signal EM2 based on the third gate voltage VGH, the fourth gate voltage VGL, the sixth clock signal EM2_CLK and the seventh start signal EM_FLM. Figure 2 The second emission control line EML2 may be configured to connect the second emission control driving circuit EDC2 to the pixel PX, and the second emission control driving circuit EDC2 may be configured to transmit a second emission control signal EM2 to the pixel PX through the second emission control line EML2.

[0109] Figure 5 is a schematic diagram of an equivalent circuit of a pixel PX according to another embodiment. Figure 5 yes Figure 2 's modifications, and with Figure 2 The difference lies in the structure of some transistors. Figure 2The description given and the differences are described.

[0110] refer to Figure 5 , the first transistor T1 may include a first upper gate Ga1 and a first lower gate Gb1. The first upper gate Ga1 and the above Figure 2 The first lower gate Gb1 may be connected to the power line PL, and the first driving voltage ELVDD may be applied to the first lower gate Gb1.

[0111] The gate of each of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include an upper gate and a lower gate connected to each other. Figure 5 , the second transistor T2 may include a second upper gate Ga2 and a second lower gate Gb2 connected to each other. The third transistor T3 may include a third upper gate Ga3 and a third lower gate Gb3 connected to each other. The fourth transistor T4 may include a fourth upper gate Ga4 and a fourth lower gate Gb4 connected to each other. The fifth transistor T5 may include a fifth upper gate Ga5 and a fifth lower gate Gb5 connected to each other. Therefore, in the case where the upper gate and the lower gate of each of the plurality of switching transistors are connected to each other, the electron mobility in the transistor may be improved.

[0112] The display device has been described above, but the present disclosure is not limited thereto. For example, a method for manufacturing a display device also falls within the scope of the present disclosure.

[0113] According to the embodiment, a display device with reduced power consumption can be realized. The scope of the present disclosure is not limited by such effects.

[0114] The above description is an example of the technical features of the present disclosure, and a person skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the above-mentioned embodiments of the present disclosure may be implemented individually or in combination with each other.

[0115] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, characterized in that: include: a substrate, the substrate comprising a display area and a peripheral area adjacent to the display area; A pixel, wherein the pixel is in the display area; a first conductive line extending in a first direction on one side of the peripheral region and to which a first gate voltage is applied; a second conductive line extending in the first direction on the one side of the peripheral region and to which a second gate voltage having a level lower than that of the first gate voltage is applied; a first clock signal line extending in the first direction on the one side of the peripheral area and to which a first clock signal is applied; a third conductive line extending in the first direction on the one side of the peripheral region and to which a third gate voltage having a level different from the level of the first gate voltage is applied; a fourth conductive line extending in the first direction on the one side of the peripheral region and to which a fourth gate voltage having a level lower than the level of the third gate voltage is applied; a second clock signal line extending in the first direction on the one side of the peripheral area and to which a second clock signal is applied; a first scan driving circuit, which is arranged on the one side of the peripheral area, is electrically connected to the first conductive line, the second conductive line, and the first clock signal line, and transmits a first scan signal to the pixel based on the first gate voltage, the second gate voltage, and the first clock signal; as well as A second scanning driving circuit is arranged on the one side of the peripheral area, is electrically connected to the third conductive line, the fourth conductive line and the second clock signal line, and transmits a second scanning signal to the pixel based on the third gate voltage, the fourth gate voltage and the second clock signal.

2. The display device according to claim 1, characterized in that The pixels include: A display element, the display element comprising an anode and a cathode; a first transistor that controls an amount of drive current flowing to the display element according to a gate-source voltage of the first transistor; a first capacitor, the first capacitor comprising a first electrode and a second electrode, the first electrode being connected to a gate of the first transistor; a second transistor transmitting a data voltage to the second electrode of the first capacitor in response to the first scan signal; and A third transistor transmits a first initialization voltage to the anode of the display element in response to the second scan signal.

3. The display device according to claim 2, characterized in that The level of the first gate voltage is higher than the level of the third gate voltage.

4. The display device according to claim 2, characterized in that The first transistor and the third transistor are both p-type metal oxide semiconductor field effect transistors, and The second transistor is an n-type metal oxide semiconductor field effect transistor.

5. The display device according to claim 2, characterized in that The pixel also includes: A fourth transistor applies a first voltage to a source of the first transistor in response to the second scan signal.

6. The display device according to claim 1, characterized in that The level of the fourth gate voltage is different from the level of the second gate voltage.

7. The display device according to claim 1, characterized in that Also includes: a third clock signal line extending in the first direction on the one side of the peripheral area and to which a third clock signal is applied; a fourth clock signal line extending in the first direction on the one side of the peripheral area and to which a fourth clock signal is applied; a fifth clock signal line extending in the first direction on the one side of the peripheral area and to which a fifth clock signal is applied; a sixth clock signal line extending in the first direction on the one side of the peripheral area and to which a sixth clock signal is applied; a third scan driving circuit, which is arranged on the one side of the peripheral area, is electrically connected to the first conductive line, the second conductive line and the third clock signal line, and transmits a third scan signal to the pixel based on the first gate voltage, the second gate voltage and the third clock signal; a fourth scan driving circuit, which is arranged on the one side of the peripheral area, is electrically connected to the first conductive line, the second conductive line and the fourth clock signal line, and transmits a fourth scan signal to the pixel based on the first gate voltage, the second gate voltage and the fourth clock signal; a first emission control driving circuit, which is arranged on the one side of the peripheral area, is electrically connected to the third conductive line, the fourth conductive line, and the fifth clock signal line, and transmits a first emission control signal to the pixel based on the third gate voltage, the fourth gate voltage, and the fifth clock signal; as well as a second emission control driving circuit, which is arranged on the one side of the peripheral area, is electrically connected to the third conductive line, the fourth conductive line and the sixth clock signal line, and transmits a second emission control signal to the pixel based on the third gate voltage, the fourth gate voltage and the sixth clock signal.

8. The display device according to claim 7, characterized in that The pixels include: A display element, the display element comprising an anode and a cathode; a first transistor that controls an amount of drive current flowing to the display element according to a gate-source voltage of the first transistor; a first capacitor, the first capacitor comprising a first electrode and a second electrode, the first electrode being connected to a gate of the first transistor; a second transistor transmitting a data voltage to the second electrode of the first capacitor in response to the first scan signal; a third transistor transmitting a first initialization voltage to the anode of the display element in response to the second scan signal; a fourth transistor that applies a first voltage to a source of the first transistor in response to the second scan signal; a fifth transistor that applies a second voltage to the second electrode of the first capacitor in response to the third scan signal; a sixth transistor that connects the source of the first transistor to the drain of the first transistor in response to the third scan signal; a seventh transistor transmitting a second initialization voltage to the gate of the first transistor in response to the fourth scan signal; an eighth transistor that applies a driving voltage to the source of the first transistor in response to the first emission control signal; and a ninth transistor that connects the drain of the first transistor to the anode of the display element in response to the second emission control signal.

9. The display device according to claim 8, characterized in that The first transistor includes a first upper gate connected to the first electrode of the first capacitor and a first lower gate to which the driving voltage is applied, The second transistor includes a second upper gate and a second lower gate connected to each other and applied with the first scan signal, The fifth transistor includes a third upper gate and a third lower gate connected to each other and applied with the third scan signal, The sixth transistor includes a fourth upper gate and a fourth lower gate connected to each other and applied with the third scan signal, and The seventh transistor includes a fifth upper gate and a fifth lower gate which are connected to each other and to which the fourth scan signal is applied.

10. A display device, characterized in that: include: A pixel connected to: Respectively transmitting a first scanning signal, a second scanning signal, a third scanning signal and a fourth scanning signal to a first scanning line, a second scanning line, a third scanning line and a fourth scanning line of the pixel; transmitting a first emission control signal and a second emission control signal to a first emission control line and a second emission control line of the pixel, respectively; transmitting a data voltage to a data line of the pixel; a power line for transmitting a drive voltage to the pixel; transmitting a first initialization voltage and a second initialization voltage to a first voltage line and a second voltage line of the pixel respectively; as well as transmitting the first voltage and the second voltage to a third voltage line and a fourth voltage line of the pixel respectively, Wherein, the pixels include: A display element, the display element comprising an anode and a cathode; a first capacitor comprising a first electrode and a second electrode; a second capacitor including a third electrode connected to the second electrode of the first capacitor and a fourth electrode connected to the power line; a first transistor including a gate connected to the first electrode of the first capacitor, a source connected to the power line, and a drain; a second transistor including a gate connected to the first scan line and connecting the data line to the second electrode of the first capacitor in response to the first scan signal; a third transistor including a gate connected to the third scan line and connecting the gate of the first transistor to the drain of the first transistor in response to the third scan signal; a fourth transistor including a gate connected to the fourth scan line and connecting the first voltage line to the gate of the first transistor in response to the fourth scan signal; a fifth transistor including a gate connected to the third scan line and connecting the third voltage line to the second electrode of the first capacitor in response to the third scan signal; a sixth transistor including a gate connected to the first emission control line and connecting the power line to the source of the first transistor in response to the first emission control signal; a seventh transistor including a gate connected to the second emission control line and connecting the drain of the first transistor to the anode of the display element in response to the second emission control signal; an eighth transistor including a gate connected to the second scan line and connecting the second voltage line to the anode of the display element in response to the second scan signal; and a ninth transistor including a gate connected to the second scan line and connecting the fourth voltage line to the source of the first transistor in response to the second scan signal.

Images