Display panel and display device

Abstract

The utility model provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, a gate drive circuit and a plurality of clock signal lines, wherein the gate drive circuit and the clock signal lines are arranged on the substrate; the clock signal line is electrically connected with the gate driving circuit in a cross-layer manner through the connecting part; for any two adjacent clock signal lines, one is marked as a first clock signal line, and the other one is marked as a second clock signal line; the connecting part corresponding to the first clock signal line is marked as a first connecting part; the connecting part corresponding to the second clock signal line is marked as a second connecting part; the first clock signal line comprises a main body extension part and a surrounding part connected with the main body extension part; the orthographic projection of the surrounding part on the substrate half surrounds the orthographic projection of the first connecting part on the substrate; or, the orthographic projection of the surrounding part on the substrate half surrounds the orthographic projection of the second connecting part on the substrate; the surrounding part comprises a sub-lead part and a resistance adjusting part connected to the side, close to the second clock signal line, of the sub-lead part.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] As display products become larger and narrower in borders, the signal lines that power electronic components in the products are becoming longer and longer, while the line widths are decreasing, which results in a significant increase in signal line resistance and makes charging more difficult. At the same time, the demand for high refresh rates in display products shortens the charging time of each row of pixels in the product, further increasing the difficulty of charging. Utility Model Content

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a display panel and a display device.

[0004] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a display panel, comprising a base substrate, a gate driving circuit arranged on the base substrate, and a plurality of clock signal lines; the clock signal lines are electrically connected to the gate driving circuit across layers through a connecting portion;

[0005] For any two adjacent clock signal lines, one of them is recorded as a first clock signal line, and the other is recorded as a second clock signal line; the connection portion corresponding to the first clock signal line is recorded as a first connection portion; the connection portion corresponding to the second clock signal line is recorded as a second connection portion;

[0006] The first clock signal line includes a main body extension portion and a surrounding portion connected to the main body extension portion; the orthographic projection of the surrounding portion on the base substrate half surrounds the orthographic projection of the first connecting portion on the base substrate; or the orthographic projection of the surrounding portion on the base substrate half surrounds the orthographic projection of the second connecting portion on the base substrate;

[0007] The surrounding portion includes a sub-lead portion and a resistance adjustment portion connected to a side of the sub-lead portion close to the second clock signal line.

[0008] In some embodiments, the opening of the sub-lead portion faces the second clock signal line; the sub-lead portion includes a first sub-segment, a second sub-segment and a third sub-segment connected in series in sequence, and the first sub-segment, the second sub-segment and the third sub-segment extend in different directions;

[0009] At least one of the first sub-segment and the third sub-segment is connected to the resistance adjusting part; when the orthographic projection of the sub-lead part on the base substrate half surrounds the orthographic projection of the first connecting part on the base substrate, the first connecting part is connected to the second sub-segment; when the orthographic projection of the sub-lead part on the base substrate half surrounds the orthographic projection of the second connecting part on the base substrate, the second sub-segment is arranged opposite to the second connecting part.

[0010] In some embodiments, for the first subsegment and the resistance adjusting portion connected thereto, the resistance adjusting portion at least partially covers a surface of the first subsegment close to the opening;

[0011] With respect to the third subsegment and the resistance adjusting portion connected thereto, the resistance adjusting portion at least partially covers a surface of the third subsegment close to the opening.

[0012] In some embodiments, the display panel includes a display area and an edge area surrounding the display area, the plurality of clock signal lines and the gate driving circuit are both located in the edge area, and the plurality of clock signal lines are arranged on a side of the gate driving circuit away from the display area;

[0013] The first clock signal line is farther away from the display area than the second clock signal line; or the first clock signal line is closer to the display area than the second clock signal line.

[0014] In some embodiments, the plurality of clock signal lines include N; the gate drive circuit includes M cascaded shift registers; wherein N is an even number greater than or equal to 6; M is an integer greater than or equal to N; one of the clock signal lines is electrically connected to one of the shift registers;

[0015] The lines connecting the centers of the connecting parts corresponding to each of the clock signal lines are not on the same straight line.

[0016] In some embodiments, the number of clock signal lines sandwiched between any two adjacent clock signal lines connected to the shift registers does not exceed 3.

[0017] In some embodiments, the N clock signal lines are arranged side by side along a first direction, and are divided into Q clock signal line groups along the first direction, each clock signal line group includes q clock signal lines; wherein Q is an integer between 2 and N / 2; q is an integer between 2 and N / 2;

[0018] For any group of the clock signal lines, the centers of the connection parts corresponding to each of the clock signal lines are connected into a straight line;

[0019] For different groups of the clock signal line groups, the extending directions of the straight lines connected by the centers of the connecting parts are different.

[0020] In some embodiments, the M shift registers are arranged side by side along the second direction, and are divided into P shift register groups along the second direction, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1;

[0021] For any group of the shift registers, the first shift register is electrically connected to the (N / 2+1)th clock signal line, or the first shift register is electrically connected to the (N / 2-1)th clock signal line;

[0022] For any group of the shift register groups, the number of clock signal lines between the i-th shift register electrically connected to the clock signal line and the i+1-th shift register electrically connected to the clock signal line is x; the number of clock signal lines between the i+1-th shift register electrically connected to the clock signal line and the i+2-th shift register electrically connected to the clock signal line is y; the number of clock signal lines between the i+2-th shift register electrically connected to the clock signal line and the i+3-th shift register electrically connected to the clock signal line is z; the number of clock signal lines between the i+3-th shift register electrically connected to the clock signal line and the i+4-th shift register electrically connected to the clock signal line is w; i is 1 to (N-5); wherein x=z, y=w.

[0023] In some embodiments, the number of clock signal lines sandwiched between any two adjacent clock signal lines connected to the shift registers does not exceed 2.

[0024] In some embodiments, the M shift registers are arranged side by side along the second direction, and are divided into P shift register groups along the second direction, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1;

[0025] For any group of the shift register groups, the number of clock signal lines between the jth shift register electrically connected to the clock signal line and the j+1th shift register electrically connected to the clock signal line is m; the number of clock signal lines between the j+1th shift register electrically connected to the clock signal line and the j+2th shift register electrically connected to the clock signal line is n; j is 1 to (N-2); wherein, |mn|≤1, wherein || represents an absolute value.

[0026] In some embodiments, the M shift registers are arranged side by side along the second direction, and are divided into P shift register groups along the second direction, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1;

[0027] For any group of shift register groups, the sth shift register is electrically connected to the clock signal line, and the number of clock signal lines sandwiched between the clock signal lines electrically connected to the (s+1)th shift register is equal to the number of clock signal lines sandwiched between the clock signal line electrically connected to the (Ns)th shift register and the clock signal line electrically connected to the (N-s+1)th shift register; s is 1 to (N / 2-1).

[0028] In some embodiments, the kth shift register is cascaded with the k+Nth shift register; k is 1-N.

[0029] In some embodiments, at least part of the clock signal line has a straight line portion and a serpentine line connected in series; the serpentine line includes a first bending portion and a second bending portion connecting two adjacent first bending portions; the extension direction of the first bending portion is the line width direction of the clock signal line, and the extension direction of the second bending portion is the overall extension direction of the clock signal line;

[0030] The number of first bending portions on the second clock signal line is greater than the number of first bending portions on the first clock signal line.

[0031] In some embodiments, the extension length of the first bending portion does not exceed the line width of the straight portion.

[0032] In some embodiments, the line width of the main extension portion of the first clock signal line is the same as the line width of the sub-lead portion;

[0033] The line width of the main extension portion of the first clock signal line is greater than or equal to the maximum line width of the second clock signal line; and / or the line width of the sub-lead portion of the first clock signal line is greater than or equal to the maximum line width of the second clock signal line.

[0034] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising a display panel as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1a A schematic diagram of the arrangement of the existing clock signal line winding and routing;

[0036] Figure 1b A schematic diagram of the electrical connection relationship between the existing clock signal line and the shift register;

[0037] Figure 2 A schematic diagram of a display panel provided in an embodiment of the present disclosure;

[0038] Figure 3a A schematic diagram of the structure of a clock signal line winding according to an example provided in an embodiment of the present disclosure;

[0039] Figure 3b for Figure 3a A local enlarged view of the A-A' region;

[0040] Figure 3c for Figure 3a A local magnified view of the C-C' region;

[0041] Figure 4a A schematic diagram of the structure of a clock signal line winding according to another example provided in an embodiment of the present disclosure;

[0042] Figure 4b for Figure 4a A local enlarged view of the B-B' region in the middle;

[0043] Figure 5 A schematic diagram of the wiring of a clock signal line in Example 1 provided in an embodiment of the present disclosure;

[0044] Figure 6 A schematic diagram of the wiring of a clock signal line in Example 2 provided in an embodiment of the present disclosure;

[0045] Figure 7 A schematic diagram of the wiring of a clock signal line in Example 3 provided in an embodiment of the present disclosure;

[0046] Figure 8 A schematic diagram of the wiring of a clock signal line in Example 4 provided in an embodiment of the present disclosure;

[0047] Fig. 9 A schematic diagram of the wiring of a clock signal line in Example 5 provided in an embodiment of the present disclosure;

[0048] Fig.10 A schematic diagram of wiring of a clock signal line in Example 6 provided in an embodiment of the present disclosure;

[0049] Fig.11 A schematic diagram of the structure of a clock signal line provided in an embodiment of the present disclosure;

[0050] Fig.12 A schematic diagram of the structure of another clock signal line provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0052] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0053] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0054] Based on the design concept of low cost and high integration, a gate driver array (GOA) is set inside the product. GOA technology is a technology commonly used in current display products. It makes the row scanning drive signal circuit on the substrate to realize the driving mode of scanning the gate row row by row. Compared with traditional technology, GOA technology makes the row scanning drive signal circuit on the display panel, thus eliminating the gate row driver chip, thereby saving huge costs. At the same time, without the row driver chips on both sides, the border of the display panel can also be narrower, which is more in line with people's aesthetic needs.

[0055] In related technologies, for narrow-frame, large-screen display products, the routing length of the clock signal line that powers the GOA continues to increase, while the line width continues to decrease, resulting in a significant increase in the resistance of the clock signal line, making charging more difficult. At the same time, the demand for high refresh rates for display products will shorten the charging time of each row of pixels in the product, further increasing the difficulty of charging. In general, the number of clock signal lines that control the GOA is increased to ensure the charging time for each row of pixels.

[0056] Current display products are limited by structure and process. Clock signal lines and GOA often need to jump through layers to achieve electrical connection. Therefore, clock signal lines need to bypass vias by winding. As the number of clock signal lines increases, the number of vias that peripheral clock signal lines need to bypass increases. The resistance difference between the outermost clock signal line (e.g., CLK8) and the innermost clock signal line (e.g., CLK1) will increase due to the increase in the number and distance of the vias. Figure 1a As shown, there are 8 clock signal lines, which are marked as the 1st to 8th clock signal lines from left to right. Due to the avoidance design of the bypass hole, the resistance of the 1st to 8th clock signal lines increases successively. Figure 1b As shown, it is a schematic diagram of the electrical connection relationship between the existing clock signal line and the shift register. With 8 shift registers as a group, the 1st to 8th shift registers (GOA_1 to GOA_8) are electrically connected to the 1st to 8th clock signal lines in sequence. Similarly, the 9th to 16th shift registers (GOA_9 to GOA_16) are electrically connected to the 1st to 8th clock signal lines in sequence, and so on. Among them, the 8th shift register and the 9th shift register respectively control the output of the gate scanning signal of the adjacent row pixels. Since the resistance difference between the 8th clock signal line and the 1st clock signal line electrically connected to the two is large, the falling time t of the clock signal output by the 8th clock signal line and the 1st clock signal line is caused. f Therefore, when the gate scanning signal is turned off, the larger t f The difference leads to inconsistent coupling and pulling of pixels in adjacent rows, resulting in differences in brightness and darkness in the display effect, which appears as periodic fine horizontal stripes on a macro scale.

[0057] In view of this, the embodiment of the present disclosure provides a display panel, which substantially balances the resistance of each clock signal line to disperse, reduce or eliminate the resistance difference between two clock signal lines corresponding to adjacent rows of pixels as much as possible, thereby reducing or eliminating the t of the clock signal on the clock signal line. f Differences, avoid t f Horizontal stripe problems caused by excessive differences.

[0058] Specifically, since the parasitic capacitance between the clock signal line and the output transistor in the shift register is the main factor affecting the capacitive load of the clock signal line, and the direct capacitance formed by the clock signal line across the line has the same effect on the two clock signal lines, the difference in capacitive load between different clock signal lines is only the lateral capacitance difference, which is relatively small. Therefore, the resistance difference is the main reason for the difference in load between adjacent clock signal lines.

[0059] Figure 2 A schematic diagram of a display panel provided in an embodiment of the present disclosure, Figure 3a A schematic diagram of a structure of a clock signal line winding according to an example provided in an embodiment of the present disclosure is provided. Figure 3b for Figure 3a A partial enlarged view of the A-A' region. Figure 4a A schematic diagram of the structure of the clock signal line winding according to another example provided in the embodiment of the present disclosure is shown. Figure 4b for Figure 4a A local enlarged view of the B-B' area in the middle.

[0060] like Figure 2 , Figure 3a , Figure 3b , Figure 4a and Figure 4b As shown, the display panel includes a base substrate (not shown in the figure), a gate drive circuit 1 arranged on the base substrate, and multiple clock signal lines (i.e., multiple CLKs, respectively denoted as CLK1~CLK8); the clock signal lines are electrically connected to the gate drive circuit 1 across the layer through the connecting part 2.

[0061] The clock signal line is configured to provide a clock signal to the gate driving circuit 1. The gate driving circuit 1 is configured to scan pixel rows one by one and provide a gate scanning signal to each row of pixels.

[0062] like Figure 2 As shown, the overall extension direction of the clock signal line is the second direction Y, and multiple clock signal lines are arranged side by side along the first direction X, and the first direction X intersects the second direction Y. Exemplarily, without considering the influence of errors, the first direction X is perpendicular to the second direction Y.

[0063] like Figure 2 As shown, the gate driving circuit 1 includes a plurality of cascaded shift registers (GOA_1 to GOA_N). In the present disclosure, one clock signal line is electrically connected to one shift register, and one shift register outputs a gate scanning signal for one row of pixels.

[0064] Specifically, the clock signal line is electrically connected to the second electrode of the output transistor (not shown in the figure) in the shift register. For example, the clock signal line is located at the gate electrode layer of the output transistor, and the second electrode of the output transistor is located at the source-drain electrode layer. Therefore, the clock signal line and the second electrode of the output transistor are connected across layers using a via, and there is at least one insulating layer between the gate electrode layer and the source-drain electrode layer. The clock signal line CLK can be electrically connected to the second electrode of the output transistor through the connecting portion 2 that passes through the via.

[0065] like Figure 3a , Figure 3b , Figure 4a and Figure 4b As shown, for any two adjacent clock signal lines, one of them is recorded as the first clock signal line 31 and the other is recorded as the second clock signal line 32; the connection part 2 corresponding to the first clock signal line 31 is recorded as the first connection part 21; the connection part 2 corresponding to the second clock signal line 32 is recorded as the second connection part 22.

[0066] It should be noted here that the first clock signal line 31 and the second clock signal are any two adjacent clock signal lines, so the first clock signal line 31 in this group of adjacent clock signal lines can also be the second clock signal line 32 in the next group of adjacent clock signal lines. Therefore, the first clock signal line 31 and the second clock signal line 32 in the present disclosure are relative concepts, not absolute concepts. Similarly, the first connection part 21 and the second connection part 22 are also relative concepts, not absolute concepts. Without specifically referring to the first connection part 21 or the second connection part 22, the following expression of "connection part 2" in the present disclosure includes the first connection part 21 and the second connection part 22.

[0067] At least part of the clock signal line is avoided in the projection area of ​​the connection part 2 by winding. Figure 3b and Figure 4b As shown, the first clock signal line 31 includes a main extension portion 311 and a surrounding portion 312 connected to the main extension portion 311. Exemplarily, the extension direction of the main extension portion 311 is the overall extension direction of the first clock signal line 31, that is, the second direction Y. The opening of the surrounding portion 312 faces the second clock signal line 32.

[0068] like Figure 3b As shown, in one case, the orthographic projection of the surrounding portion 312 on the substrate and the orthographic projection of the semi-surrounding first connecting portion 21 on the substrate. Figure 4b As shown, in another case, the orthographic projection of the surrounding portion 312 on the substrate substrate semi-surrounds the orthographic projection of the second connecting portion 22 on the substrate substrate.

[0069] like Figure 3b and Figure 4bAs shown, the surrounding portion 312 includes a sub-lead portion 312a and a resistance adjustment portion 312b connected to the surface of the sub-lead portion 312a near the second clock signal line 32. The material of the resistance adjustment portion 312b is a conductive material. The resistance adjustment portion 312b is in contact with the sub-lead portion 312a, which is equivalent to increasing the wire width of the sub-lead portion 312a at the contact position, thereby reducing the resistance of the surrounding portion 312, thereby reducing the resistance difference between the first clock signal line 31 and the second clock signal line 32, thereby reducing the resistance difference between any two clock signal lines, and reducing the t between any two clock signal lines. f Difference, improve fine horizontal stripes.

[0070] For example, Figure 3c As shown, it is Figure 3a In the partial enlarged view of the CC' region, the connection portion 2 includes at least a first sub-portion 2a located at the gate electrode layer and electrically connected to the clock signal line, and a second sub-portion 2b located at the source-drain electrode layer and electrically connected to the transfer lead 41. The transfer lead 41 extends along the first direction X to the GOA region and is electrically connected to the second electrode of the output transistor in the shift register.

[0071] Exemplarily, when multiple insulating layers are disposed between the gate electrode layer and the source-drain electrode layer, the connecting portion 2 further includes a third sub-portion 1c disposed between the multiple insulating layers. At this time, the second sub-portion 2b is connected to the transfer lead 41 as an integral structure.

[0072] Exemplarily, the orthographic projection of the connecting portion 2 on the substrate has no overlap with the orthographic projection of the resistance adjusting portion 312 b on the substrate.

[0073] Optionally, the material of the resistance adjusting portion 312b is the same as that of the sub-lead portion 312a. Optionally, the resistance adjusting portion 312b is connected with the sub-lead portion 312a as an integral structure, which can be formed by a single process during the preparation stage.

[0074] In some embodiments, Figure 3b and Figure 4b As shown, the opening of the sub-lead portion 312a faces the second clock signal line 32, that is, the opening faces the first direction X. The sub-lead portion 312a includes a first sub-segment 3121, a second sub-segment 3122 and a third sub-segment 3123 connected in series in sequence, and the first sub-segment 3121, the second sub-segment 3122 and the third sub-segment 3123 extend in different directions.

[0075] For example, Figure 3bAs shown, the extension direction of the second sub-segment 3122 is the same as the extension direction of the main extension portion 311; the extension direction of the main extension portion 311 is the same as the overall extension direction of the first clock signal line 31 or the second clock signal line 32, that is, the second direction Y. The angle α1 formed by the first sub-segment 3121 and the second sub-segment 3122 is an obtuse angle; and the angle α2 formed by the second sub-segment 3122 and the third sub-segment 3123 is an obtuse angle. Exemplarily, α1=α2.

[0076] like Figure 3b and Figure 4b As shown, at least one of the first sub-segment 3121 and the third sub-segment 3123 is connected to the resistance adjusting portion 312b. Exemplarily, the resistance adjusting portion 312b includes two, and the first sub-segment 3121 and the third sub-segment 3123 are connected to different resistance adjusting portions 312b.

[0077] Since the first sub-segment 3121 and the third sub-segment 3123 are arranged obliquely relative to the second sub-segment 3122, there is a certain distance between the first sub-segment 3121 and the third sub-segment 3123 and the connecting portion 2. That is, the present disclosure utilizes a part of the space between the first sub-segment 3121 and the third sub-segment 3123 and the connecting portion 2 to arrange the resistance adjustment portion 312b, so as to improve the resistance difference between the clock signal lines, without changing the process conditions and the layout space of the clock signal lines.

[0078] like Figure 3b As shown, when the orthographic projection of the sub-lead portion 312 a on the substrate half surrounds the orthographic projection of the first connecting portion 21 on the substrate, the first connecting portion 21 is connected to the second sub-segment 3122 .

[0079] like Figure 4b As shown, when the orthographic projection of the sub-lead portion 312a on the substrate half surrounds the orthographic projection of the second connecting portion 22 on the substrate, the second sub-segment 3122 is arranged opposite to the second connecting portion 22.

[0080] The line width of the resistance adjustment portion 312 b may be set according to factors such as the resistance difference between the first clock signal line 31 and the second clock signal line 32 , actual wiring space, and signal crosstalk, and is not specifically limited in the embodiment of the present disclosure.

[0081] Optionally, the first sub-segment 3121 and the third sub-segment 3123 have the same length in the extension direction, and the larger the angle between the extension line of the first sub-segment 3121 and the extension line of the third sub-segment 3123, the more conducive it is to achieve a narrow frame. In actual product design, it is mainly determined by the size of the via hole and the gap between adjacent clock signal lines of the connecting part. In order to prevent tip discharge (ESD), the angle between the extension line of the first sub-segment 3121 and the extension line of the third sub-segment 3123 is ≥90°.

[0082] In some embodiments, Figure 3b and Figure 4b As shown, for the first sub-segment 3121 and the resistance adjusting portion 312b connected thereto, the resistance adjusting portion 312b covers the surface of the first sub-segment 3121 close to the opening; for the third sub-segment 3123 and the resistance adjusting portion 312b connected thereto, the resistance adjusting portion 312b at least partially covers the surface of the third sub-segment 3123 close to the opening, and by reasonably increasing the wire width of the sub-lead portion 312a at the contact position, the resistance difference between the first clock signal line 31 and the second clock signal line 32 is reduced as much as possible, so that the difference is 0, thereby improving the defect of fine horizontal lines.

[0083] In some embodiments, Figure 2 As shown, the display panel includes a display area AA and an edge area BB surrounding the display area AA, multiple clock signal lines and a gate driving circuit 1 are located in the edge area BB, and multiple clock signal lines (CLK) are arranged on a side of the gate driving circuit 1 away from the display area AA.

[0084] The first clock signal line 31 is farther away from the display area AA than the second clock signal line 32 ; or the first clock signal line 31 is closer to the display area AA than the second clock signal line 32 .

[0085] like Figure 3a and Figure 3b As shown, a plurality of clock signal lines are arranged side by side along the first direction X, and point from the edge area BB to the display area AA, and the resistance of the clock signal lines decreases successively. At this time, the first clock signal line 31 with a larger resistance is farther away from the display area AA than the second clock signal line 32 with a smaller resistance. Here, the orthographic projection of the sub-lead portion 312a on the substrate substrate half surrounds the orthographic projection of the first connecting portion 21 on the substrate substrate. Of course, under this arrangement of the clock signal lines, in other examples, the orthographic projection of the sub-lead portion 312a on the substrate substrate may also half surround the orthographic projection of the second connecting portion 22 on the substrate substrate.

[0086] For example, Figure 3a As shown, the clock signal line closest to the display area AA does not have a surrounding portion 312 and has the smallest resistance.

[0087] like Figure 4a and Figure 4bAs shown, a plurality of clock signal lines are arranged side by side along the first direction X, and point from the edge area BB to the display area AA, and the resistance of the clock signal lines increases successively. At this time, the first clock signal line 31 with a larger resistance is closer to the display area AA than the second clock signal line 32 with a smaller resistance. Here, the orthographic projection of the sub-lead portion 312a on the substrate substrate half surrounds the orthographic projection of the second connection portion 22 on the substrate substrate. Of course, under this arrangement of the clock signal lines, in other examples, the orthographic projection of the sub-lead portion 312a on the substrate substrate may also half surround the orthographic projection of the first connection portion 21 on the substrate substrate.

[0088] For example, Figure 4a As shown, the clock signal line farthest from the display area AA has no surrounding portion 312 and has the smallest resistance.

[0089] It should be noted that, when the remaining space near the opening of the first sub-segment 3121 and the third sub-segment 3123 is large enough, the resistance difference between the first clock signal line 31 with the resistance adjustment portion 312b and the second clock signal line 32 without the resistance adjustment portion 312b may be 0. However, when the remaining space near the opening of the first sub-segment 3121 and the third sub-segment 3123 is insufficient, the added resistance adjustment portion 312b can only reduce the resistance difference between the first clock signal line 31 and the second clock signal line 32, but cannot completely eliminate the resistance difference.

[0090] In some embodiments, the remaining space near the opening side of the first sub-segment 3121 and the third sub-segment 3123 is large enough, and the added resistance adjustment part 312b can reduce or eliminate the resistance difference between two adjacent clock signal lines (it can be inferred that it also means reducing the resistance difference between two clock signal lines corresponding to adjacent rows of pixels), improve the problem of fine horizontal lines, and the clock signal line can adopt the wiring method corresponding to Example 1.

[0091] Figure 5 A schematic diagram of the wiring of a clock signal line under Example 1 provided in an embodiment of the present disclosure, such as Figure 5 As shown, in combination with the structure of the above-mentioned clock signal lines, the plurality of clock signal lines include N; the gate drive circuit 1 includes M cascaded shift registers; wherein N is an even number greater than or equal to 6; M is an integer greater than or equal to N; in the first direction X, the N clock signal lines from the edge area BB to the display area A are respectively recorded as the 1st to the Nth clock signal lines. The M shift registers are arranged side by side along the second direction Y, and are divided into P groups of shift register groups along the second direction Y, each group of shift register groups includes N shift registers; wherein P is an integer greater than or equal to 1; wherein the rth clock signal line is electrically connected to the rth shift register. r is 1 to N. The rth shift register is electrically connected to the clock signal line CLK_(N-r+1).

[0092] Exemplarily, N is 6.

[0093] The present disclosure is applied to large-size and narrow-frame display products, and N clock signal lines are set to control GOA, where N is an even number greater than or equal to 6 to ensure the charging time of each row of pixels. For example, N includes but is not limited to 8, 10, 12, and 16. For ease of understanding, the present disclosure embodiment is described by taking N=8 as an example, and the wiring principles of other examples of the number of lines are similar, so they are not listed one by one.

[0094] The remaining space near the opening of the first sub-segment 3121 and the third sub-segment 3123 is insufficient. Although the resistance adjustment part 312b is added to reduce the resistance difference between two adjacent clock signal lines, the more the number of clock signal lines, the more resistance adjustment parts are provided, which may not be enough to compensate for the resistance difference. That is, the resistance difference between the two clock signal lines corresponding to the adjacent rows of pixels is still large. f The display requirements will still not be met, which means that there is still a problem of fine horizontal stripes. At this time, the clock signal line can use the wiring methods of Examples 2 to 5 to further disperse the resistance difference of the two clock signal lines corresponding to the adjacent rows of pixels, so that the resistance difference is relatively evenly distributed.

[0095] Figure 6 This is a schematic diagram of the wiring of the clock signal line in Example 2 provided in an embodiment of the present disclosure, Figure 7 This is a schematic diagram of the wiring of the clock signal line in Example 3 provided in an embodiment of the present disclosure, Figure 8 A schematic diagram of the wiring of a clock signal line in Example 4 provided in an embodiment of the present disclosure, Fig. 9 This is a schematic diagram of the wiring of the clock signal line in Example 5 provided in the embodiment of the present disclosure, Fig.10 A schematic diagram of the wiring of clock signal lines in Example 6 provided in an embodiment of the present disclosure.

[0096] In some embodiments, in combination with the structure of the above clock signal line, such as Figure 6 to Figure 10 As shown, the plurality of clock signal lines include N; the gate drive circuit 1 includes M cascaded shift registers; wherein N is an even number greater than or equal to 6, for example, N=8; M is an integer greater than or equal to N; a clock signal line is electrically connected to a shift register; and the connecting lines of the centers of the connecting parts 2 corresponding to each clock signal line are not on the same straight line.

[0097] Since the connecting portion 2 includes multiple sub-portions located in different layers, the so-called "center of the connecting portion 2" here can be understood as the center of the positive projection of the entire connecting portion 2 (the first sub-portion, the second sub-portion and the third sub-portion) on the substrate.

[0098] In application scenarios with many clock signal lines, such as Figure 5 As shown, the 8th clock signal line electrically connected to the 8th shift register corresponding to the adjacent row of pixels is separated from the 1st clock signal line electrically connected to the 9th shift register by 6 clock signal lines. According to the above analysis, the load difference between the 1st clock signal line and the 8th clock signal line is the largest. Although the resistance difference △R between the adjacent clock signal lines has been compensated by adding the above resistance adjustment unit, the sum of the 7 △Rs between the 8th clock signal line and the 1st clock signal line (7×△R) will still cause a larger t between the 8th shift register and the 9th shift register. f Differences, resulting in fine horizontal stripes.

[0099] Based on this, the present disclosure further improves the arrangement of the clock signal lines (e.g., CLK8-1) electrically connected to the sequentially arranged shift registers, and the connecting lines of the centers of the connecting parts 2 corresponding to each clock signal line are not on the same straight line, thereby dispersing the resistance difference between the two clock signal lines corresponding to adjacent rows of pixels.

[0100] Optionally, the kth shift register is cascaded with the k+Nth shift register; k is 1 to N. For example, N=8, the 1st shift register is cascaded with the 9th shift register, thereby providing sufficient pulse width to ensure charging time.

[0101] In some embodiments, Figure 6 to Figure 10 As shown, the number of clock signal lines sandwiched between any two adjacent shift registers connected to the clock signal lines does not exceed 3, which means that the resistance difference between the two clock signal lines corresponding to the adjacent row pixels does not exceed 4△R. Experimental tests show that when the frame space is sufficient, the additional resistance adjustment part 312b has ensured that △R is very small (for example, △R<4%R, R represents the maximum resistance of the clock signal line), and does not exceed 4△R, the load uniformity condition is met, and fine horizontal stripes can be eliminated.

[0102] In some embodiments, Figure 8 to Figure 10 As shown, the number of clock signal lines sandwiched between any two adjacent shift registers connected to the clock signal lines does not exceed 2, which means that the resistance difference between the two clock signal lines corresponding to the adjacent row pixels does not exceed 3△R. Experimental tests show that the frame space is insufficient, and the additional resistance adjustment part 312b is not enough to eliminate the resistance difference. At this time, △R is greater than 4%R. At this time, when it does not exceed 3△R, the load uniformity condition is met, and fine horizontal stripes can be eliminated.

[0103] In some embodiments, Figure 6 and Figure 7As shown, N clock signal lines are arranged side by side along a first direction X, and are divided into Q clock signal line groups along the first direction X, each clock signal line group includes q clock signal lines; wherein Q is an integer from 2 to N / 2; q is an integer from 2 to N / 2; for any group of clock signal line groups, the center of the connecting portion 2 corresponding to each clock signal line is connected to form a straight line; for different groups of clock signal line groups, the extension direction of the straight line connected to the center of the connecting portion 2 is different.

[0104] N=8, Q=2, q=4, the first group of clock signal lines includes the first to fourth clock signal lines, and the second group of clock signal lines includes the fifth to eighth clock signal lines. Figure 6 As shown, the first shift register is electrically connected to the fourth clock signal line (CLK_8); the second shift register is electrically connected to the third clock signal line (CLK_7); the third shift register is electrically connected to the second clock signal line (CLK_6); the fourth shift register is electrically connected to the first clock signal line (CLK_5); the fifth shift register is electrically connected to the fifth clock signal line (CLK_4); the sixth shift register is electrically connected to the sixth clock signal line (CLK_3); the seventh shift register is electrically connected to the seventh clock signal line (CLK_2); and the eighth shift register is electrically connected to the eighth clock signal line (CLK_1). In this example, the arrangement order of the AN clock signal lines from the edge area BB to the display area A in the first direction X is CLK_5→CLK_6→CLK_7→CLK_8→CLK_4→CLK_3→CLK_2→CLK_1. Compared with the arrangement mode of CLK_8→CLK_7→CLK_6→CLK_5→CLK_4→CLK_3→CLK_2→CLK_1 in the traditional technology, the resistance difference of the two clock signal lines corresponding to the pixels in adjacent rows is further dispersed, so that the resistance difference is relatively evenly distributed, thereby making t f The differences are relatively evenly distributed, improving the problem of fine horizontal lines.

[0105] Another example is Figure 7As shown, the first shift register is electrically connected to the first clock signal line (CLK_8); the second shift register is electrically connected to the second clock signal line (CLK_7); the third shift register is electrically connected to the third clock signal line (CLK_6); the fourth shift register is electrically connected to the fourth clock signal line (CLK_5); the fifth shift register is electrically connected to the eighth clock signal line (CLK_4); the sixth shift register is electrically connected to the seventh clock signal line (CLK_3); the seventh shift register is electrically connected to the sixth clock signal line (CLK_2); and the eighth shift register is electrically connected to the fifth clock signal line (CLK_1). In this example, the arrangement order of the AN clock signal lines from the edge area BB to the display area A in the first direction X is CLK_8→CLK_7→CLK_6→CLK_5→CLK_1→CLK_2→CLK_3→CLK_4.

[0106] In some embodiments, Figure 8 As shown, M shift registers are arranged side by side along the second direction Y, and are divided into P shift register groups along the second direction Y, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1. For any group of shift register groups, the number of clock signal lines between the ith shift register electrically connected to the clock signal line and the ith+1th shift register electrically connected to the clock signal line is x; the number of clock signal lines between the ith+1th shift register electrically connected to the clock signal line and the ith+2nd shift register electrically connected to the clock signal line is y; the number of clock signal lines between the ith+2nd shift register electrically connected to the clock signal line and the ith+3rd shift register electrically connected to the clock signal line is z; the number of clock signal lines between the ith+3rd shift register electrically connected to the clock signal line and the ith+4th shift register electrically connected to the clock signal line is w; i is 1 to (N-5); wherein x=z, y=w.

[0107] For example, Figure 8As shown, the first shift register is electrically connected to the fifth clock signal line (CLK_8), the second shift register is electrically connected to the second clock signal line (CLK_7), the third shift register is electrically connected to the first clock signal line (CLK_6), the fourth shift register is electrically connected to the fourth clock signal line (CLK_5), the fifth shift register is electrically connected to the third clock signal line (CLK_4), the sixth shift register is electrically connected to the sixth clock signal line (CLK_3), the seventh shift register is electrically connected to the seventh clock signal line (CLK_2), and the eighth shift register is electrically connected to the eighth clock signal line (CLK_1). i≤(8-5), therefore, taking the first shift register group, i=1 as an example, two clock signal lines are sandwiched between the fifth clock signal line (CLK_8) and the second clock signal line (CLK_7), that is, x=2; no clock signal line is sandwiched between the second clock signal line (CLK_7) and the first clock signal line (CLK_6), that is, y=0; two clock signal lines are sandwiched between the first clock signal line (CLK_6) and the fourth clock signal line (CLK_5), that is, z=2; no clock signal line is sandwiched between the fourth clock signal line (CLK_5) and the third clock signal line (CLK_4), that is, w=0. At this time, x=z, y=w.

[0108] In this embodiment, the arrangement order of the N clock signal lines is CLK_6→CLK_7→CLK_4→CLK_5→CLK_8→CLK_3→CLK_2→CLK_1, which disperses the resistance difference of the two clock signal lines corresponding to the pixels in adjacent rows, so that the resistance difference is relatively evenly distributed, so that t f The differences are relatively evenly distributed, improving the problem of fine horizontal lines.

[0109] In some embodiments, Fig. 9 As shown, M shift registers are arranged side by side along the second direction Y, and are divided into P shift register groups along the second direction Y, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1; for any group of shift register groups, the number of clock signal lines between the jth shift register electrically connected to the clock signal line and the j+1th shift register electrically connected to the clock signal line is m; the number of clock signal lines between the j+1th shift register electrically connected to the clock signal line and the j+2th shift register electrically connected to the clock signal line is n; j is 1 to (N-2); wherein, |mn|≤1, wherein, || represents an absolute value.

[0110] For example, Fig. 9As shown, the first shift register is electrically connected to the sixth clock signal line (CLK_8), the second shift register is electrically connected to the eighth clock signal line (CLK_7), the third shift register is electrically connected to the fifth clock signal line (CLK_6), the fourth shift register is electrically connected to the third clock signal line (CLK_5), the fifth shift register is electrically connected to the first clock signal line (CLK_4), the sixth shift register is electrically connected to the second clock signal line (CLK_3), the seventh shift register is electrically connected to the fourth clock signal line (CLK_2), and the eighth shift register is electrically connected to the seventh clock signal line (CLK_1).

[0111] like Fig. 9 As shown, taking the first shift register group, j is 1 as an example, one clock signal line is sandwiched between the sixth clock signal line (CLK_8) and the eighth clock signal line (CLK_7), that is, m=1; two clock signal lines are sandwiched between the eighth clock signal line (CLK_7) and the fifth clock signal line (CLK_6), that is, n=2. |mn|=1.

[0112] like Fig. 9 As shown, taking the first shift register group, j is 2 as an example, m=2, n=1, |mn|=1.

[0113] like Fig. 9 As shown, taking the first shift register group, j is 3 as an example, m=1, n=1, |mn|=0.

[0114] like Fig. 9 As shown, taking the first shift register group, j is 4 as an example, m=1, n=0, |mn|=1.

[0115] like Fig. 9 As shown, taking the first shift register group, j is 5 as an example, m=0, n=1, |mn|=1.

[0116] like Fig. 9 As shown, taking the first shift register group, j is 6 as an example, m=1, n=2, |mn|=1.

[0117] In this embodiment, the arrangement order of the N clock signal lines is CLK_4→CLK_3→CLK_5→CLK_2→CLK_6→CLK_8→CLK_1→CLK_7, which not only disperses the resistance difference of the two clock signal lines corresponding to the pixels in adjacent rows, but also calculates the difference value, and the resistance difference is distributed more evenly, so that t f The differences are relatively evenly distributed, improving the problem of fine horizontal lines.

[0118] In some embodiments, Fig.10As shown, M shift registers are arranged side by side along the second direction Y, and are divided into P shift register groups along the second direction Y, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1; for any group of shift register groups, the sth shift register is electrically connected to the clock signal line, and the number of clock signal lines sandwiched between the (s+1)th shift register is electrically connected to the clock signal line is equal to the number of clock signal lines sandwiched between the (Ns)th shift register is electrically connected to the clock signal line and the (N-s+1)th shift register is electrically connected to the clock signal line; s is 1 to (N / 2-1).

[0119] For example, Fig.10 As shown, the first shift register is electrically connected to the fourth clock signal line (CLK_8), the second shift register is electrically connected to the seventh clock signal line (CLK_7), the third shift register is electrically connected to the eighth clock signal line (CLK_6), the fourth shift register is electrically connected to the sixth clock signal line (CLK_5), the fifth shift register is electrically connected to the third clock signal line (CLK_4), the sixth shift register is electrically connected to the first clock signal line (CLK_3), the seventh shift register is electrically connected to the second clock signal line (CLK_2), and the eighth shift register is electrically connected to the fifth clock signal line (CLK_1).

[0120] like Fig.10 As shown, taking the first shift register group, s being 1 as an example, the number of clock signal lines sandwiched between the 4th clock signal line (CLK_8) and the 7th clock signal line (CLK_7) is equal to the number of clock signal lines sandwiched between the 2nd clock signal line (CLK_2) and the 5th clock signal line (CLK_1), both being two.

[0121] like Fig.10 As shown, taking the first shift register group, s is 2 as an example, the number of clock signal lines sandwiched between the 7th clock signal line (CLK_7) and the 8th clock signal line (CLK_6) is equal to the number of clock signal lines sandwiched between the 1st clock signal line (CLK_3) and the 2nd clock signal line (CLK_2), both of which are 0.

[0122] like Fig.10 As shown, taking the first shift register group, s is 3 as an example, the number of clock signal lines sandwiched between the 8th clock signal line (CLK_6) and the 6th clock signal line (CLK_5) is equal to the number of clock signal lines sandwiched between the 3rd clock signal line (CLK_4) and the 1st clock signal line (CLK_3), both of which are 2.

[0123] In this embodiment, the number of interposed lines is symmetrically arranged, and the arrangement order of the N clock signal lines is CLK_3→CLK_2→CLK_4→CLK_8→CLK_1→CLK_5→CLK_7→CLK_6. The number of interposed clock signal lines shows a trend of gradually decreasing and then gradually increasing, that is, 2→0→1→2→1→0→2. Not only the resistance difference of the two clock signal lines corresponding to the pixels in adjacent rows is dispersed, but also the difference shows a trend of gradually increasing and decreasing, thereby avoiding the t caused by a sudden drop or a sudden increase. f Difference, improve the problem of fine horizontal lines.

[0124] In some embodiments, if the layout space of the resistance adjustment part 312b is limited, and the resistance difference between the first clock signal line 31 having the resistance adjustment part 312b and the second clock signal line 32 is still large, the resistance of the second clock signal line 32 can be further increased to compensate for the resistance difference between the first clock signal line 31 and the second clock signal line 32.

[0125] Fig.11 A schematic diagram of a clock signal line structure provided by an embodiment of the present disclosure is shown in FIG. Fig.11 As shown, Figure 3b Taking the clock signal line shown as an example, at least part of the clock signal line has a straight portion 321 and a serpentine line 322 connected in series; the serpentine line 322 includes a first bend 3221 and a second bend 3222 connecting two adjacent first bends 3221. The extension direction of the straight portion 321 is the same as the overall extension direction of the clock signal line, that is, the second direction Y. The extension direction of the first bend 3221 is the line width direction of the clock signal line, and the extension direction of the second bend 3222 is the overall extension direction of the clock signal line, that is, the second direction Y. The number of first bends 3221 on the second clock signal line 32 is greater than the number of first bends 3221 on the first clock signal line 31.

[0126] It should be noted that the serpentine trace 322 is provided in the present disclosure to compensate for the resistance difference between the first clock signal line 31 and the second clock signal line 32. Therefore, the extension length of the serpentine trace 322 in the second direction Y can be designed according to the resistance of the first clock signal line 31 so that the resistance difference between the two is approximately zero.

[0127] The clock signal line of this embodiment adopts a serpentine routing structure, which improves the resistance and makes up for the resistance difference between the first clock signal line 31 and the second clock signal line 32, thereby improving the fine horizontal lines.

[0128] Alternatively, if Fig.11As shown, the extension length of the first bending portion 3221 (ie, the length of the first bending portion 3221 in the extension direction X) does not exceed the line width of the straight portion 321, that is, the original wiring space is used without occupying other wiring space, thereby ensuring the realization of a narrow frame.

[0129] Optionally, the line width of the serpentine trace 322 (ie, the length of the first bend portion 3221 in the extension direction X) is smaller than the line width of the straight portion 321, which is more conducive to increasing a greater resistance within a shorter line length and saving wiring space.

[0130] Optionally, there is a certain gap between adjacent first bending portions 3221 .

[0131] Optionally, the length of the second bending portion 3222 in the extension direction Y is smaller than the length of the first bending portion 3221 in the extension direction X.

[0132] In some embodiments, if the layout space of the resistance adjustment portion 312b is limited, and the resistance difference between the first clock signal line 31 having the resistance adjustment portion 312b and the second clock signal line 32 is still large, the line width of the first clock signal line 31 can be further increased to reduce the resistance of the first clock signal line 31, thereby compensating for the resistance difference between the first clock signal line 31 and the second clock signal line 32.

[0133] Fig.12 A schematic diagram of the structure of another clock signal line provided in an embodiment of the present disclosure, such as Fig.12 As shown, the line width of the main extension portion 311 of the first clock signal line 31 is the same as the line width of the sub-lead portion 312a; the line width of the main extension portion 311 of the first clock signal line 31 is greater than or equal to the maximum line width of the second clock signal line 32; and / or, the line width of the sub-lead portion 312a of the first clock signal line 31 is greater than or equal to the maximum line width of the second clock signal line 32.

[0134] In this embodiment, by increasing the line width of the main extension portion 311 or the sub-lead portion 312a of the first clock signal line 31, the resistance of the first clock signal line 31 is increased, thereby reducing the resistance difference between the first clock signal line 31 and the second clock signal line 32, and effectively improving the fine horizontal lines.

[0135] In this embodiment, different clock signal lines are routed with different line widths. The longer the signal line is, the larger the line width is, so that the effects of increasing line width on reducing resistance and increasing routing distance on increasing resistance offset each other, ultimately achieving equal resistance wiring.

[0136] This embodiment uses different line widths to route clock signal lines, so that all clock signal lines have the same resistance load, so that the gate drive signal of each row of pixels can be kept consistent, thereby achieving uniform visual effects across the entire display panel.

[0137] In addition, the embodiment of the present disclosure further provides a display device, which includes the display panel of any one of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.

[0138] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: It comprises a base substrate, a gate drive circuit and a plurality of clock signal lines arranged on the base substrate; the clock signal lines are electrically connected to the gate drive circuit via a connecting portion across layers; For any two adjacent clock signal lines, one of them is recorded as a first clock signal line, and the other is recorded as a second clock signal line; the connection portion corresponding to the first clock signal line is recorded as a first connection portion; the connection portion corresponding to the second clock signal line is recorded as a second connection portion; The first clock signal line includes a main body extension portion and a surrounding portion connected to the main body extension portion; the orthographic projection of the surrounding portion on the base substrate half surrounds the orthographic projection of the first connecting portion on the base substrate; or the orthographic projection of the surrounding portion on the base substrate half surrounds the orthographic projection of the second connecting portion on the base substrate; The surrounding portion includes a sub-lead portion and a resistance adjustment portion connected to a side of the sub-lead portion close to the second clock signal line.

2. The display panel according to claim 1, characterized in that: The opening of the sub-lead portion faces the second clock signal line; the sub-lead portion comprises a first sub-segment, a second sub-segment and a third sub-segment connected in series in sequence, and the first sub-segment, the second sub-segment and the third sub-segment extend in different directions; At least one of the first sub-segment and the third sub-segment is connected to the resistance adjusting part; when the orthographic projection of the sub-lead part on the base substrate half surrounds the orthographic projection of the first connecting part on the base substrate, the first connecting part is connected to the second sub-segment; when the orthographic projection of the sub-lead part on the base substrate half surrounds the orthographic projection of the second connecting part on the base substrate, the second sub-segment is arranged opposite to the second connecting part.

3. The display panel according to claim 2, characterized in that: With respect to the first sub-segment and the resistance adjusting portion connected thereto, the resistance adjusting portion at least partially covers a surface of the first sub-segment close to the opening; With respect to the third subsegment and the resistance adjusting portion connected thereto, the resistance adjusting portion at least partially covers a surface of the third subsegment close to the opening.

4. The display panel according to claim 2, characterized in that: The display panel comprises a display area and an edge area surrounding the display area, the plurality of clock signal lines and the gate driving circuit are both located in the edge area, and the plurality of clock signal lines are arranged on a side of the gate driving circuit away from the display area; The first clock signal line is farther away from the display area than the second clock signal line; or the first clock signal line is closer to the display area than the second clock signal line.

5. The display panel according to claim 1, characterized in that: The plurality of clock signal lines include N; the gate drive circuit includes M cascaded shift registers; wherein N is an even number greater than or equal to 6; M is an integer greater than or equal to N; one of the clock signal lines is electrically connected to one of the shift registers; The lines connecting the centers of the connecting parts corresponding to each of the clock signal lines are not on the same straight line.

6. The display panel according to claim 5, characterized in that: The number of clock signal lines sandwiched between any two adjacent clock signal lines connected to the shift registers does not exceed 3.

7. The display panel according to claim 6, characterized in that: The N clock signal lines are arranged side by side along a first direction, and are divided into Q clock signal line groups along the first direction, each clock signal line group includes q clock signal lines; wherein Q is an integer between 2 and N / 2; and q is an integer between 2 and N / 2; For any group of the clock signal lines, the centers of the connection parts corresponding to each of the clock signal lines are connected into a straight line; For different groups of the clock signal line groups, the extending directions of the straight lines connected by the centers of the connecting parts are different.

8. The display panel according to claim 5, characterized in that: The M shift registers are arranged side by side along the second direction, and are divided into P shift register groups along the second direction, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1; For any group of the shift registers, the first shift register is electrically connected to the (N / 2+1)th clock signal line, or the first shift register is electrically connected to the (N / 2-1)th clock signal line; For any group of the shift register groups, the number of clock signal lines between the i-th shift register electrically connected to the clock signal line and the i+1-th shift register electrically connected to the clock signal line is x; the number of clock signal lines between the i+1-th shift register electrically connected to the clock signal line and the i+2-th shift register electrically connected to the clock signal line is y; the number of clock signal lines between the i+2-th shift register electrically connected to the clock signal line and the i+3-th shift register electrically connected to the clock signal line is z; the number of clock signal lines between the i+3-th shift register electrically connected to the clock signal line and the i+4-th shift register electrically connected to the clock signal line is w; i is 1 to (N-5); wherein x=z, y=w.

9. The display panel according to claim 5, characterized in that: The number of clock signal lines sandwiched between any two adjacent clock signal lines connected to the shift registers does not exceed 2.

10. The display panel according to claim 9, characterized in that: The M shift registers are arranged side by side along the second direction, and are divided into P shift register groups along the second direction, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1; For any group of the shift register groups, the number of clock signal lines between the jth shift register electrically connected to the clock signal line and the j+1th shift register electrically connected to the clock signal line is m; the number of clock signal lines between the j+1th shift register electrically connected to the clock signal line and the j+2th shift register electrically connected to the clock signal line is n; j is 1 to (N-2); wherein, |mn|≤1, wherein || represents an absolute value.

11. The display panel according to claim 9, characterized in that: The M shift registers are arranged side by side along the second direction, and are divided into P shift register groups along the second direction, each shift register group includes N shift registers; wherein P is an integer greater than or equal to 1; For any group of shift register groups, the sth shift register is electrically connected to the clock signal line, and the number of clock signal lines sandwiched between the clock signal lines electrically connected to the (s+1)th shift register is equal to the number of clock signal lines sandwiched between the clock signal line electrically connected to the (Ns)th shift register and the clock signal line electrically connected to the (N-s+1)th shift register; s is 1 to (N / 2-1).

12. The display panel according to claim 5, characterized in that: The kth shift register is cascaded with the k+Nth shift register; k is 1 to N.

13. The display panel according to claim 1, characterized in that: At least part of the clock signal line has a straight line portion and a serpentine line connected in series; the serpentine line includes a first bending portion and a second bending portion connecting two adjacent first bending portions; the extension direction of the first bending portion is the line width direction of the clock signal line, and the extension direction of the second bending portion is the overall extension direction of the clock signal line; The number of the first bending portions on the second clock signal line is greater than the number of the first bending portions on the first clock signal line.

14. The display panel according to claim 13, characterized in that: The extension length of the first bending portion does not exceed the line width of the straight line portion.

15. The display panel according to claim 1, characterized in that: The line width of the main extension portion of the first clock signal line is the same as the line width of the sub-lead portion; The line width of the main extension portion of the first clock signal line is greater than or equal to the maximum line width of the second clock signal line; and / or the line width of the sub-lead portion of the first clock signal line is greater than or equal to the maximum line width of the second clock signal line.

16. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 15.

Images