Display substrate and display device

Abstract

The utility model discloses a display substrate. Comprising a substrate, a plurality of first light-emitting elements for emitting first color light, a plurality of second light-emitting elements for emitting second color light, a plurality of third light-emitting elements for emitting third color light, a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of third pixel circuits, wherein the first light-emitting elements, the second light-emitting elements and the third light-emitting elements are located in a first display area; and the first pixel circuits, the second pixel circuits and the third pixel circuits are located in a second display area. The first pixel circuit is connected with at least two first light-emitting elements through a first connecting line, the second pixel circuit is connected with at least one second light-emitting element through a second connecting line, and the third pixel circuit is connected with at least one third light-emitting element through a third connecting line. The length of the first connecting line is smaller than that of the second connecting line and smaller than that of the third connecting line; the plurality of first connecting lines connected with the plurality of first pixel circuits are located on the same conductive layer. According to the utility model, the load difference of the plurality of first connecting lines can be improved.

Description

Technical Field

[0001] The utility model relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. The under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of the display device. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] In order to solve the problem that the number and arrangement space of conductive connection lines in an external pixel circuit solution are limited by the size of the pixel circuit and the light-emitting element, an embodiment of the utility model provides a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, including: a substrate, a plurality of first-region light-emitting elements, and a plurality of first-type pixel circuits. The substrate includes: a first display area and a second display area located at least on one side of the first display area. The plurality of first-region light-emitting elements are located in the first display area, including: a plurality of first light-emitting elements emitting first color light, a plurality of second light-emitting elements emitting second color light, and a plurality of third light-emitting elements emitting third color light. The plurality of first-type pixel circuits are located in the second display area, including: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits. The first pixel circuit is connected to at least two first light-emitting elements through a first connecting line, the second pixel circuit is connected to at least one second light-emitting element through a second connecting line, and the third pixel circuit is connected to at least one third light-emitting element through a third connecting line. The length of the first connecting line is less than the length of the second connecting line, and less than the length of the third connecting line; the plurality of first connecting lines connected to the plurality of first pixel circuits are located in the same conductive layer.

[0006] In some exemplary embodiments, the first display area is provided with a plurality of first area display units, each of which includes: two first light-emitting elements, one second light-emitting element and one third light-emitting element; the first pixel circuit is connected to the two first light-emitting elements of a first area display unit via a first connecting line.

[0007] In some exemplary embodiments, the conductive layer where the plurality of second connection lines connected to the plurality of second pixel circuits and the plurality of third connection lines connected to the plurality of third pixel circuits are located is different from the conductive layer where the plurality of first connection lines are located.

[0008] In some example embodiments, the plurality of second connection lines and the plurality of third connection lines are located on a side of the plurality of first connection lines away from the substrate.

[0009] In some exemplary embodiments, the display substrate further includes: a plurality of first invalid pixel circuits located in the second display area, the plurality of first invalid pixel circuits being located on a side of the plurality of first type pixel circuits away from the first display area. The display substrate further includes: a plurality of data connection lines located in the second display area, the plurality of data connection lines including: a plurality of first data connection lines, a plurality of second data connection lines, and a plurality of third data connection lines; the first data connection lines are connected to a plurality of first pixel circuits arranged along the first direction, the second data connection lines are connected to a plurality of second pixel circuits and a plurality of third pixel circuits arranged along the first direction, the third data connection lines are connected to a plurality of first invalid pixel circuits arranged along the first direction; the plurality of second data connection lines are located on a side of the plurality of first data connection lines away from the first display area, and the plurality of third data connection lines are located on a side of the plurality of second data connection lines away from the first display area.

[0010] In some exemplary embodiments, the display substrate further includes: a plurality of second-region light-emitting elements and a plurality of second-type pixel circuits located in the second display area, the plurality of second-region light-emitting elements and the plurality of second-type pixel circuits being electrically connected one-to-one; the plurality of second-region light-emitting elements including: a plurality of fourth light-emitting elements emitting first color light, a plurality of fifth light-emitting elements emitting second color light, and a plurality of sixth light-emitting elements emitting third color light. The display substrate further includes: a plurality of first data lines, the first data lines being configured to provide data signals to a column of second-region light-emitting elements separated by the first display area, the column of second-region light-emitting elements including: a plurality of second-region light-emitting elements arranged along the first direction. Wherein, the first data line providing data signals to the fifth light-emitting element and the sixth light-emitting element is configured to be connected to the second data connection line; the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the third data connection line; or, the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the third data connection line. Wherein, the first light-emitting elements in the even-numbered columns and the first light-emitting elements in the odd-numbered columns are determined according to the order of the first light-emitting elements in the first display area along the second direction, and the second direction intersects with the first direction.

[0011] In some exemplary embodiments, the first data line includes: a first routing segment and a second routing segment located on both sides of the first display area along the first direction. The display substrate further includes: a plurality of first windings and a plurality of second windings, the first windings being connected between the first routing segment of the first data line and a data connection line, and the second windings being connected between the second routing segment of the first data line and the data connection line. The substrate further includes: a frame area located outside the first display area and the second display area, the plurality of first windings being located in the frame area, and the plurality of second windings being located in the second display area.

[0012] In some exemplary embodiments, the plurality of first windings include: a plurality of first-type first windings and a plurality of second-type first windings, and the plurality of first-type first windings and the plurality of second-type first windings are alternately disposed and arranged in different conductive layers.

[0013] In some exemplary embodiments, the first-type first winding wire is connected to the first data connection wire or the third data connection wire, and the second-type first winding wire is connected to the second data connection wire.

[0014] In some exemplary embodiments, the plurality of first-type first windings are located on a side of the plurality of second-type first windings that is away from the substrate.

[0015] In some exemplary embodiments, the first type first winding is directly connected to the first routing segment of the first data line; the second type first winding is connected to the first routing segment of the first data line through a first transfer electrode, the first routing segment of the first data line is located on a side of the first transfer electrode away from the substrate, and the first transfer electrode is located on a side of the second type first winding away from the substrate; the first transfer electrode and the first type first winding are in the same layer structure.

[0016] In some exemplary embodiments, the second type first winding is located in the first source-drain metal layer, the first type first winding is located in the second source-drain metal layer, the first data line is located in the third source-drain metal layer, the third source-drain metal layer is located on the side of the second source-drain metal layer away from the substrate, and the second source-drain metal layer is located on the side of the first source-drain metal layer away from the substrate.

[0017] In some exemplary embodiments, the first type first winding adjacent to the first switching electrode has a straight portion and a folded line portion, the folded line portion is located between two adjacent straight portions and connected to the two straight portions, and the folded line portion bypasses the first switching electrode from one side of the first direction.

[0018] In some exemplary embodiments, the first color light is green light, the second color light is red light, and the third color light is blue light.

[0019] On the other hand, this embodiment provides a display device, including the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate overlaps with the first display area of ​​the display substrate.

[0020] In some exemplary embodiments, the sensor is a camera.

[0021] On the other hand, the present embodiment provides a display substrate, comprising: a substrate, a plurality of first-region light-emitting elements, a plurality of first-type pixel circuits, a plurality of first invalid pixel circuits, a plurality of second-region light-emitting elements, a plurality of second-type pixel circuits, a plurality of data connection lines, and a plurality of first data lines. The substrate comprises: a first display area and a second display area located at least on one side of the first display area. The plurality of first-region light-emitting elements are located in the first display area, comprising: a plurality of first light-emitting elements emitting first color light, a plurality of second light-emitting elements emitting second color light, and a plurality of third light-emitting elements emitting third color light. The plurality of first-type pixel circuits are located in the second display area, comprising: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits, the first pixel circuits being connected to at least two first light-emitting elements through a first connection line, the second pixel circuits being connected to at least one second light-emitting element through a second connection line, and the third pixel circuits being connected to at least one third light-emitting element through a third connection line. The plurality of first invalid pixel circuits are located in the second display area, and are located on a side of the plurality of first-type pixel circuits away from the first display area. A plurality of second-region light-emitting elements and a plurality of second-type pixel circuits are located in the second display area, the plurality of second-region light-emitting elements and the plurality of second-type pixel circuits are electrically connected one by one, the plurality of second-region light-emitting elements include: a plurality of fourth light-emitting elements emitting first color light, a plurality of fifth light-emitting elements emitting second color light, and a plurality of sixth light-emitting elements emitting third color light. A plurality of data connection lines are located in the second display area, including: a plurality of first data connection lines, a plurality of second data connection lines, and a plurality of third data connection lines, the first data connection lines are connected to a plurality of first pixel circuits arranged along a first direction, the second data connection lines are connected to a plurality of second pixel circuits and a plurality of third pixel circuits arranged along the first direction, the third data connection lines are connected to a plurality of first invalid pixel circuits arranged along the first direction; the plurality of second data connection lines are located on a side of the plurality of first data connection lines away from the first display area, and the plurality of third data connection lines are located on a side of the plurality of second data connection lines away from the first display area. The first data line is configured to provide a data signal to a column of second-region light-emitting elements separated by the first display area, and the column of second-region light-emitting elements includes: a plurality of second-region light-emitting elements arranged along the first direction.Wherein, the first data line providing data signals to the fifth light-emitting element and the sixth light-emitting element is configured to be connected to the second data connection line; the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the third data connection line; or, the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the third data connection line. The first light-emitting elements in the even-numbered columns and the first light-emitting elements in the odd-numbered columns are determined according to the order of the first light-emitting elements in the first display area along the second direction, and the second direction intersects with the first direction.

[0022] In some exemplary embodiments, the first data line includes: a first routing segment and a second routing segment located on both sides of the first display area along the first direction. The display substrate further includes: a plurality of first windings and a plurality of second windings, the first windings being connected between the first routing segment of the first data line and a data connection line, and the second windings being connected between the second routing segment of the first data line and the data connection line. The substrate further includes: a frame area located outside the first display area and the second display area, the plurality of first windings being located in the frame area, and the plurality of second windings being located in the second display area.

[0023] In some exemplary embodiments, the plurality of first windings include: a plurality of first-type first windings and a plurality of second-type first windings, and the plurality of first-type first windings and the plurality of second-type first windings are alternately disposed and arranged in different conductive layers.

[0024] In some exemplary embodiments, the first color light is green light, the second color light is red light, and the third color light is blue light.

[0025] The display substrate provided in this embodiment can improve the load difference of multiple first connecting lines by setting the length of the first connecting line connected to the first light-emitting element to be shorter than the lengths of the second connecting line and the third connecting line, and multiple first connecting lines are set in the same conductive layer, thereby improving the display effect of the first light-emitting element in the first display area.

[0026] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0028] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 2 A schematic diagram of a planar structure of a display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0030] Figure 3 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0031] Figure 4 A partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 5 A schematic diagram of the connection between the first-region light-emitting element and the first-type pixel circuit according to at least one embodiment of the present disclosure;

[0033] Figure 6 A schematic diagram of a partial structure of a first display area of ​​at least one embodiment of the present disclosure;

[0034] Figure 7 A schematic diagram of a data cable winding design according to at least one embodiment of the present disclosure;

[0035] Figure 8 A schematic diagram of a partial structure of a first border area of ​​at least one embodiment of the present disclosure;

[0036] Fig. 9 for Figure 8 A partial enlarged schematic diagram of the middle area S1;

[0037] Fig.10 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0039] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0040] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0041] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0042] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal connection of two elements. For ordinary technicians in this field, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "connection" may include "electrical connection", and "electrical connection" may include the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.

[0043] In this specification, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0044] In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, the second electrode may be a drain electrode. In addition, the gate electrode may also be referred to as a control electrode. In the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0045] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0046] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0047] In this specification, "about" and "substantially" mean that the limits are not strictly defined and the process and measurement errors are allowed. In this disclosure, "same" includes the case where the numerical value differs within 10%, such as the case where the numerical value differs within 5%.

[0048] In this specification, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" means "the main part of A extends along direction B".

[0049] In this specification, "A and B are of the same layer structure" means that A and B are formed simultaneously by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0050] The "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.

[0051] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and in-screen hole have appeared one after another. These technologies are to reduce the area occupied by the camera by digging holes in part of the display area and placing a camera under the hole area, thereby increasing the screen-to-body ratio. However, the above technology requires digging out part of the display area, which will cause part of the display screen to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit externalization method is usually used in the camera area under the screen.

[0052] The external pixel circuit method refers to setting the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area, and improving the light transmittance of the under-screen camera area by arranging the light-emitting element and the pixel circuit separately. Since there is no pixel circuit in the under-screen camera area, there is no other light-shielding layer in this area except the anode of the light-emitting element, so a higher light transmittance can be achieved. However, in this way, the pixel circuit and the light-emitting element need to be electrically connected through a conductive connecting wire, and the number and arrangement space of the conductive connecting wires arranged in a single layer are limited by the size of the pixel circuit and the light-emitting element. Moreover, in this way, it is also necessary to design the winding of the data line separated by the under-screen camera area. The winding design of the data line has problems such as occupying a large space and limiting the size of the frame.

[0053] The present embodiment provides a display substrate, comprising: a substrate, a plurality of first-region light-emitting elements, and a plurality of first-type pixel circuits. The substrate comprises: a first display area and a second display area located at least on one side of the first display area. The plurality of first-region light-emitting elements are located in the first display area, and include: a plurality of first light-emitting elements emitting first color light, a plurality of second light-emitting elements emitting second color light, and a plurality of third light-emitting elements emitting third color light. The plurality of first-type pixel circuits are located in the second display area, and include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits. The first pixel circuit is connected to at least two first light-emitting elements through a first connecting line, the second pixel circuit is connected to at least one second light-emitting element through a second connecting line, and the third pixel circuit is connected to at least one third light-emitting element through a third connecting line. The length of the first connecting line is less than the length of the second connecting line, and less than the length of the third connecting line; the plurality of first connecting lines connected to the plurality of first pixel circuits are located in the same conductive layer.

[0054] The display substrate provided in this embodiment can improve the load difference of multiple first connecting lines by setting the length of the first connecting line connected to the first light-emitting element to be shorter than the lengths of the second connecting line and the third connecting line, and multiple first connecting lines are set in the same conductive layer, thereby improving the display effect of the first light-emitting element in the first display area.

[0055] In some exemplary embodiments, the first display area may be provided with a plurality of first area display units, each of which may include: two first light emitting elements, one second light emitting element, and one third light emitting element. The first pixel circuit may be connected to the two first light emitting elements of a first area display unit via a first connecting line. In this example, the number of first connecting lines can be reduced by adopting a one-drive-two design for the first light emitting element, that is, one first pixel circuit drives two first light emitting elements to emit light.

[0056] In some exemplary embodiments, the conductive layer where the plurality of second connection lines connected to the plurality of second pixel circuits and the plurality of third connection lines connected to the plurality of third pixel circuits are located may be different from the conductive layer where the plurality of first connection lines are located. In some examples, the plurality of second connection lines and the plurality of third connection lines may be located on the side of the plurality of first connection lines away from the substrate. For example, the display substrate may include: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer sequentially arranged in a direction away from the substrate, the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer may be made of transparent conductive materials, a plurality of first connection lines may be located in the first conductive connection layer, and a plurality of second connection lines and a plurality of third connection lines may be located in the second conductive connection layer and the third conductive connection layer. For example, half the number of second connection lines and half the number of third connection lines may be located in the second conductive connection layer, and half the number of second connection lines and half the number of third connection lines may be located in the third conductive connection layer. This example may be beneficial to improving the arrangement space occupied by the plurality of first connection lines, the plurality of second connection lines, and the plurality of third connection lines, and may reduce the load of the first connection line, which is beneficial to ensuring the display effect of the light-emitting element in the first area. However, this embodiment is not limited to this. In some other examples, the plurality of first connection lines may be located in the first conductive connection layer, the plurality of second connection lines may be located in the second conductive connection layer, and the plurality of third connection lines may be located in the third conductive connection layer.

[0057] In some exemplary embodiments, the display substrate may further include: a plurality of first invalid pixel circuits located in the second display area, and the plurality of first invalid pixel circuits may be located on a side of the plurality of first type pixel circuits away from the first display area. The display substrate may further include: a plurality of data connection lines located in the second display area, and the plurality of data connection lines may include: a plurality of first data connection lines, a plurality of second data connection lines, and a plurality of third data connection lines. The first data connection line may be connected to a plurality of first pixel circuits arranged along the first direction, the second data connection line may be connected to a plurality of second pixel circuits and a plurality of third pixel circuits arranged along the first direction, and the third data connection line may be connected to a plurality of first invalid pixel circuits arranged along the first direction. The plurality of second data connection lines may be located on a side of the plurality of first data connection lines away from the first display area, and the plurality of third data connection lines may be located on a side of the plurality of second data connection lines away from the first display area. This example can be advantageous in reducing the length of the first connection line connected to the first pixel circuit by setting the second pixel circuit and the third pixel circuit to be located on a side of the first pixel circuit away from the first display area.

[0058] In some exemplary embodiments, the display substrate may further include: a plurality of second-region light-emitting elements and a plurality of second-type pixel circuits located in the second display area, and the plurality of second-region light-emitting elements and the plurality of second-type pixel circuits may be electrically connected one by one. The plurality of second-region light-emitting elements may include: a plurality of fourth light-emitting elements emitting first color light, a plurality of fifth light-emitting elements emitting second color light, and a plurality of sixth light-emitting elements emitting third color light. The display substrate may further include: a plurality of first data lines, the first data lines may be configured to provide data signals to a column of second-region light-emitting elements separated by the first display area, the column of second-region light-emitting elements including: a plurality of second-region light-emitting elements arranged along a first direction. Wherein, the first data line providing data signals to the fifth light-emitting element and the sixth light-emitting element is configured to be connected to the second data connection line. The first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the third data connection line; or, the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the third data connection line. The first light-emitting elements in the even-numbered columns and the odd-numbered columns can be determined according to the order of the first light-emitting elements in the multiple columns in the first display area along the second direction, and the second direction intersects with the first direction, for example, the second direction can be perpendicular to the first direction. The even-numbered columns and the odd-numbered columns are determined only according to the order of the first light-emitting elements in the multiple columns, and do not include the second light-emitting elements and the third light-emitting elements in the multiple columns. The winding of the first data line in this example follows the following rules: the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is wound first, the first data line connected to the fifth light-emitting element and the sixth light-emitting element is wound in sequence, and the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is wound last; or, the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is wound first, the first data line connected to the fifth light-emitting element and the sixth light-emitting element is wound in sequence, and the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is wound last. The winding method of the first data line in this example can match the one-drive-two design adopted by the first light-emitting element in the first display area, and can reduce the load of the routing that transmits data signals to the first light-emitting element and the fourth light-emitting element.

[0059] In some exemplary embodiments, the first data line may include: a first routing segment and a second routing segment located on both sides of the first display area along the first direction. The display substrate may also include: a plurality of first windings and a plurality of second windings, the first winding may be connected between the first routing segment of the first data line and a data connection line, and the second winding may be connected between the second routing segment of the first data line and the data connection line. The substrate may also include: a frame area located outside the first display area and the second display area. Among them, the plurality of first windings may be located in the frame area, and the plurality of second windings may be located in the second display area. In some examples, the plurality of first windings may be alternately arranged in two different conductive layers. This example can save the routing space in the frame area and reduce the occupation of the frame area by alternately wiring the plurality of first windings in different conductive layers.

[0060] The solution of this embodiment is described below by means of some examples.

[0061] Figure 1 Schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, the display substrate may include: a display area AA, and a border area BB surrounding the periphery of the display area AA. For example, the border area BB may include: a first border area B1 located on one side of the display area AA, and border areas located on the other side of the display area AA (for example, may include a second border area B2, a third border area B3, and a fourth border area B4). Among them, the first border area B1 may be an upper border of the display substrate, the second border area B2 may be a lower border of the display substrate, the third border area B3 may be a left border of the display substrate, and the fourth border area B4 may be a right border of the display substrate.

[0062] In some examples, the display area AA may include: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the first display area A1 may be located in the top center of the display area AA, and the second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located in other positions such as the upper left corner or the upper right corner of the display area AA, and the second display area A2 may surround at least one side of the first display area A1.

[0063] In some examples, such as Figure 1 As shown, the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be a circle or an ellipse. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon or other shapes.

[0064] In some examples, such as Figure 1As shown, the first display area A1 can be a light-transmitting display area, which can also be called a Full Display with Camera (FDC) area, configured to display images and transmit light; the second display area A2 can be a normal display area, configured to display images. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate can be located in the first display area A1 of the display substrate. In some examples, such as Figure 1 As shown, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0065] In some examples, such as Figure 1 As shown, the pixel density of the first display area A1 may be less than or equal to the pixel density of the second display area A2. For example, the pixel density of the first display area A1 may be equal to the pixel density of the second display area A2. This embodiment is not limited to this.

[0066] In some examples, the ratio of the resolution of the first display area A1 to the resolution of the second display area A2 may be approximately 0.8 to 1.2. Alternatively, the resolution of the second display area A2 may be substantially the same as the resolution of the first display area A1. This embodiment is not limited thereto.

[0067] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 2 As shown, each pixel unit of the display area may include: two first sub-pixels P11 and P12 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light. Multiple pixel units may be arranged in an array in the display area AA. The pixel circuits of multiple sub-pixels in the second display area may be arranged in an array along the first direction Y and the second direction X. In a single pixel unit, the light-emitting elements of four sub-pixels may be arranged in different columns along the second direction X, and the light-emitting elements of four sub-pixels may be arranged in the same row; the pixel circuits of four sub-pixels may be arranged in sequence along the second direction X. For example, the second sub-pixel P2, the first sub-pixel P11, the third sub-pixel P3, and the first sub-pixel P12 may be arranged in sequence along the second direction X, or the third sub-pixel P3, the first sub-pixel P12, the second sub-pixel P2, and the first sub-pixel P11 may be arranged in sequence along the second direction X.

[0068] In some examples, the first color light may be green light, the second color light may be red light, and the third color light may be blue light. The second sub-pixel P2 may be a red sub-pixel (R), the third sub-pixel P3 may be a blue sub-pixel (B), and the first sub-pixels P11 and P12 may be green sub-pixels (G). For example, the first sub-pixel P11 may be a first green sub-pixel (G1), and the first sub-pixel P12 may be a second green sub-pixel (G2).

[0069] In some examples, such as Figure 2 As shown, a plurality of pixel units arranged along the second direction X (also referred to as the row direction) may be a row of pixel units, and a plurality of pixel units arranged along the first direction Y (also referred to as the column direction) may be a column of pixel units. The plurality of pixel units may include a plurality of first pixel units Pa and a plurality of second pixel units Pb, and the arrangement order of the four sub-pixels in the first pixel unit Pa and the second pixel unit Pb may be different. For example, the e-th row of pixel units may include: a plurality of first pixel units Pa arranged in sequence along the second direction X; the second sub-pixel P2, the first sub-pixel P11, the third sub-pixel P3 and the first sub-pixel P12 of the first pixel unit Pa are arranged in sequence along the second direction X. The e+1-th row of pixel units may include: a plurality of second pixel units Pb arranged in sequence along the second direction X, and the third sub-pixel P3, the first sub-pixel P12, the second sub-pixel P2 and the first sub-pixel P11 of the second pixel unit Pb may be arranged in sequence along the second direction X. A column of pixel units may include: the first pixel units Pa and the second pixel units Pb alternately arranged along the first direction Y. Wherein, e may be an integer greater than 0. For example, the sub-pixels of odd-numbered pixel rows in the display area may be arranged in RG1BG2, and the sub-pixels of even-numbered pixel rows may be arranged in BG2RG1; or, the sub-pixels of odd-numbered pixel rows in the display area may be arranged in BG2RG1, and the sub-pixels of even-numbered pixel rows may be arranged in RG1BG2.

[0070] In some examples, a plurality of sub-pixels arranged along the first direction Y may be a column of sub-pixels. The jth column of sub-pixels may include: second sub-pixels P2 and third sub-pixels P3 alternately arranged along the first direction Y; the j+1th column of sub-pixels may include: first sub-pixels P11 and P12 alternately arranged along the first direction Y. j may be an integer greater than 1. The pixel circuits of each column of sub-pixels may be connected to the same data line. For example, the jth column of sub-pixels may be connected to the data line DLj, and the j+1th column of sub-pixels may be connected to the data line DLj+1. The data line DLj may provide data signals to the second sub-pixel P2 and the third sub-pixel P3 in a time-sharing manner, and the data line DLj+1 may provide data signals to the first sub-pixels P11 and P12 in a time-sharing manner. For example, the data signals required for the first sub-pixels P11 and P12 may be the same.

[0071] In some examples, each sub-pixel may include a circuit unit and a light-emitting element, the circuit unit may include at least a pixel circuit, the pixel circuit is respectively connected to a scan line, a data line, and a light-emitting control line, and the pixel circuit may be configured to receive a data voltage transmitted by the data line under the control of the scan line and the light-emitting control line, and output a corresponding current to the light-emitting element. The light-emitting elements in at least one sub-pixel are respectively connected to the pixel circuit of the sub-pixel, and the light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0072] In some examples, the pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0073] In some examples, the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0074] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, namely an LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0075] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0076] In some examples, the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. The light-emitting elements of the four sub-pixels of a pixel unit may be arranged in horizontal parallel, vertical parallel, or in a square manner. However, this embodiment is not limited to this. In other examples, a pixel unit may include three sub-pixels, and the light-emitting elements of the three sub-pixels may be arranged in horizontal parallel, vertical parallel, or in a herringbone manner.

[0077] Figure 3 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described by taking a 7T1C structure as an example. In some examples, such as Figure 3 As shown, the pixel circuit of this example may include six switch transistors (T1, T2, T4 to T7), a drive transistor T3 and a storage capacitor Cst. The six switch transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light emitting element EL may include an anode, a cathode and an organic light emitting layer disposed between the anode and the cathode.

[0078] In some examples, such as Figure 3As shown, the display substrate may include: a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel driving circuit, the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel driving circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL may be configured to provide a scan signal SCAN to the pixel driving circuit, the data line DL may be configured to provide a data signal DATA to the pixel driving circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel driving circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel driving circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel driving circuit. In some examples, in the n-th row pixel driving circuit, the first reset control line RST1 can be electrically connected to the scan line GL of the n-1-th row pixel driving circuit to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected to the scan line GL of the n-th row pixel driving circuit to be input with the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In some examples, the second reset control line RST2 electrically connected to the n-th row pixel driving circuit and the first reset control line RST1 electrically connected to the n+1-th row pixel driving circuit can be an integrated structure. Wherein, n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and the narrow frame design of the display substrate can be realized. However, this embodiment is not limited to this.

[0079] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel driving circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel driving circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.

[0080] In some examples, such as Figure 3As shown, the driving transistor T3 is electrically connected to the light emitting element EL, and outputs a driving current under the control of the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals to drive the light emitting element EL to emit light. The gate of the data writing transistor T4 is electrically connected to the scanning line GL, the first electrode of the data writing transistor T4 is electrically connected to the data line DL, and the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scanning line GL, the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3. The gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is electrically connected to the first power line PL1, and the second electrode of the first light emission control transistor T5 is electrically connected to the first electrode of the driving transistor T3. The gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second light emission control transistor T6 is electrically connected to the anode of the light emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light emitting element EL and is configured to reset the anode of the light emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the anode of the light emitting element EL. A first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3 , and a second capacitor plate of the storage capacitor Cst is electrically connected to the first power line PL1 .

[0081] In this example, the first node N1 is a connection point between the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N2 is a connection point between the first light emission control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 is a connection point between the driving transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is a connection point between the second light emission control transistor T6, the second reset transistor T7 and the light emitting element EL. The fourth node N4 is an anode connection node.

[0082] Below Figure 3 The working process of the pixel circuit is described as follows. Figure 3 The pixel circuit shown in the figure includes a plurality of transistors which are all P-type transistors. In some examples, in a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage and a third stage.

[0083] The first stage is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, which initializes the first node N1 and clears the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, which turns off the data writing transistor T4, the threshold compensation transistor T2, the first light control transistor T5, the second light control transistor T6 and the second reset transistor T7. In this stage, the light emitting element EL does not emit light.

[0084] The second stage is called the data writing stage or the threshold compensation stage. The scanning signal SCAN provided by the scanning line GL is a low level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the light control signal EM provided by the light control line EML are both high level signals, and the data line DL outputs the data signal DATA. In this stage, since the first capacitor plate of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on. The scanning signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, and the voltage of the first capacitor plate (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, the anode of the light-emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and it is ensured that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, which turns off the first reset transistor T1. The light emitting control signal EM provided by the light emitting control signal line EML is a high level signal, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off.

[0085] The third stage is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, and the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, and the first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor T5, the driving transistor T3 and the second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0086] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0087] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0088] Among them, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0089] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the driving transistor T3.

[0090] In some examples, such as Figure 1 As shown, the display substrate may include at least: a plurality of first-region light-emitting elements 31 located in the first display area A1, a plurality of second-region light-emitting elements 32 located in the second display area A2, a plurality of first-type pixel circuits 41 and a plurality of second-type pixel circuits 42.

[0091] In some examples, at least one second-type pixel circuit 42 may be connected to at least one second-region light-emitting element 32, and configured to drive the at least one second-region light-emitting element 32 to emit light. For example, a plurality of second-region light-emitting elements 32 and a plurality of second-type pixel circuits 42 may be in a one-to-one relationship, that is, one second-type pixel circuit 42 may be electrically connected to one second-region light-emitting element 32, and configured to drive the connected one second-region light-emitting element 32 to emit light; or, a plurality of second-type pixel circuits 42 and a plurality of second-region light-emitting elements 32 may be in a one-to-many relationship, that is, one second-type pixel circuit 42 may be electrically connected to a plurality of second-region light-emitting elements 32, and configured to drive the connected plurality of second-region light-emitting elements 32 to emit light; or, a plurality of second-type pixel circuits 42 and a plurality of second-region light-emitting elements 32 may be in a many-to-one relationship, that is, a plurality of second-type pixel circuits 42 may be electrically connected to one second-region light-emitting element 32, and configured to drive the second-region light-emitting element 32 to emit light.

[0092] In some examples, at least one first-type pixel circuit 41 can be connected to at least one first-region light-emitting element 31 through a connecting line 51, and is configured to drive the at least one first-region light-emitting element 31 to emit light. In some examples, a portion of the first-type pixel circuits in the plurality of first-type pixel circuits 41 and the plurality of first-region light-emitting elements 31 can be in a one-to-many relationship, and another portion of the first-type pixel circuits and the plurality of first-region light-emitting elements 31 can be in a one-to-one relationship. For example, a first-type pixel circuit 41 can be electrically connected to a plurality of first-region light-emitting elements 31 emitting light of the same color, and is configured to drive the plurality of first-region light-emitting elements emitting light of the same color to emit light. Since the first-region light-emitting element 31 and the first-type pixel circuit 41 are located in different regions, there may be no overlapping portion between the orthographic projection of at least one first-region light-emitting element 31 on the substrate and the orthographic projection of at least one first-region light-emitting element 31 on the substrate. By arranging the first-type pixel circuit 41 in the second display area A2, it is beneficial to improve the light transmittance of the first display area A1. In some examples, the connection line 51 may be made of a transparent conductive material (eg, indium tin oxide (ITO)) to maximize the light transmittance of the first display area A1.

[0093] In some examples, since the second display area A2 is not only provided with a first type pixel circuit 41 electrically connected to the first area light-emitting element 31, but also provided with a second type pixel circuit 42 electrically connected to the second area light-emitting element 32, the number of pixel circuits in the second display area A2 is greater than the number of second area light-emitting elements 32. In some examples, the area for setting the newly added pixel circuit (including the first type pixel circuit) can be obtained by reducing the size of the second type pixel circuit 42 in the second direction X. For example, the size of the pixel circuit in the second direction X can be smaller than the size of the second area light-emitting element 32 in the second direction X. In some examples, the original h-column pixel circuit can be compressed along the second direction X to add a new column of pixel circuit arrangement space, and the space occupied by the h-column pixel circuit before compression and the h+1-column pixel circuit after compression can be the same. Wherein, h can be an integer greater than 1. In this example, h can be equal to 2 or 4. However, this embodiment is not limited to this.

[0094] In some examples, the first type pixel circuit 41 may be disposed in the second display area A2 on both sides (e.g., left and right sides) of the first display area A1 along the second direction X, and the first type pixel circuit may not be disposed in the second display area A2 on both sides (e.g., upper and lower sides) of the first display area A1 along the first direction Y. This embodiment is not limited to this.

[0095] Figure 4 A partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 4 The structure of a sub-pixel in the second display area is used as an example for illustration. In this example, the same type of multiple transistors in the pixel circuit is used as an example for illustration. For example, multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In other examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors.

[0096] In some examples, such as Figure 4 As shown, in a direction perpendicular to the display substrate, the second display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 11, a conductive connection layer 12, a light emitting structure layer 13 and a packaging structure layer 14 sequentially arranged on the substrate 10. The circuit structure layer 11 may include at least: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits, each pixel circuit may include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 may include at least: a plurality of second-region light emitting elements.

[0097] In some examples, Figure 4In the figure, a thin film transistor 21 and a capacitor 22 included in each pixel unit are used as an example for illustration. In some examples, the circuit structure layer 11 of the second display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate 10. A first gate insulating layer 101 may be arranged between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be arranged between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be arranged between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first flat layer 105 may be arranged between the first source-drain metal layer and the second source-drain metal layer, a second flat layer 106 may be arranged between the second source-drain metal layer and the third source-drain metal layer, and a third flat layer 107 may be arranged on the side of the third source-drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103 and the passivation layer 104 can be inorganic insulating layers, and the first flat layer 105, the second flat layer 106 and the third flat layer 107 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can also be provided on the side of the semiconductor layer close to the substrate, and the buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate, and can also increase the adhesion of the film layer in the display substrate on the substrate. In other examples, a bottom shading metal layer (BSM, Bottom Shielding Metal) can be provided on the side of the buffer layer close to the substrate, and the bottom shading metal layer can be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to avoid external light from affecting the performance of the thin film transistor. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first flat layer can be provided between the first source and drain metal layer and the second source and drain metal layer. In some other examples, the circuit structure layer may omit the third source-drain metal layer, or the circuit structure layer may further include a fourth source-drain metal layer located on a side of the third source-drain metal layer away from the substrate.

[0098] In some examples, such as Figure 4 As shown, the conductive connection layer 12 may include a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer sequentially arranged along the direction of the substrate 10. A fourth flat layer 108 may be arranged between the first conductive connection layer and the second conductive connection layer, a fifth flat layer 109 may be arranged between the second conductive connection layer and the third conductive connection layer, and a sixth flat layer 110 may be arranged on the side of the third conductive connection layer away from the substrate 10. The fourth flat layer 108, the fifth flat layer 109, and the sixth flat layer 110 may be organic insulating layers. In some examples, the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer may be made of transparent conductive materials, such as ITO.

[0099] In some examples, such as Figure 4As shown, the semiconductor layer of the second display area may include at least: an active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first area 2101, a second area 2102, and a channel area 2100 located between the first area 2101 and the second area 2102. The first gate metal layer may include at least: a gate electrode 213 of the thin film transistor 21, and a first electrode plate 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel area 2100 of the active layer 210 on the substrate 10. The second gate metal layer may include at least: a second electrode plate 222 of the capacitor 22. The orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may overlap. The first source-drain metal layer may include at least: a source electrode 211 and a drain electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least: a first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain electrode 212 of the thin film transistor 21 of the pixel circuit through the third pixel via hole opened in the passivation layer 104 and the first flat layer 105. The third source-drain metal layer can at least include: a second transfer electrode 232, and the second transfer electrode 232 can be connected to the first transfer electrode 231 through a fourth pixel via hole opened in the second flat layer 106. The first conductive connection layer can at least include: a third transfer electrode 233, and the third transfer electrode 233 can be connected to the second transfer electrode 232 through a fifth pixel via hole opened in the third flat layer 107. The second conductive connection layer can at least include: a fourth transfer electrode 234, and the fourth transfer electrode 234 can be connected to the third transfer electrode 233 through a sixth pixel via hole opened in the fourth flat layer 108. The third conductive connection layer can at least include: a fifth transfer electrode 235, and the fifth transfer electrode 235 can be connected to the fourth transfer electrode 234 through a seventh pixel via hole opened in the fifth flat layer 109. In this example, the second source-drain metal layer, the third source-drain metal layer and the three conductive connection layers can realize the electrical connection between the pixel circuit and the light-emitting element. However, this embodiment is not limited to this. In other examples, the number of the conductive connection layers can be two or more.

[0100] In some examples, such as Figure 4 As shown, the light emitting structure layer 13 of the display area may include: a pixel definition layer 304 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 301, an organic light emitting layer 302 and a second electrode 303. The first electrode 301 of the light emitting element may be an anode. For example, the first electrode 301 of the light emitting element in the second area may be disposed on the fifth flat layer 110, and electrically connected to the fifth transfer electrode 235 through the eighth pixel via hole opened in the fifth flat layer 110. The pixel definition layer 304 is disposed on the first electrode 301 and the fifth flat layer 110, and the pixel definition layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 301. At least part of the organic light emitting layer 302 may be disposed in a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light emitting layer 302 and connected to the organic light emitting layer 302. The organic light emitting layer 302 may emit light of corresponding colors under the drive of the first electrode 301 and the second electrode 303. An isolation column layer may be further disposed on a side of the pixel definition layer 304 away from the substrate 10 , and the isolation column layer may include a plurality of isolation columns (PS).

[0101] In some examples, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0102] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, FineMetal Mask) or an open mask (Open Mask), or by inkjet technology.

[0103] In some examples, such as Figure 4 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked. Among them, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 may be arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0104] Figure 5 The present invention is a schematic diagram of the connection between the first-region light-emitting element and the first-type pixel circuit according to at least one embodiment of the present disclosure. Figure 6 It is a schematic diagram of the partial structure of the first display area of ​​at least one embodiment of the present disclosure. Figure 5 The connection method between the first area light-emitting element in the first display area A1 and the first type pixel circuit in the second display area A2 on the left is taken as an example for explanation. The connection method between the first area light-emitting element in the first display area and the first type pixel circuit in the second display area on the right is similar, so it will not be repeated here.

[0105] In some examples, such as Figure 1 and Figure 5As shown, the plurality of first-region light-emitting elements 31 located in the first display area A1 may include: a plurality of first light-emitting elements 311a and 311b emitting first color light (e.g., green light), a plurality of second light-emitting elements 312 emitting second color light (e.g., red light), and a plurality of third light-emitting elements 313 emitting third color light (e.g., blue light). The first display area A1 may be provided with a plurality of first-region display units arranged in an array, and each first-region display unit may include: two first light-emitting elements 311a and 311b, one second light-emitting element 312, and one third light-emitting element 313. Along the second direction X, one of the first light-emitting elements in the first-region display unit may be arranged in the second light-emitting element 312 and the third light-emitting element 313. For example, the second light-emitting element 312, the first light-emitting element 311a, the third light-emitting element 313 and the first light-emitting element 311b of the odd-numbered rows of the first area display units can be arranged in sequence along the second direction X, and the third light-emitting element 313, the first light-emitting element 311b, the second light-emitting element 312 and the first light-emitting element 311a of the even-numbered rows of the first area display units can be arranged in sequence along the second direction X.

[0106] In some examples, the plurality of first-type pixel circuits located in the second display area A2 may include: a plurality of first pixel circuits 411, a plurality of second pixel circuits 412, and a plurality of third pixel circuits 413. The plurality of first-type pixel circuits may be arranged between the plurality of second-type pixel circuits 42. For example, along the second direction X, one first-type pixel circuit is inserted into every four second-type pixel circuits 42. The plurality of first pixel circuits 411 may be located on one side of the plurality of second pixel circuits 412 and the plurality of third pixel circuits 413 close to the first display area A1.

[0107] In some examples, the second display area A2 may include: a transition area A20, a first sub-area A21, a second sub-area A22, a third sub-area A23, and a fourth sub-area A24, which are sequentially arranged in the second direction X along a direction away from the first display area A1. The transition area A20 may be provided with a plurality of second invalid pixel circuits 415, and the fourth sub-area A24 may be provided with a plurality of first invalid pixel circuits 414. The insertion rule of the first invalid pixel circuit 414 and the second invalid pixel circuit 415 in the plurality of second type pixel circuits 42 may be the same as the insertion rule of the first type pixel circuit. For example, along the second direction X, one first invalid pixel circuit 414 or one second invalid pixel circuit 415 may be inserted into every four second type pixel circuits 42. For example, three columns of second invalid pixel circuits 415 may be provided in the transition area A20.

[0108] In some examples, the first sub-region A21 may be provided with a plurality of first pixel circuits 411 and a plurality of second type pixel circuits 42. Each first pixel circuit 411 may be connected to two first light-emitting elements 311a and 311b via a first connecting line 511, and configured to drive the two connected first light-emitting elements 311a and 311b to emit light. The two first light-emitting elements 311a and 311b connected to the first pixel circuit 411 may belong to the same first area display unit. In other examples, the two first light-emitting elements connected to the first pixel circuit 411 may belong to two adjacent first area display units, and the two first light-emitting elements are separated by a second light-emitting element or a third light-emitting element.

[0109] In some examples, the multiple first connection lines 511 connected to the multiple first pixel circuits 411 may be located in the same conductive layer, for example, may all be located in the first conductive connection layer, so as to reduce the load of the first connection lines 511 and improve the display effect of the first light-emitting element.

[0110] In some examples, the second sub-area A22 and the third sub-area A23 may be provided with a plurality of second pixel circuits 412, a plurality of third pixel circuits 413, and a plurality of second-type pixel circuits 42. Each second pixel circuit 412 may be connected to a second light-emitting element 312 via a second connection line 512, and configured to drive the connected second light-emitting element 412. Each third pixel circuit 413 may be connected to a third light-emitting element 313 via a third connection line 513, and configured to drive the connected third light-emitting element 413. In some examples, due to differences in the arrangement order of the first-area light-emitting elements in the first-area display units of adjacent rows, the plurality of second pixel circuits 412 and the plurality of third pixel circuits 413 in the second display area may be arranged alternately along the first direction Y. For example, a column of first-type pixel circuits in the second sub-area A22 and the third sub-area A23 may include second pixel circuits 412 and third pixel circuits 413 arranged alternately.

[0111] In some examples, the multiple second connection lines 512 connected to the multiple second pixel circuits 412 in the second sub-area A22 and the multiple third connection lines 513 connected to the multiple third pixel circuits 413 can be located in the same conductive layer, for example, in the second conductive connection layer; the multiple second connection lines 512 connected to the multiple second pixel circuits 412 in the third sub-area A23 and the multiple third connection lines 513 connected to the multiple third pixel circuits 413 can be located in the same conductive layer, for example, in the third conductive connection layer. However, this embodiment is not limited to this. In other examples, the multiple second connection lines connected to the multiple second pixel circuits in the second display area can be located in the same conductive layer, and the multiple third connection lines connected to the multiple third pixel circuits can be located in the same conductive layer, and the conductive layer where the multiple second connection lines are located is different from the conductive layer where the multiple third connection lines are located.

[0112] In some examples, such as Figure 5 and Figure 6 As shown, a plurality of first region light emitting elements arranged along the second direction X form a row of first region light emitting elements. A plurality of first connection lines 511 connected to a row of first region light emitting elements may be located on the same side of the row of first region light emitting elements in the first direction Y, such as the upper side.

[0113] In some examples, such as Figure 6 As shown, the first connection line 511 may include: a first connection segment 511-1, a second connection segment 511-2, a third connection segment 511-3, a fourth connection segment 511-4, a first connection block 511-5 and a second connection block 511-6. The first connection segment 511-1 and the third connection segment 511-3 may extend along the second direction X, and the second connection segment 511-2 and the fourth connection segment 511-4 may extend along the first direction Y. The first connection block 511-5 may be connected to the second connection segment 511-2, and the second connection block 511-6 may be connected to the fourth connection segment 511-4. The length of the first connection segment 511-1 may be greater than the length of the third connection segment 511-3, and the length of the second connection segment 511-2 may be greater than the length of the fourth connection segment 511-4. One end of the first connecting segment 511 - 1 is connected to the second connecting segment 511 - 2 , and two ends of the third connecting segment 511 - 3 are connected to the second connecting segment 511 - 2 and the fourth connecting segment 511 - 4 , respectively.

[0114] In some examples, the orthographic projections of the first connection block 511-5 and the second connection block 511-6 on the substrate may be approximately rectangular. The first connection block 511-5 may be connected to the anode 3111a of the first light-emitting element 311a, and the second connection block 511-6 may be connected to the anode 3111b of the first light-emitting element 311b. For example, the first connection line 511 may be located in the first conductive connection layer, and the first connection block 511-5 may be connected to the anode 3111a of the first light-emitting element 311a through a transition block located in the second conductive connection layer and the third conductive connection layer, and the second connection block 511-6 may be connected to the anode 3111b of the first light-emitting element 311b through a transition block located in the second conductive connection layer and the third conductive connection layer.

[0115] Compared with the scheme in which each first-region light-emitting element is connected to a first-type pixel circuit, this example sets a first pixel circuit to drive two first light-emitting elements, which can reduce the number of first connection lines between the first light-emitting element and the first pixel circuit by half. For example, the number of connection lines arranged in the three conductive connection layers can be the same, for example, the first conductive connection layer can be provided with twelve first connection lines, the second conductive connection layer can be provided with twelve second connection lines and third connection lines, and the third conductive connection layer can be provided with twelve second connection lines and third connection lines. Moreover, in this example, the first connection lines connected to the multiple first light-emitting elements emitting the first color light can be located in the same conductive connection layer, which can reduce the load difference of the multiple first light-emitting elements and is conducive to ensuring the display effect. In this example, the first pixel circuit that preferentially connects the first light-emitting element can make the length of the first connection line less than the length of the second connection line and the third connection line, which can be conducive to improving the display effect of the first light-emitting element.

[0116] In some examples, taking the second connecting wire located in the second conductive connection layer and the third connecting wire located in the third conductive connection layer as examples, the second connecting wire can be connected to the adapter block located in the first conductive connection layer, and can also be connected to the anode 3121 of the second light-emitting element 312 through the adapter block located in the third conductive connection layer; the third connecting wire can be connected to the adapter block located in the first conductive connection layer through the adapter block located in the second conductive connection layer, and can also be connected to the anode 3131 of the third light-emitting element 313.

[0117] Figure 7 A schematic diagram of a data line winding design according to at least one embodiment of the present disclosure. Figure 7 The wiring in the second display area A2 on the left side of the first display area A1 is taken as an example for description. The wiring in the second display area A2 on the right side of the first display area A1 is similar and will not be described in detail here. Figure 7 right Figure 1 The connection method between the data connection line 61 and the first data line 63 is specifically illustrated.

[0118] In some examples, such as Figure 1 and Figure 7 As shown, the display substrate may include: a plurality of data connection lines 61 located in the second display area A2 , and the plurality of data connection lines 61 may include: a plurality of first data connection lines 611 , a plurality of second data connection lines 612 , and a plurality of third data connection lines 613 . Figure 7 , a first data connection line 611, three second data connection lines 612, and a third data connection line 613 are used as examples for illustration. A plurality of first data connection lines 611, a plurality of second data connection lines 612, and a plurality of third data connection lines 613 may extend along the first direction Y. The first data connection line 611 may be connected to a plurality of first pixel circuits 411 arranged along the first direction Y, the second data connection line 612 may be connected to a plurality of second pixel circuits 412 and a plurality of third pixel circuits 413 arranged along the first direction Y, and the third data connection line 613 may be connected to a plurality of first invalid pixel circuits 414 arranged along the first direction Y. For example, the first pixel circuit 411 connected to the first data connection line 611 may be connected to two adjacent first light-emitting elements (e.g., green light-emitting elements) in the first display area A1 through the first connection line 511. The second pixel circuit 412 connected to the second data connection line 612 may be connected to a second light-emitting element (e.g., red light-emitting element) in the first display area A1 through the second connection line 512. The third pixel circuit 413 connected to the second data connection line 612 can be connected to the third light-emitting element (e.g., a blue light-emitting element) in the first display area A1 through the third connection line 513. The first pixel circuit 411 and the first light-emitting element connected thereto can be located in the same row, the second pixel circuit 412 and the second light-emitting element connected thereto can be located in the same row, and the third pixel circuit 413 and the third light-emitting element connected thereto can be located in the same row.

[0119] In some examples, such as Figure 7 As shown, the plurality of second data connection lines 612 may be located between the plurality of first data connection lines 611 and the plurality of third data connection lines 613. The plurality of first data connection lines 611, the plurality of second data connection lines 612, and the plurality of third data connection lines 613 may be arranged in a direction away from the first display area A1. In other words, the plurality of second data connection lines 612 are located on a side of the plurality of first data connection lines 611 away from the first display area A1, and the plurality of third data connection lines 613 are located on a side of the plurality of second data connection lines 612 away from the first display area A1.

[0120] In some examples, such as Figure 1 and Figure 7 As shown, the display substrate may further include: a plurality of first data lines 63 (eg, including Figure 7 The first data lines 63a, 63b and 63c shown in the figure), and a plurality of second data lines 65. The first data lines 63a, 63b and 63c can be configured to provide data signals to a column of second region light emitting elements separated by the first display area A1. The second data lines 65 can be configured to provide data signals to a column of second region light emitting elements not separated by the first display area A1.

[0121] In some examples, such as Figure 1 and Figure 7 As shown, the display substrate may further include: a plurality of invalid data lines 66 and a plurality of third invalid pixel circuits 43 located in the second display area A2. The plurality of third invalid pixel circuits 43 may be arranged between the plurality of second type pixel circuits 42, for example, a third invalid pixel circuit 43 may be arranged for every four second type pixel circuits 42. The plurality of third invalid pixel circuits 43 may be located on at least one side of the first display area A1 along the first direction Y. The invalid data line 66 may be connected to the plurality of third invalid pixel circuits 43 arranged along the first direction Y. An invalid data line 66 may be connected to a column of third invalid pixel circuits 43. A column of third invalid pixel circuits 43 connected to the invalid data line 66 may be connected to a column of first type pixel circuits 41 or a column of first invalid pixel circuits 414 or a column of second invalid pixel circuits 415 (in Figure 5 A data connection line 61 may be aligned with an invalid data line 66, and the two may not be connected. A plurality of (eg, four) second data lines 65 or first data lines 63 may be arranged between adjacent invalid data lines 66.

[0122] In some examples, the plurality of second region light emitting elements of the second display area A2 may include: a plurality of fourth light emitting elements emitting a first color light (e.g., green light), a plurality of fifth light emitting elements emitting a second color light (e.g., red light), and a plurality of sixth light emitting elements emitting a third color light (e.g., blue light). The arrangement of the fourth light emitting element, the fifth light emitting element, and the sixth light emitting element is similar to the arrangement of the first light emitting element, the second light emitting element, and the third light emitting element in the first display area A1, and therefore will not be described in detail herein.

[0123] In some examples, such as Figure 1 and Figure 7As shown, the plurality of first data lines 63 may include: a first data line 63b providing a data signal to a column of fifth and sixth light-emitting elements, and first data lines 63a and 63c providing a data signal to a column of fourth light-emitting elements. The fourth light-emitting element connected to the first data line 63a may be aligned with the first light-emitting element of the odd column in the first display area A1, and the fourth light-emitting element connected to the first data line 63c may be aligned with the first light-emitting element of the even column in the first display area A1. In other examples, the fourth light-emitting element connected to the first data line 63a may be aligned with the first light-emitting element of the even column in the first display area A1, and the fourth light-emitting element connected to the first data line 63c may be aligned with the first light-emitting element of the odd column in the first display area A1. In some examples, the plurality of first-region light-emitting elements in the first display area A1 may be arranged in a plurality of columns, wherein the plurality of second light-emitting elements and third light-emitting elements alternately arranged along the first direction Y may be arranged in the same column, and alternately arranged along the second direction X with the column where the first light-emitting element is located. By sorting the columns of first light emitting elements along the second direction X, it is possible to determine the columns of first light emitting elements with odd sorting numbers (i.e., odd-numbered columns of first light emitting elements) and the columns of first light emitting elements with even sorting numbers (i.e., even-numbered columns of first light emitting elements).

[0124] In some examples, Figure 7In the figure, two first-region display units located in different rows in the first display area A1 are used as an example for illustration. In other words, four columns of first-region light-emitting elements in the first display area A1 are used as an example. Along the second direction X, the first and third columns of first-region light-emitting elements include second light-emitting elements (e.g., red light-emitting elements) and third light-emitting elements (e.g., blue light-emitting elements) alternately arranged along the first direction Y, and the second and fourth columns of first-region light-emitting elements include a plurality of first light-emitting elements (e.g., green light-emitting elements) arranged along the first direction Y. The first data line 63b connected to the fifth and sixth light-emitting elements aligned with the first column of first-region light-emitting elements in the second display area A2 is configured to bypass the first display area A1 through the second data connection line 612 to achieve data signal transmission. The first data line 63a connected to the fourth light-emitting element aligned with the second column of first-region light-emitting elements in the second display area A2 is configured to bypass the first display area A1 through the first data connection line 611 to achieve data signal transmission. The first data line 63c connected to the fourth light-emitting element aligned with the first-region light-emitting element of the fourth column in the second display area A2 is configured to bypass the first display area A1 through the first data connection line 613 to achieve data signal transmission. In this example, the first data line connected to the fourth light-emitting element aligned with the first light-emitting element of a column is wound through the first data connection line, and the first data line connected to the fourth light-emitting element aligned with the first light-emitting element of the adjacent column of the first light-emitting element of the column is wound through the third data connection line. In other words, the first light-emitting elements in the first display area A1 are sorted alone, the first-region light-emitting element of the second column is the first light-emitting element of the first column, the first-region light-emitting element of the fourth column is the first light-emitting element of the second column, the first data line connected to the fourth light-emitting element aligned with the first light-emitting element of the odd column can be wound through the first data connection line, and the first data line connected to the fourth light-emitting element aligned with the first light-emitting element of the even column can be wound through the third data connection line. In other examples, the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the even column can be routed through the first data connection line, and the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the odd column can be routed through the third data connection line.

[0125] In some examples, since the first light-emitting elements located in adjacent odd columns and even columns in the same row of the first display area A1 are connected to the same first pixel circuit, for example, two first light-emitting elements located in the same row and in the first column and the second column are connected to the same first pixel circuit 411, therefore, of the two data signals corresponding to the fourth light-emitting elements in two adjacent columns blocked by the first display area A1 in the second display area A2, only one of the data signals is provided to the first pixel circuit 411 to drive the corresponding first light-emitting elements, and the other data signal can be provided to the plurality of fourth light-emitting elements blocked by the first display area A1 through the third data connection line 613 connected to the first invalid pixel circuit 414. For example, the first data line connected to a column of fourth light-emitting elements corresponding to the first column of first light-emitting elements can be connected to the first data connection line, and the first data line connected to a column of fourth light-emitting elements corresponding to the second column of first light-emitting elements can be connected to the third data connection line. However, this embodiment is not limited to this. For example, the first data line connected to a column of fourth light emitting elements corresponding to the second column of first light emitting elements can be connected to the first data connection line, and the first data line connected to a column of fourth light emitting elements corresponding to the first column of first light emitting elements can be connected to the third data connection line.

[0126] In some examples, such as Figure 1 As shown, a first data line 63 may include: a first routing segment 631 and a second routing segment 632 located at both sides of the first display area A1 along the first direction Y and extending along the first direction Y. Figure 7 As shown, the first data line 63a may include a first routing segment 631a and a second routing segment 632a, the first data line 63b may include a first routing segment 631b and a second routing segment 632b, and the first data line 63c may include a first routing segment 631c and a second routing segment 632c.

[0127] In some examples, such as Figure 1 As shown, the display substrate may further include: a plurality of first windings 641 extending along the second direction X and a plurality of second windings 642 extending along the second direction X. The first winding 641 may be connected between a first routing segment 631 of a first data line 63 and a data connection line 61, and the second winding 642 may be connected between the data connection line 61 and the second routing segment 632 of the first data line 63. For example, a plurality of first windings 641 may be located in the first frame area B1, and a plurality of second windings 642 may be located in the second display area A2. A plurality of data connection lines 61 may extend from the second display area A2 to the first frame area B1, and be connected to a plurality of first windings 641 in the first frame area B1. However, this embodiment is not limited to this. In other examples, a plurality of first windings may be located in the second display area, or may be partially located in the second display area.

[0128] In some examples, such as Figure 7 As shown, the first winding wire 641 connected to the first data line 63a may be located on a side of the first winding wire 641 connected to the first data line 63b close to the first display area A1, and the first winding wire 641 connected to the first data line 63b may be located on a side of the first winding wire 641 connected to the first data line 63c close to the first display area A1. The second winding wire 642 connected to the first data line 63a may be located on a side of the second winding wire 642 connected to the first data line 63b close to the first display area A1, and the second winding wire 642 connected to the first data line 63b may be located on a side of the second winding wire 642 connected to the first data line 63c close to the first display area A1.

[0129] In some examples, such as Figure 1 and Figure 7 As shown, the winding of the first data line 63 follows the following rules: the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is wound first, the first data line connected to the fifth light-emitting element and the sixth light-emitting element is wound in sequence, and the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is wound last; or, the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is wound first, the first data line connected to the fifth light-emitting element and the sixth light-emitting element is wound in sequence, and the first data line connected to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is wound last. In this example, the odd and even columns of the first light-emitting elements are determined only by the order of the first light-emitting elements along the second direction. The winding method of the first data line in this example can match the one-drive-two design adopted by the first light-emitting element in the first display area, and can reduce the load of the routing for transmitting data signals to the first light-emitting element and the fourth light-emitting element.

[0130] Figure 8 It is a schematic diagram of the partial structure of the first border area of ​​at least one embodiment of the present disclosure. Fig. 9 for Figure 8 A partial enlarged schematic diagram of the middle area S1. Figure 8 Schematic diagram of the connection between the first routing segments of the plurality of first data lines and the plurality of first windings is shown in FIG. The connection between the plurality of first windings and the plurality of data connection lines is similar and will not be described in detail herein.

[0131] In some examples, such as Figure 8 and Fig. 9As shown, the plurality of first windings 641 located in the first frame area may include: a plurality of first-type first windings 641a and a plurality of second-type first windings 641b. The plurality of first-type first windings 641a and the plurality of second-type first windings 641b are alternately arranged along the first direction Y and arranged in two different conductive layers. The plurality of first-type first windings 641a may be located on the side of the plurality of second-type first windings 641b away from the substrate. For example, the plurality of first-type first windings 641a may be located in the second source-drain metal layer, and the plurality of second-type first windings 641b may be located in the first source-drain metal layer. However, this embodiment is not limited to this. In other examples, the plurality of first-type first windings may be located in the source-drain metal layer, and the plurality of second-type first windings may be located in the gate metal layer; or, the plurality of first-type first windings and the plurality of second-type first windings may be located in different gate metal layers.

[0132] In some examples, a plurality of first-type first windings 641a may be connected to a plurality of first data connection lines 611 and a first routing segment 631a of a plurality of first data lines 63a, and may also be connected to a plurality of third data connection lines 613 and a first routing segment 631c of a plurality of first data lines 63c, and a plurality of second-type first windings 641b may be connected to a plurality of second data connection lines 612 and a first routing segment 631b of a plurality of first data lines 63b. In this example, the routing for transmitting data signals to the light-emitting elements (including the first light-emitting element and the fourth light-emitting element) emitting the first color light and the routing for transmitting data signals to the light-emitting elements (including the second light-emitting element, the third light-emitting element, the fifth light-emitting element and the sixth light-emitting element) emitting the second color light and the third color light are arranged in different conductive layers, which may be beneficial to the routing load for transmitting data signals to the first light-emitting element and the fourth light-emitting element.

[0133] In some examples, the first routing segments of the plurality of data connection lines and the plurality of first data lines may extend to the first border region and may be located on the side of the plurality of first windings away from the substrate. For example, the first routing segments of the plurality of data connection lines and the plurality of first data lines may be located in the third source-drain metal layer. The first routing segment 631a of the first data line 63a (or the first routing segment 631c of the first data line 63c) located in the third source-drain metal layer may be directly connected to the first type first winding 641a located in the second source-drain metal layer through a transfer hole opened in the organic insulating layer (e.g., the fourth planar layer 109). Fig. 9As shown, the first routing segment 631b of the first data line 63b located in the third source-drain metal layer can be connected to the second type first winding 641b located in the first source-drain metal layer through the first switching electrode 651. The first switching electrode 651 can be located in the second source-drain metal layer. The first routing segment 631b of the first data line 63b can be connected to the first switching electrode 651 through a switching hole opened in the organic insulating layer (for example, the fourth flat layer 109), and the first switching electrode 651 can be connected to the second type first winding 641b through a switching hole opened in the organic insulating layer (for example, the third flat layer 108).

[0134] In some examples, such as Fig. 9 As shown, the first type first winding 641a adjacent to the first switching electrode 651 may have a straight portion 641-1 and a folded line portion 641-2 extending along the second direction X. The folded line portion 641-2 may be located between two adjacent straight line portions 641-1 and connected to the two straight line portions 641-1, and the folded line portion 641-2 may bypass the first switching electrode 651 from one side of the first direction Y. In this example, by providing a folded line portion on the first type first winding adjacent to the first switching electrode 651 to bypass the first switching electrode, it may be beneficial to reduce the spacing between adjacent wirings, and to reduce the space occupied by multiple first windings in the frame area.

[0135] In this example, by alternately arranging multiple first windings in different conductive layers, the space occupied by the wiring can be effectively saved, and the space occupied by the frame area can be reduced. Moreover, by setting a folded line portion for the first type of first winding to bypass the first transfer electrode, the spacing between adjacent wirings can be further reduced, greatly reducing the frame occupation.

[0136] This embodiment also provides a display substrate, including: a substrate, a plurality of first-region light-emitting elements, a plurality of first-type pixel circuits, a plurality of first invalid pixel circuits, a plurality of second-region light-emitting elements, a plurality of second-type pixel circuits, a plurality of data connection lines, and a plurality of first data lines. The substrate includes: a first display area and a second display area located at least on one side of the first display area. The plurality of first-region light-emitting elements are located in the first display area, including: a plurality of first light-emitting elements emitting first color light, a plurality of second light-emitting elements emitting second color light, and a plurality of third light-emitting elements emitting third color light. The plurality of first-type pixel circuits are located in the second display area, including: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits, the first pixel circuit is connected to at least two first light-emitting elements through a first connection line, the second pixel circuit is connected to at least one second light-emitting element through a second connection line, and the third pixel circuit is connected to at least one third light-emitting element through a third connection line. The plurality of first invalid pixel circuits are located in the second display area, and are located on the side of the plurality of first-type pixel circuits away from the first display area. A plurality of second-region light-emitting elements and a plurality of second-type pixel circuits are located in the second display area, the plurality of second-region light-emitting elements and the plurality of second-type pixel circuits are electrically connected one by one, the plurality of second-region light-emitting elements include: a plurality of fourth light-emitting elements emitting first color light, a plurality of fifth light-emitting elements emitting second color light, and a plurality of sixth light-emitting elements emitting third color light. A plurality of data connection lines are located in the second display area, including: a plurality of first data connection lines, a plurality of second data connection lines, and a plurality of third data connection lines, the first data connection lines are connected to a plurality of first pixel circuits arranged along a first direction, the second data connection lines are connected to a plurality of second pixel circuits and a plurality of third pixel circuits arranged along the first direction, the third data connection lines are connected to a plurality of first invalid pixel circuits arranged along the first direction; the plurality of second data connection lines are located on a side of the plurality of first data connection lines away from the first display area, and the plurality of third data connection lines are located on a side of the plurality of second data connection lines away from the first display area. The first data line is configured to provide a data signal to a column of second-region light-emitting elements separated by the first display area, and the column of second-region light-emitting elements includes: a plurality of second-region light-emitting elements arranged along the first direction.Wherein, the first data line providing data signals to the fifth light-emitting element and the sixth light-emitting element is configured to be connected to the second data connection line; the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the third data connection line; or, the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the third data connection line. The first light-emitting elements in the even-numbered columns and the first light-emitting elements in the odd-numbered columns are determined according to the order of the first light-emitting elements in the first display area along the second direction, and the second direction intersects with the first direction.

[0137] The winding method of the first data line provided in this embodiment can match the connection design between the first light-emitting element and the first pixel circuit in the first display area, and can reduce the load of the routing line transmitting data signals to the first light-emitting element and the fourth light-emitting element.

[0138] In some exemplary embodiments, the first data line includes: a first routing segment and a second routing segment located on both sides of the first display area along the first direction. The display substrate further includes: a plurality of first windings and a plurality of second windings, the first windings being connected between the first routing segment of the first data line and a data connection line, and the second windings being connected between the second routing segment of the first data line and the data connection line. The substrate further includes: a frame area located outside the first display area and the second display area, the plurality of first windings being located in the frame area, and the plurality of second windings being located in the second display area.

[0139] In some exemplary embodiments, the plurality of first windings include: a plurality of first-type first windings and a plurality of second-type first windings, and the plurality of first-type first windings and the plurality of second-type first windings are alternately disposed and arranged in different conductive layers.

[0140] In some exemplary embodiments, the first color light is green light, the second color light is red light, and the third color light is blue light.

[0141] The relevant description of the display substrate provided in this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0142] Fig.10 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.10As shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 can be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may overlap with the first display area A1. For example, the sensor 92 may be a camera.

[0143] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large area of ​​wall, an information query device (such as business query equipment for e-government, banks, hospitals, power and other departments), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0144] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0145] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising: a first display area and a second display area located at at least one side of the first display area; A plurality of first-region light-emitting elements, located in the first display area, including: a plurality of first light-emitting elements emitting first color light, a plurality of second light-emitting elements emitting second color light, and a plurality of third light-emitting elements emitting third color light; A plurality of first-type pixel circuits, located in the second display area, including: a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of third pixel circuits; the first pixel circuits are connected to at least two first light-emitting elements via a first connecting line, the second pixel circuits are connected to at least one second light-emitting element via a second connecting line, and the third pixel circuits are connected to at least one third light-emitting element via a third connecting line; The length of the first connection line is smaller than the length of the second connection line, and smaller than the length of the third connection line; and the plurality of first connection lines connected to the plurality of first pixel circuits are located in the same conductive layer.

2. The display substrate according to claim 1, characterized in that: The first display area is provided with a plurality of first area display units, each of which includes: two first light-emitting elements, a second light-emitting element and a third light-emitting element; the first pixel circuit is connected to the two first light-emitting elements of a first area display unit through a first connecting line.

3. The display substrate according to claim 1, characterized in that: The conductive layer where the plurality of second connection lines connected to the plurality of second pixel circuits and the plurality of third connection lines connected to the plurality of third pixel circuits are located is different from the conductive layer where the plurality of first connection lines are located.

4. The display substrate according to claim 3, characterized in that: The plurality of second connection lines and the plurality of third connection lines are located on a side of the plurality of first connection lines away from the substrate.

5. The display substrate according to claim 1, characterized in that: The display substrate further comprises: a plurality of first invalid pixel circuits located in the second display area, the plurality of first invalid pixel circuits being located on a side of the plurality of first type pixel circuits away from the first display area; The display substrate also includes: a plurality of data connection lines located in the second display area, the plurality of data connection lines including: a plurality of first data connection lines, a plurality of second data connection lines and a plurality of third data connection lines; the first data connection lines are connected to a plurality of first pixel circuits arranged along a first direction, the second data connection lines are connected to a plurality of second pixel circuits and a plurality of third pixel circuits arranged along the first direction, and the third data connection lines are connected to a plurality of first invalid pixel circuits arranged along the first direction; the plurality of second data connection lines are located on a side of the plurality of first data connection lines away from the first display area, and the plurality of third data connection lines are located on a side of the plurality of second data connection lines away from the first display area.

6. The display substrate according to claim 5, characterized in that: The display substrate further includes: a plurality of second-region light-emitting elements and a plurality of second-type pixel circuits located in the second display area, wherein the plurality of second-region light-emitting elements and the plurality of second-type pixel circuits are electrically connected in a one-to-one correspondence; the plurality of second-region light-emitting elements include: a plurality of fourth light-emitting elements emitting first-color light, a plurality of fifth light-emitting elements emitting second-color light, and a plurality of sixth light-emitting elements emitting third-color light; The display substrate further includes: a plurality of first data lines, the first data lines being configured to provide data signals to a column of second-region light-emitting elements separated by the first display area, the column of second-region light-emitting elements including: a plurality of second-region light-emitting elements arranged along the first direction; Wherein, the first data line for providing data signals to the fifth light-emitting element and the sixth light-emitting element is configured to be connected to the second data connection line; the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the third data connection line; or, the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the third data connection line; The even-numbered columns and odd-numbered columns of first light-emitting elements are determined according to the order of multiple columns of first light-emitting elements in the first display area along a second direction, and the second direction intersects the first direction.

7. The display substrate according to claim 6, characterized in that: The first data line includes: a first routing segment and a second routing segment located at two sides of the first display area along the first direction; The display substrate further includes: a plurality of first windings and a plurality of second windings, the first windings being connected between a first routing segment of the first data line and a data connection line, and the second windings being connected between a second routing segment of the first data line and the data connection line; The substrate further includes: a frame area located outside the first display area and the second display area, the plurality of first windings are located in the frame area, and the plurality of second windings are located in the second display area.

8. The display substrate according to claim 7, characterized in that: The plurality of first windings include: a plurality of first-type first windings and a plurality of second-type first windings, and the plurality of first-type first windings and the plurality of second-type first windings are alternately arranged and disposed in different conductive layers.

9. The display substrate according to claim 8, characterized in that: The first-type first winding wire is connected to the first data connection wire or the third data connection wire, and the second-type first winding wire is connected to the second data connection wire.

10. The display substrate according to claim 9, characterized in that: The plurality of first-type first windings are located on a side of the plurality of second-type first windings away from the substrate.

11. The display substrate according to claim 9, characterized in that: The first type first winding is directly connected to the first routing segment of the first data line; the second type first winding is connected to the first routing segment of the first data line through the first transfer electrode, the first routing segment of the first data line is located on the side of the first transfer electrode away from the substrate, and the first transfer electrode is located on the side of the second type first winding away from the substrate; the first transfer electrode and the first type first winding are in the same layer structure.

12. The display substrate according to claim 11, characterized in that: The second type first winding is located in the first source-drain metal layer, the first type first winding is located in the second source-drain metal layer, the first data line is located in the third source-drain metal layer, the third source-drain metal layer is located on the side of the second source-drain metal layer away from the substrate, and the second source-drain metal layer is located on the side of the first source-drain metal layer away from the substrate.

13. The display substrate according to claim 11, characterized in that: The first type first winding adjacent to the first switching electrode has a straight portion and a folded line portion, the folded line portion is located between two adjacent straight portions and connected to the two straight portions, and the folded line portion bypasses the first switching electrode from one side of the first direction.

14. The display substrate according to any one of claims 1 to 13, characterized in that: The first color light is green light, the second color light is red light, and the third color light is blue light.

15. A display device, characterized in that: The invention comprises a display substrate as claimed in any one of claims 1 to 14, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate overlaps with a first display area of ​​the display substrate.

16. The display device according to claim 15, characterized in that: The sensor is a camera.

17. A display substrate, characterized in that: include: A substrate, comprising: a first display area and a second display area located at at least one side of the first display area; A plurality of first-region light-emitting elements, located in the first display area, including: a plurality of first light-emitting elements emitting first color light, a plurality of second light-emitting elements emitting second color light, and a plurality of third light-emitting elements emitting third color light; a plurality of first-type pixel circuits, located in the second display area, including: a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of third pixel circuits, wherein the first pixel circuits are connected to at least two first light-emitting elements via a first connecting line, the second pixel circuits are connected to at least one second light-emitting element via a second connecting line, and the third pixel circuits are connected to at least one third light-emitting element via a third connecting line; A plurality of first invalid pixel circuits are located in the second display area and located on a side of the plurality of first type pixel circuits away from the first display area; A plurality of second-region light-emitting elements and a plurality of second-type pixel circuits are located in the second display area, the plurality of second-region light-emitting elements and the plurality of second-type pixel circuits are electrically connected in a one-to-one correspondence, and the plurality of second-region light-emitting elements include: a plurality of fourth light-emitting elements emitting first-color light, a plurality of fifth light-emitting elements emitting second-color light, and a plurality of sixth light-emitting elements emitting third-color light; a plurality of data connection lines, located in the second display area, including: a plurality of first data connection lines, a plurality of second data connection lines and a plurality of third data connection lines, the first data connection lines being connected to a plurality of first pixel circuits arranged along a first direction, the second data connection lines being connected to a plurality of second pixel circuits and a plurality of third pixel circuits arranged along the first direction, and the third data connection lines being connected to a plurality of first invalid pixel circuits arranged along the first direction; the plurality of second data connection lines being located on a side of the plurality of first data connection lines away from the first display area, and the plurality of third data connection lines being located on a side of the plurality of second data connection lines away from the first display area; a plurality of first data lines, wherein the first data lines are configured to provide data signals to a column of second-region light-emitting elements separated by the first display area, wherein the column of second-region light-emitting elements comprises: a plurality of second-region light-emitting elements arranged along the first direction; Wherein, the first data line for providing data signals to the fifth light-emitting element and the sixth light-emitting element is configured to be connected to the second data connection line; the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the third data connection line; or, the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the even-numbered columns in the first display area is configured to be connected to the first data connection line, and the first data line for providing data signals to the fourth light-emitting element aligned with the first light-emitting element in the odd-numbered columns in the first display area is configured to be connected to the third data connection line; The even-numbered columns and the odd-numbered columns of first light-emitting elements are determined according to the order of a plurality of columns of first light-emitting elements in the first display area along a second direction, and the second direction intersects the first direction.

18. The display substrate according to claim 17, characterized in that: The first data line includes: a first routing segment and a second routing segment located at two sides of the first display area along the first direction; The display substrate further includes: a plurality of first windings and a plurality of second windings, the first windings being connected between a first routing segment of the first data line and a data connection line, and the second windings being connected between a second routing segment of the first data line and the data connection line; The substrate further includes: a frame area located outside the first display area and the second display area, the plurality of first windings are located in the frame area, and the plurality of second windings are located in the second display area.

19. The display substrate according to claim 18, characterized in that: The plurality of first windings include: a plurality of first-type first windings and a plurality of second-type first windings, and the plurality of first-type first windings and the plurality of second-type first windings are alternately arranged and disposed in different conductive layers.

20. The display substrate according to claim 17, characterized in that: The first color light is green light, the second color light is red light, and the third color light is blue light.

Images