Voltage-controlled constant-temperature crystal oscillator frequency adjusting module

Abstract

The utility model discloses a voltage-controlled constant-temperature crystal oscillator frequency adjusting module, and relates to the technical field of radio. The circuit comprises an FPGA chip, a digital-to-analog conversion circuit, a phase-locked loop circuit, a loop filter, an analog switch, a crystal oscillator tuning voltage circuit and two power dividers. The input end of the FPGA chip receives a control command, and three output ends of the FPGA chip are respectively connected with the input end of the phase-locked loop circuit, the input end of the digital-to-analog conversion circuit and the NC pin of the analog switch; the output end of the digital-to-analog conversion circuit is connected with the NC pin of the analog switch; two input ends of the phase-locked loop circuit are respectively connected with a reference signal and an output command of the FPGA chip; the output end of the phase-locked loop circuit is connected with the NO pin of the analog switch; a COM pin of the analog switch is connected with the input end of the crystal oscillator tuning voltage circuit, a tuning voltage is output to the constant temperature crystal oscillator, the crystal oscillator tuning voltage circuit outputs a signal to the two power dividers, the two power dividers divide the signal into two paths, one path outputs a crystal oscillator signal, and the other path is fed back to the phase-locked loop circuit.

Description

Technical Field

[0001] The utility model relates to the field of radio technology, in particular to a voltage-controlled constant temperature crystal oscillator frequency adjustment module. Background Art

[0002] As the heart of electronic products, crystal oscillators provide reference signals for all kinds of electronic products. With the rapid development of radio communication and radio monitoring technology, the whole system has put forward higher and more stringent requirements for signal frequency accuracy. As the reference signal of the whole system, the crystal oscillator signal requires its output frequency signal to remain accurate for a long time. However, since its internal components will age after long-term operation, the output frequency will drift, and the output signal frequency will no longer be accurate. At this time, external means must be used to readjust the crystal oscillator frequency accurately.

[0003] At present, the frequency accuracy of the constant temperature crystal oscillator is mostly adjusted by a resistor voltage divider circuit. After the resistance value of the voltage divider resistor in the circuit is fixed, the voltage control voltage of the tuned constant temperature crystal oscillator will also be fixed. However, after the constant temperature crystal oscillator has worked for a long time, the crystal inside the constant temperature crystal oscillator ages, the frequency of the constant temperature crystal oscillator will shift, and the voltage control voltage of the tuned constant temperature crystal oscillator will not change, resulting in the frequency of the constant temperature crystal oscillator shifting. If the voltage divider resistor in the circuit is changed to an adjustable resistor, the frequency of the constant temperature crystal oscillator will shift after the constant temperature crystal oscillator has worked for a long time. The resistance value can be manually adjusted outside the product to change the voltage control voltage and recalibrate the constant temperature crystal oscillator. However, this method is limited by the product use environment and can only be used in indoor environments. If it is used outdoors such as on a signal tower, later maintenance will be very difficult. Utility Model Content

[0004] The purpose of the utility model is to provide a voltage-controlled constant temperature crystal oscillator frequency adjustment module, which is used in conjunction with a voltage-controlled constant temperature crystal oscillator frequency adjustment method. As the hardware support of the voltage-controlled constant temperature crystal oscillator frequency adjustment method, a digital-to-analog conversion circuit and a phase-locked loop circuit are provided. The analog switch is controlled by software commands to connect the above two circuits with a crystal oscillator tuning circuit, and the crystal oscillator frequency self-calibration and synchronization external reference signal functions can be remotely realized to solve the problems of the prior art.

[0005] In order to achieve the above purpose, the technical solution adopted by the utility model is as follows:

[0006] A voltage-controlled constant temperature crystal oscillator frequency adjustment module, comprising an FPGA chip, a digital-to-analog conversion circuit, a phase-locked loop circuit, a loop filter circuit, an analog switch circuit, a crystal oscillator tuning voltage circuit, and a two-power divider circuit;

[0007] The input end of the FPGA chip receives the control command, and the three output ends of the FPGA chip are respectively connected to the input end of the phase-locked loop circuit, the input end of the digital-to-analog conversion circuit, and the NC pin of the analog switch; the output end of the digital-to-analog conversion circuit is connected to the NC pin of the analog switch;

[0008] The two input ends of the phase-locked loop circuit are respectively connected to the reference signal and the output command of the above-mentioned FPGA chip; the output end of the phase-locked loop circuit is connected to the NO pin of the analog switch in the analog switch circuit through the loop filter circuit;

[0009] The COM pin of the analog switch is connected to the input end of the crystal oscillator tuning voltage circuit, and the tuning voltage is output to the constant temperature crystal oscillator. The crystal oscillator tuning voltage circuit outputs a signal to the two-power divider circuit. The two-power divider circuit divides the signal into two paths, one of which outputs the crystal oscillator signal and the other signal is fed back to the phase-locked loop circuit.

[0010] As a preferred technical solution, the analog switch is an analog single-pole double-throw switch.

[0011] As a preferred technical solution, when the constant temperature crystal oscillator frequency needs to be self-adjusted, the analog switch connects the digital-to-analog conversion circuit and the crystal oscillator tuning voltage circuit; the FPGA chip controls the digital-to-analog conversion circuit to generate the required tuning voltage and change the constant temperature crystal oscillator frequency.

[0012] When the constant temperature crystal oscillator signal needs to be synchronized with the external reference signal, the analog switch connects the phase-locked loop circuit and the crystal oscillator tuning voltage circuit, and the FPGA chip controls the phase-locked loop circuit to lock the constant temperature crystal oscillator, so that the constant temperature crystal oscillator signal is synchronized with the external reference signal.

[0013] As a preferred technical solution, the FPGA chip model is GW2A-LV18QN88C8 / I7.

[0014] As a preferred technical solution, the digital-to-analog conversion circuit includes a DAC chip U2, the model of which is CBM53D24AMS; pin 1 of the DAC chip U2 is connected to one end of a resistor R4, the positive electrode of a polar capacitor C4, and one end of an inductor B1; the other end of the inductor B1 is connected to a 5V voltage; the negative electrode of the polar capacitor C4 is grounded; pin 5 of the DAC chip U2 is connected to the other end of the resistor R4 and one end of a resistor R5; the other end of the resistor R5 is grounded; pin 6 of the DAC chip U2 is connected to one end of a resistor R6, the other end of the resistor R6 is connected to the other end of the capacitor C5, and serves as The output end DAC-OUT of the digital-to-analog conversion circuit; Pins 8, 9 and 10 of the DAC chip U2 are respectively connected to one end of the resistor R1, one end of the resistor R2 and one end of the resistor R3; the other end of the resistor R1, the other end of the resistor R2 and the other end of the resistor R3 are respectively connected to Pins 86, 85 and 84 of the FPGA chip U1; the other end of the resistor R1, the other end of the resistor R2 and the other end of the resistor R3 are also respectively connected to one end of the capacitor C1, one end of the capacitor C2 and one end of the capacitor C3; the other end of the capacitor C1, the other end of the capacitor C2 and the other end of the capacitor C3 are grounded.

[0015] As a preferred technical solution, the phase-locked loop circuit includes a phase detector U3, the model of which is ADF4002BRUZ; the pin 1 of the phase detector U3 is connected to the ground through a resistor R12; the pin 2 of the phase detector U3 is connected to the loop filter; the pin 5 of the phase detector U3 is connected to one end of capacitor C12, and the other end of capacitor C12 is connected to the ground through a resistor R11; the pin 6 of the phase detector U3 is connected to one end of capacitor C11, and the other end of capacitor C11 is connected to the constant temperature crystal oscillator signal fed back; the pin 7 of the phase detector U3 is connected to one end of capacitor C10 and connected to a 3.3V voltage; the other end of capacitor C10 is grounded; the pin 8 of the phase detector U3 is connected to Connect one end of capacitor C6; the other end of capacitor C6 is connected to the RF signal; pin 10 of phase detector U3 is connected to one end of capacitor C7 and connected to 3.3V voltage; the other end of capacitor C7 is grounded; pins 11, 12, 13 and 14 of phase detector U3 are connected to pins 37, 38, 39 and 40 of FPGA chip U1 through resistors R7, R8, R9 and R10 respectively; pin 15 of phase detector U3 is connected to one end of capacitor C8 and connected to 3.3V voltage; the other end of capacitor C8 is grounded; pin 16 of phase detector U3 is connected to one end of capacitor C9 and connected to 5V voltage, and the other end of capacitor C9 is grounded.

[0016] As a preferred technical solution, the loop filter circuit includes a capacitor C13, one end of the capacitor C13, one end of the resistor R13, and one end of the resistor R14; the other end of the capacitor C13 is grounded; the other end of the resistor R13 is connected to the ground through the capacitor C14; the other end of the resistor R14 is connected to one end of the capacitor C15 as the output end PLL-VT.

[0017] As a preferred technical solution, the analog switch circuit includes an analog switch U6, and the model of the analog switch U6 is MAX4649EKA+T; pin 1 of the analog switch U6 is connected to the crystal oscillator tuning voltage circuit; pin 2 of the analog switch U6 is connected to the output end DAC-OUT of the digital-to-analog conversion circuit; pin 4 of the analog switch U6 is connected to one end of the capacitor C6 and connected to a 5V voltage, and the other end of the capacitor C6 is grounded; pin 6 of the analog switch U6 is connected to pin 75 of the FPGA chip U1 through a resistor R15; pin 7 of the analog switch U6 is grounded, and pin 8 of the analog switch U6 is connected to the output end PLL-VT of the loop filter.

[0018] As a preferred technical solution, the crystal oscillator tuning voltage circuit includes a constant temperature crystal oscillator U4, and the model of the constant temperature crystal oscillator U4 is JTM2056B; the 1st pin of the constant temperature crystal oscillator U4 is connected to the analog switch U6, and the 5th pin of the constant temperature crystal oscillator U4 is connected to one end of the capacitor C18, one end of the capacitor C19, one end of the capacitor C20, the positive electrode of the polar capacitor C21, and one end of the inductor B2; the other end of the inductor B2 is connected to a 5V voltage; the other end of the capacitor C18 is connected to the other end of the capacitor C19, the other end of the capacitor C20, the negative electrode of the polar capacitor C21 and grounded;

[0019] Pin 4 of the constant temperature crystal oscillator U4 is connected to one end of the capacitor C17, and the other end of the capacitor C17 is connected to the two-power divider;

[0020] The two-power divider circuit includes a power divider U5, and the model of the power divider U5 is SBTC-2-10L+; the 6th pin of the power divider U5 is connected to the constant temperature crystal oscillator through the capacitor C17; the 3rd pin of the power divider U5 outputs the crystal oscillator signal to the outside, and the 4th pin of the power divider U5 outputs the crystal oscillator signal to the phase-locked loop circuit.

[0021] Compared with the prior art, the utility model has the following beneficial effects:

[0022] The utility model is provided with a digital-to-analog conversion circuit and a phase-locked loop circuit, and the analog switch can be controlled by software commands to connect the two circuits with the crystal oscillator tuning circuit, so that the crystal oscillator frequency self-calibration and synchronization external reference signal functions can be remotely realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is the principle diagram of the utility model;

[0024] Figure 2 This is the circuit schematic diagram of the FPGA chip;

[0025] Figure 3 is a circuit schematic diagram of a digital-to-analog conversion circuit;

[0026] Figure 4 is a circuit schematic diagram of a phase-locked loop circuit;

[0027] Figure 5 This is the circuit schematic of the crystal oscillator tuning voltage circuit. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] On the contrary, the present application covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present application as defined by the claims. Further, in order to make the public have a better understanding of the present application, some specific details are described in detail in the detailed description of the present application below. Those skilled in the art can fully understand the present application without the description of these details.

[0030] Example 1

[0031] like Figure 1 As shown, a voltage-controlled constant temperature crystal oscillator frequency adjustment module includes an FPGA chip, a digital-to-analog conversion circuit (DAC), a phase-locked loop circuit, a loop filter, an analog switch, a crystal oscillator tuning voltage circuit, and a two-power divider.

[0032] Preferably, the analog switch is an analog single-pole double-throw switch.

[0033] Further, the input end of the FPGA chip receives the control command, and the three output ends of the FPGA chip are respectively connected to the input end of the phase-locked loop circuit, the input end of the digital-to-analog conversion circuit, and the NC pin of the analog switch;

[0034] The output end of the digital-to-analog conversion circuit is connected to the NC pin of the analog switch;

[0035] The two input ends of the phase-locked loop circuit are connected to the reference signal and the output command of the above-mentioned FPGA chip respectively; the output end of the phase-locked loop circuit is connected to the NO pin of the analog switch;

[0036] The COM pin of the analog switch is connected to the input end of the crystal oscillator tuning voltage circuit, and the tuning voltage is output to the constant temperature crystal oscillator. The constant temperature crystal oscillator outputs the signal to the two-power divider, and the two-power divider divides the signal into two paths, one of which outputs the crystal oscillator signal and the other signal is fed back to the phase-locked loop circuit.

[0037] In this embodiment, the controlled devices inside the FPGA chip control module are set; different tuning voltages are generated by setting a digital-to-analog conversion circuit to adjust the crystal oscillator frequency; the internal crystal oscillator is locked by setting a phase-locked loop circuit and a loop filter, so that the internal constant temperature crystal oscillator signal is synchronized with the external reference signal; the DAC voltage and the phase-locked loop voltage are switched by setting an analog switch, so as to adjust the constant temperature crystal oscillator frequency internally and externally; the constant temperature crystal oscillator output signal is set; and the constant temperature crystal oscillator output signal is divided into two paths by setting a two-power divider, one path is directly output, and the other path is fed back to the phase-locked loop to participate in phase locking.

[0038] As a preferred mode, the constant temperature crystal oscillator outputs a 120 MHz signal.

[0039] The principle of the utility model is as follows: by receiving user control commands, the internal FPGA of the product decodes the user control commands and generates different control sub-commands to control the controlled devices inside the module. When the internal constant temperature crystal oscillator frequency of the product needs to be self-adjusted, command 1 connects the analog switch to the DAC and the crystal oscillator tuning voltage circuit, and command 2 controls the DAC to generate the required tuning voltage, thereby changing the constant temperature crystal oscillator frequency. When the internal constant temperature crystal oscillator signal of the product needs to be synchronized with the external reference signal, command 1 connects the analog switch to the phase-locked loop circuit and the crystal oscillator tuning voltage circuit, and command 3 controls the phase-locked loop to lock the constant temperature crystal oscillator, so that the constant temperature crystal oscillator signal is synchronized with the external reference signal.

[0040] The method for adjusting the frequency of the voltage-controlled constant temperature crystal oscillator is as follows:

[0041] When the user needs the product's internal constant temperature crystal oscillator to adjust its frequency, the user can send a software command to connect the crystal oscillator tuning voltage circuit that tunes the constant temperature crystal oscillator frequency to the DAC. The DAC outputs different voltages to adjust the constant temperature crystal oscillator voltage control voltage, thereby achieving constant temperature crystal oscillator frequency adjustment. When the user needs the product's internal constant temperature crystal oscillator signal to be synchronized with an external reference signal, the user can send a software command to connect the crystal oscillator tuning voltage circuit that tunes the constant temperature crystal oscillator frequency to the phase-locked loop circuit. The phase-locked loop will lock the constant temperature crystal oscillator, and the output signal of the constant temperature crystal oscillator will be synchronized with the external reference signal.

[0042] The circuit principle of the above FPGA chip is as follows Figure 2 As shown, the model of the FPGA chip is GW2A-LV18QN88C8 / I7.

[0043] Digital-to-analog conversion circuits such as Figure 3 As shown, it includes a DAC chip U2, and the model of the DAC chip U2 is CBM53D24AMS; the 1st pin of the DAC chip U2 is connected to one end of the resistor R4, the positive electrode of the polar capacitor C4, and one end of the inductor B1; the other end of the inductor B1 is connected to a 5V voltage; the negative electrode of the polar capacitor C4 is grounded; the 5th pin of the DAC chip U2 is connected to the other end of the resistor R4 and one end of the resistor R5; the other end of the resistor R5 is grounded; the 6th pin of the DAC chip U2 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the other end of the capacitor C5, and serves as the digital-to-analog conversion circuit. Output terminal DAC-OUT; Pins 8, 9 and 10 of DAC chip U2 are respectively connected to one end of resistor R1, one end of resistor R2 and one end of resistor R3; the other end of resistor R1, the other end of resistor R2 and the other end of resistor R3 are respectively connected to pins 86, 85 and 84 of FPGA chip U1; the other end of resistor R1, the other end of resistor R2 and the other end of resistor R3 are also respectively connected to one end of capacitor C1, one end of capacitor C2 and one end of capacitor C3; the other end of capacitor C1, the other end of capacitor C2 and the other end of capacitor C3 are grounded.

[0044] Phase-locked loop circuit Figure 4 As shown, it includes a phase detector U3, the model of the phase detector U3 is ADF4002BRUZ; the 1st pin of the phase detector U3 is connected to the ground through the resistor R12; the 2nd pin of the phase detector U3 is connected to the loop filter; the 5th pin of the phase detector U3 is connected to one end of the capacitor C12, and the other end of the capacitor C12 is connected to the ground through the resistor R11; the 6th pin of the phase detector U3 is connected to one end of the capacitor C11, and the other end of the capacitor C11 is connected to the feedback constant temperature crystal oscillator signal; the 7th pin of the phase detector U3 is connected to one end of the capacitor C10 and connected to the 3.3V voltage; the other end of the capacitor C10 is grounded; the 8th pin of the phase detector U3 is connected to one end of the capacitor C6 end; the other end of capacitor C6 is connected to the RF signal; pin 10 of phase detector U3 is connected to one end of capacitor C7 and connected to 3.3V voltage; the other end of capacitor C7 is grounded; pins 11, 12, 13 and 14 of phase detector U3 are connected to pins 37, 38, 39 and 40 of FPGA chip U1 through resistors R7, R8, R9 and R10 respectively; pin 15 of phase detector U3 is connected to one end of capacitor C8 and connected to 3.3V voltage; the other end of capacitor C8 is grounded; pin 16 of phase detector U3 is connected to one end of capacitor C9 and connected to 5V voltage, and the other end of capacitor C9 is grounded.

[0045] The loop filter circuit includes a capacitor C13, one end of the capacitor C13, one end of the resistor R13, and one end of the resistor R14; the other end of the capacitor C13 is grounded; the other end of the resistor R13 is connected to the ground through the capacitor C14; the other end of the resistor R14 is connected to one end of the capacitor C15 as the output end PLL-VT.

[0046] Analog switch circuits such as Figure 5 As shown, it includes an analog switch U6, and the model of the analog switch U6 is MAX4649EKA+T; the pin 1 of the analog switch U6 is connected to the crystal tuning voltage circuit; the pin 2 of the analog switch U6 is connected to the output end DAC-OUT of the digital-to-analog conversion circuit; the pin 4 of the analog switch U6 is connected to one end of the capacitor C6 and connected to the 5V voltage, and the other end of the capacitor C6 is grounded; the pin 6 of the analog switch U6 is connected to the pin 75 of the FPGA chip U1 through the resistor R15; the pin 7 of the analog switch U6 is grounded, and the pin 8 of the analog switch U6 is connected to the output end PLL-VT of the loop filter.

[0047] Crystal oscillator tuning voltage circuit such as Figure 5As shown, the crystal oscillator tuning voltage circuit includes a constant temperature crystal oscillator U4, and the model of the constant temperature crystal oscillator U4 is JTM2056B; the 1st pin of the constant temperature crystal oscillator U4 is connected to the radio frequency switch, and the 5th pin of the constant temperature crystal oscillator U4 is connected to one end of the capacitor C18, one end of the capacitor C19, one end of the capacitor C20, the positive electrode of the polar capacitor C21, and one end of the inductor B2; the other end of the inductor B2 is connected to a 5V voltage; the other end of the capacitor C18 is connected to the other end of the capacitor C19, the other end of the capacitor C20, the negative electrode of the polar capacitor C21 and grounded;

[0048] Pin 4 of the constant temperature crystal oscillator U4 is connected to one end of the capacitor C17, and the other end of the capacitor C17 is connected to the two-power divider.

[0049] The two-power divider circuit includes a power divider U5, and the model of the power divider U5 is SBTC-2-10L+; the 6th pin of the power divider U5 is connected to the constant temperature crystal oscillator through the capacitor C17; the 3rd pin of the power divider U5 outputs the crystal oscillator signal to the outside, and the 4th pin of the power divider U5 outputs the crystal oscillator signal to the phase-locked loop circuit.

[0050] It is worth noting that, based on the above structural design, in order to solve the same technical problem, even if some insubstantial improvements are made on the present invention, they also fall within the protection scope of the present invention.

Claims

1. A voltage-controlled constant temperature crystal oscillator frequency adjustment module, characterized in that: Including FPGA chip, digital-to-analog conversion circuit, phase-locked loop circuit, loop filter circuit, analog switch circuit, crystal oscillator tuning voltage circuit, and two-power divider circuit; The input end of the FPGA chip receives the control command, and the three output ends of the FPGA chip are respectively connected to the input end of the phase-locked loop circuit, the input end of the digital-to-analog conversion circuit, and the NC pin of the analog switch; the output end of the digital-to-analog conversion circuit is connected to the NC pin of the analog switch; The two input ends of the phase-locked loop circuit are respectively connected to the reference signal and the output command of the above-mentioned FPGA chip; the output end of the phase-locked loop circuit is connected to the NO pin of the analog switch in the analog switch circuit through the loop filter circuit; The COM pin of the analog switch is connected to the input end of the crystal oscillator tuning voltage circuit, and the tuning voltage is output to the constant temperature crystal oscillator. The crystal oscillator tuning voltage circuit outputs a signal to the two-power divider circuit. The two-power divider circuit divides the signal into two paths, one of which outputs the crystal oscillator signal and the other signal is fed back to the phase-locked loop circuit.

2. A voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 1, characterized in that: The analog switch simulates a single-pole double-throw switch.

3. The voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 1, characterized in that: When the constant temperature crystal oscillator frequency needs to be adjusted automatically, the analog switch connects the digital-to-analog conversion circuit and the crystal oscillator tuning voltage circuit; the FPGA chip controls the digital-to-analog conversion circuit to generate the required tuning voltage to change the constant temperature crystal oscillator frequency; When the constant temperature crystal oscillator signal needs to be synchronized with the external reference signal, the analog switch connects the phase-locked loop circuit and the crystal oscillator tuning voltage circuit, and the FPGA chip controls the phase-locked loop circuit to lock the constant temperature crystal oscillator, so that the constant temperature crystal oscillator signal is synchronized with the external reference signal.

4. The voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 1, characterized in that: The model of the FPGA chip is GW2A-LV18QN88C8 / I7.

5. The voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 1, characterized in that: The digital-to-analog conversion circuit includes a DAC chip U2, and the model of the DAC chip U2 is CBM53D24AMS; the 1st pin of the DAC chip U2 is connected to one end of the resistor R4, the positive electrode of the polar capacitor C4, and one end of the inductor B1; the other end of the inductor B1 is connected to a 5V voltage; the negative electrode of the polar capacitor C4 is grounded; the 5th pin of the DAC chip U2 is connected to the other end of the resistor R4 and one end of the resistor R5; the other end of the resistor R5 is grounded; the 6th pin of the DAC chip U2 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the other end of the capacitor C5, and serves as a digital-to-analog conversion circuit. The output end DAC-OUT of the circuit; Pins 8, 9 and 10 of the DAC chip U2 are respectively connected to one end of the resistor R1, one end of the resistor R2, and one end of the resistor R3; the other end of the resistor R1, the other end of the resistor R2, and the other end of the resistor R3 are respectively connected to Pins 86, 85, and 84 of the FPGA chip U1; the other end of the resistor R1, the other end of the resistor R2, and the other end of the resistor R3 are also connected to one end of the capacitor C1, one end of the capacitor C2, and one end of the capacitor C3; the other end of the capacitor C1, the other end of the capacitor C2, and the other end of the capacitor C3 are grounded.

6. A voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 5, characterized in that: The phase-locked loop circuit includes a phase detector U3, the model of which is ADF4002BRUZ; pin 1 of the phase detector U3 is connected to the ground through a resistor R12; pin 2 of the phase detector U3 is connected to the loop filter; pin 5 of the phase detector U3 is connected to one end of capacitor C12, and the other end of capacitor C12 is connected to the ground through a resistor R11; pin 6 of the phase detector U3 is connected to one end of capacitor C11, and the other end of capacitor C11 is connected to the feedback constant temperature crystal oscillator signal; pin 7 of the phase detector U3 is connected to one end of capacitor C10 and connected to a 3.3V voltage; the other end of capacitor C10 is grounded; pin 8 of the phase detector U3 is connected to the one end; the other end of capacitor C6 is connected to the RF signal; pin 10 of phase detector U3 is connected to one end of capacitor C7 and connected to 3.3V voltage; the other end of capacitor C7 is grounded; pins 11, 12, 13 and 14 of phase detector U3 are connected to pins 37, 38, 39 and 40 of FPGA chip U1 through resistors R7, R8, R9 and R10 respectively; pin 15 of phase detector U3 is connected to one end of capacitor C8 and connected to 3.3V voltage; the other end of capacitor C8 is grounded; pin 16 of phase detector U3 is connected to one end of capacitor C9 and connected to 5V voltage, and the other end of capacitor C9 is grounded.

7. The voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 6, characterized in that: The loop filter circuit includes a capacitor C13, one end of the capacitor C13, one end of the resistor R13, and one end of the resistor R14; the other end of the capacitor C13 is grounded; the other end of the resistor R13 is connected to the ground through the capacitor C14; the other end of the resistor R14 is connected to one end of the capacitor C15 as the output end PLL-VT.

8. The voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 7, characterized in that: The analog switch circuit includes an analog switch U6, and the model of the analog switch U6 is MAX4649EKA+T; the pin 1 of the analog switch U6 is connected to the crystal oscillator tuning voltage circuit; the pin 2 of the analog switch U6 is connected to the output terminal DAC-OUT of the digital-to-analog conversion circuit; Pin 4 of analog switch U6 is connected to one end of capacitor C6 and connected to 5V voltage, and the other end of capacitor C6 is grounded; Pin 6 of analog switch U6 is connected to pin 75 of FPGA chip U1 through resistor R15; Pin 7 of the analog switch U6 is grounded, and pin 8 of the analog switch U6 is connected to the output terminal PLL-VT of the loop filter.

9. The voltage-controlled oven-controlled crystal oscillator frequency adjustment module according to claim 8, characterized in that: The crystal oscillator tuning voltage circuit includes a constant temperature crystal oscillator U4, and the model of the constant temperature crystal oscillator U4 is JTM2056B; the pin 1 of the constant temperature crystal oscillator U4 is connected to the analog switch U6, and the pin 5 of the constant temperature crystal oscillator U4 is connected to one end of the capacitor C18, one end of the capacitor C19, one end of the capacitor C20, the positive electrode of the polar capacitor C21, and one end of the inductor B2; the other end of the inductor B2 is connected to a 5V voltage; the other end of the capacitor C18 is connected to the other end of the capacitor C19, the other end of the capacitor C20, the negative electrode of the polar capacitor C21 and grounded; Pin 4 of the constant temperature crystal oscillator U4 is connected to one end of the capacitor C17, and the other end of the capacitor C17 is connected to the two-power divider; The two-power divider circuit includes a power divider U5, and the model of the power divider U5 is SBTC-2-10L+; the 6th pin of the power divider U5 is connected to the constant temperature crystal oscillator through the capacitor C17; the 3rd pin of the power divider U5 outputs the crystal oscillator signal to the outside, and the 4th pin of the power divider U5 outputs the crystal oscillator signal to the phase-locked loop circuit.

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