A piezoelectric ceramic detection circuit and system
By designing a piezoelectric ceramic detection circuit including comparator U1A, transistor Q1, transistor Q2 and other components, the problems of unstable and false alarms in the prior art are solved, accurate detection and circuit recovery of piezoelectric ceramics are achieved, and the stability and accuracy of detection are improved.
Patent Information
- Application Number
- CN202421575980.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-07-04
AI Technical Summary
The existing piezoelectric ceramic detection system has unstable and inaccurate detection, and is prone to false alarms and repeated signals, which urgently needs to be improved.
A piezoelectric ceramic detection circuit is designed, including comparator U1A, transistor Q1, transistor Q2, first voltage divider resistor R3 and second voltage divider resistor R4. By comparing the detection signal to the reference voltage of the comparator U1A, a low-level signal is output to lock the abnormal signal, and the circuit recovery is realized through transistors Q1 and Q2.
Accurate and stable detection of piezoelectric ceramics is achieved, preventing repeated signals and false alarms, and accurately determining whether piezoelectric ceramics are temporary overload or complete damage, and circuit recovery is achieved when determining temporary overload, extending the service life of piezoelectric ceramics.
Smart Images
Figure CN222704112U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of electronic circuits, and in particular relates to a piezoelectric ceramic detection circuit and system. Background Art
[0002] Piezoelectric ceramics are information functional ceramic materials that can convert mechanical energy and electrical energy into each other. Under the action of mechanical stress, the internal positive and negative charge centers can be relatively displaced and polarized, which in turn leads to the appearance of bound charges of opposite signs on the surfaces of both ends of the material. Piezoelectric ceramics have a wide range of applications due to their piezoelectricity, dielectricity, elasticity, etc.
[0003] In some application fields, piezoelectric ceramics are consumables, easy to damage, and have high cost. Therefore, the detection and protection of piezoelectric ceramics are very important. At present, the piezoelectric ceramic detection systems on the market generally have unstable and inaccurate detection, prone to false alarms and repeated signals, and urgently need to be improved. Utility Model Content
[0004] The purpose of the utility model is to provide a piezoelectric ceramic detection circuit and system to solve the above problems existing in the prior art.
[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0006] The utility model provides a piezoelectric ceramic detection circuit, comprising a comparator U1A, a transistor Q1, a transistor Q2, a first voltage-dividing resistor R3 and a second voltage-dividing resistor R4, wherein the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4 are connected in series, one end of the first voltage-dividing resistor R3 is grounded, one end of the second voltage-dividing resistor R4 is connected to a power supply VCC, a non-phase input end of the comparator U1A is connected to a common connection end of the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4, an inverting input end of the comparator U1A is connected to a piezoelectric ceramic load end DET, an output end of the comparator U1A is connected to a base of the transistor Q2 and an external processor, a collector of the transistor Q2 is connected to an inverting input end of the comparator U1A, an emitter of the transistor Q2 is connected to a power supply VCC, a collector of the transistor Q1 is connected to an inverting input end of the comparator U1A, the emitter of the transistor Q1 is grounded, and the base of the transistor Q1 is connected to an external processor.
[0007] When it is used, the signal to be detected at the piezoelectric ceramic load end DET is transmitted to the inverting input end of the comparator U1A, and the comparator U1A compares the voltage of the signal to be detected at the inverting input end with the reference voltage input at the non-inverting input end. When the signal to be detected is abnormal and causes the voltage at the inverting input end to be higher than the reference voltage input at the non-inverting input end, the output end of the comparator U1A outputs a low-level signal, and the external processor makes a judgment and alarm after receiving the low-level signal output by the comparator U1A. At the same time, the low-level signal output by the comparator U1A turns on the transistor Q2. After the transistor Q2 is turned on, the voltage at the inverting input end of the comparator U1A will continue to be higher than the non-inverting input end, so that the output end of the comparator U1A always outputs a low-level signal to lock the abnormal signal, prevent the signal from switching back and forth to cause the external processor to misjudge, and reserve sufficient time for the external processor to process the signal. When transistor Q2 maintains the low-level signal and allows the external processor to complete more accurate multiple signal processing, if the external processor determines that the piezoelectric ceramic is temporarily overloaded and the circuit needs to be restored, a high-level signal is output to the base of transistor Q1, causing transistor Q1 to be turned on. After transistor Q1 is turned on, the voltage at the inverting input terminal of comparator U1A will be lower than the reference voltage at the non-inverting input terminal, and the output terminal of comparator U1A will output a high-level signal, thereby restoring the circuit to normal.
[0008] In one possible design, the comparator U1A is implemented as an operational amplifier.
[0009] In a possible design, the transistor Q1 is an NPN transistor, and the transistor Q2 is a PNP transistor.
[0010] In a possible design, a capacitor C3 is connected to the common terminal of the base of the transistor Q2 and the output terminal of the comparator U1A, and the other terminal of the capacitor C3 is grounded.
[0011] In a possible design, the capacitor C3 is a chip capacitor with a capacitance in the range of 1nF-4.7nF.
[0012] In a possible design, a current limiting resistor R1 and a current limiting resistor R6 are connected between the non-phase input terminal of the comparator U1A and the piezoelectric ceramic load terminal DET, a current limiting resistor R5 is connected between the inverting input terminal of the comparator U1A and the common connection terminal of the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4, a current limiting resistor R11 is connected between the output terminal of the comparator U1A and the power supply VCC, and a current limiting resistor R12 is connected between the output terminal of the comparator U1A and the base of the transistor Q2.
[0013] In a possible design, a current limiting resistor R7 is connected between the base of the transistor Q1 and the external processor, the base of the transistor Q1 is connected to a discharge resistor R8, the other end of the discharge resistor R8 is grounded, a current limiting resistor R9 is connected between the emitter of the transistor Q2 and the power supply VCC, and a third voltage dividing resistor R10 is connected between the base and emitter of the transistor Q2.
[0014] The utility model provides a piezoelectric ceramic detection system, comprising a central processing unit and the above-mentioned piezoelectric ceramic detection circuit, wherein the output end of the comparator U1A in the piezoelectric ceramic detection circuit is connected to the signal input end of the central processing unit, and the base of the transistor Q1 in the piezoelectric ceramic detection circuit is connected to the signal control end of the central processing unit.
[0015] Beneficial effects: The utility model can realize accurate and stable detection of piezoelectric ceramics, and when abnormal signals of piezoelectric ceramics are detected, the abnormal signals are locked so that the processor can perform multiple analyses during the signal retention period, thereby accurately determining whether the piezoelectric ceramics are temporarily overloaded or completely damaged, so as to make corresponding correct alarms and prevent signal repetition and false alarms. At the same time, the utility model can also restore the circuit when determining that the piezoelectric ceramics are temporarily overloaded, allowing the piezoelectric ceramics to continue working, preventing the piezoelectric ceramics that could have continued to work from being eliminated due to misjudgment, and saving a lot of costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0017] Figure 1 A schematic diagram of a circuit structure provided for an embodiment of the utility model. DETAILED DESCRIPTION
[0018] It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. The specific structural and functional details disclosed herein are only used to describe the exemplary embodiments of the present invention. However, the present invention can be embodied in many alternative forms, and it should not be understood that the present invention is limited to the embodiments described herein.
[0019] It should be understood that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments can be understood according to specific circumstances.
[0020] In the following description, certain details are provided to facilitate a complete understanding of the example embodiments. However, it will be appreciated by those of ordinary skill in the art that the example embodiments may be implemented without these certain details. For example, the system may be shown in a block diagram to avoid obscuring the example with unnecessary details. In other embodiments, well-known processes, structures, and techniques may not be shown in unnecessary detail to avoid obscuring the embodiments.
[0021] Example:
[0022] This embodiment provides a piezoelectric ceramic detection circuit, such as Figure 1 As shown, it includes a comparator U1A, a transistor Q1, a transistor Q2, a first voltage-dividing resistor R3 and a second voltage-dividing resistor R4, the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4 are connected in series, and one end of the first voltage-dividing resistor R3 is grounded, and one end of the second voltage-dividing resistor R4 is connected to the power supply VCC, the non-inverting input end of the comparator U1A is connected to the common connection end of the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4, the inverting input end of the comparator U1A is connected to the piezoelectric ceramic load end DET, the output end of the comparator U1A is connected to the base of the transistor Q2 and the external processor, the collector of the transistor Q2 is connected to the inverting input end of the comparator U1A, the emitter of the transistor Q2 is connected to the power supply VCC, the collector of the transistor Q1 is connected to the inverting input end of the comparator U1A, the emitter of the transistor Q1 is grounded, and the base of the transistor Q1 is connected to the external processor.
[0023] In specific implementation, the comparator U1A can use an operational amplifier, the transistor Q1 uses an NPN transistor, and the transistor Q2 uses a PNP transistor. The signal to be detected at the piezoelectric ceramic load end DET is transmitted to the inverting input end of the comparator U1A, and the comparator U1A compares the voltage of the signal to be detected at the inverting input end with the reference voltage input at the positive input end. When the abnormality of the signal to be detected causes the voltage at the inverting input end to be higher than the reference voltage input at the positive input end, the output end of the comparator U1A outputs a low-level signal, and the external processor issues an alarm after receiving the low-level signal output by the comparator U1A. At the same time, the low-level signal output by the comparator U1A turns on the transistor Q2. After the transistor Q2 is turned on, the voltage at the inverting input end of the comparator U1A will continue to be higher than the positive input end, so that the output end of the comparator U1A always outputs a low-level signal to lock the abnormal signal, prevent the signal from switching back and forth to cause the external processor to misjudge, and reserve sufficient time for the external processor to process the signal. When transistor Q2 maintains the low-level signal and allows the external processor to complete more accurate multiple signal processing, if the external processor determines that the piezoelectric ceramic is temporarily overloaded and the circuit needs to be restored, a high-level signal is output to the base of transistor Q1, causing transistor Q1 to be turned on. After transistor Q1 is turned on, the voltage at the inverting input terminal of comparator U1A will be lower than the reference voltage at the non-inverting input terminal, and the output terminal of comparator U1A will output a high-level signal, thereby restoring the circuit to normal.
[0024] Furthermore, a capacitor C3 is connected to the common terminal of the base of the transistor Q2 and the output terminal of the comparator U1A, and the other end of the capacitor C3 is grounded. The capacitor C3 is a chip capacitor with a capacitance in the range of 1nF-4.7nF. The capacitor C3 can stabilize the circuit, improve the reliability of the circuit operation, reduce noise and interference, improve the quality of the signal, and ensure the accuracy of the detection.
[0025] Furthermore, a current-limiting resistor R1 and a current-limiting resistor R6 are connected between the non-phase input terminal of the comparator U1A and the piezoelectric ceramic load terminal DET, a current-limiting resistor R5 is connected between the inverting input terminal of the comparator U1A and the common connection terminal of the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4, a current-limiting resistor R11 is connected between the output terminal of the comparator U1A and the power supply VCC, a current-limiting resistor R12 is connected between the output terminal of the comparator U1A and the base of the transistor Q2, a current-limiting resistor R7 is connected between the base of the transistor Q1 and the external processor, a discharge resistor R8 is connected to the base of the transistor Q1, and the other end of the discharge resistor R8 is grounded, a current-limiting resistor R9 is connected between the emitter of the transistor Q2 and the power supply VCC, and a third voltage-limiting resistor R10 is connected between the base and the emitter of the transistor Q2. The current limiting resistors R1, R5, R6, R11, and R12 can provide effective current limiting protection for the comparator U1A, and the current limiting resistor R7 can provide current limiting protection for the transistor Q1. The current limiting resistors R1, R5, R6, R7, R11, and R12 can select 1kΩ-5kΩ resistors according to actual conditions; the discharge resistor R8 plays a discharging role, and a 10kΩ resistor can be used; the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4 can select 1kΩ-5kΩ resistors according to actual conditions to provide a suitable reference voltage for the positive input terminal of the comparator U1A; the current limiting resistor R9 can provide current limiting protection for the transistor Q2, and the third voltage-dividing resistor R10 plays a role in the voltage-dividing conduction of the transistor Q2. The current limiting resistor R9 can use a 1kΩ resistor, and the third voltage-dividing resistor R10 can use a 10kΩ resistor.
[0026] This embodiment also provides a piezoelectric ceramic detection system, including a central processing unit and the above-mentioned piezoelectric ceramic detection circuit, wherein the output end of the comparator U1A in the piezoelectric ceramic detection circuit is connected to the signal input end of the central processing unit, and the base of the transistor Q1 in the piezoelectric ceramic detection circuit is connected to the signal control end of the central processing unit. In specific implementation, the piezoelectric ceramic detection circuit can detect abnormalities in the signal at the piezoelectric ceramic end. When it detects an abnormality, the piezoelectric ceramic detection circuit outputs a low-level signal and locks the low-level signal to maintain the central processing unit's multiple sampling and signal analysis of the low-level signal to obtain a more accurate detection result. When the central processing unit determines that the piezoelectric ceramic is temporarily overloaded, the piezoelectric ceramic detection circuit can be controlled to achieve circuit recovery, allowing the piezoelectric ceramic to continue working, preventing the piezoelectric ceramic that could have continued to work from being eliminated due to misjudgment, thereby saving use costs.
[0027] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A piezoelectric ceramic detection circuit, characterized in that: It includes a comparator U1A, a transistor Q1, a transistor Q2, a first voltage-dividing resistor R3 and a second voltage-dividing resistor R4, wherein the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4 are connected in series, and one end of the first voltage-dividing resistor R3 is grounded, and one end of the second voltage-dividing resistor R4 is connected to a power supply VCC, a non-inverting input end of the comparator U1A is connected to the common connection end of the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4, an inverting input end of the comparator U1A is connected to a piezoelectric ceramic load end DET, an output end of the comparator U1A is connected to the base of the transistor Q2 and an external processor, a collector of the transistor Q2 is connected to the inverting input end of the comparator U1A, an emitter of the transistor Q2 is connected to the power supply VCC, a collector of the transistor Q1 is connected to the inverting input end of the comparator U1A, the emitter of the transistor Q1 is grounded, and the base of the transistor Q1 is connected to an external processor.
2. A piezoelectric ceramic detection circuit according to claim 1, characterized in that: The comparator U1A adopts an operational amplifier.
3. A piezoelectric ceramic detection circuit according to claim 1, characterized in that: The transistor Q1 is an NPN transistor, and the transistor Q2 is a PNP transistor.
4. A piezoelectric ceramic detection circuit according to claim 3, characterized in that: A capacitor C3 is connected to the common terminal of the base of the transistor Q2 and the output terminal of the comparator U1A, and the other end of the capacitor C3 is grounded.
5. A piezoelectric ceramic detection circuit according to claim 4, characterized in that: The capacitor C3 is a chip capacitor with a capacitance in the range of 1nF-4.7nF.
6. A piezoelectric ceramic detection circuit according to claim 3, characterized in that: A current limiting resistor R1 and a current limiting resistor R6 are connected between the non-phase input terminal of the comparator U1A and the piezoelectric ceramic load terminal DET, a current limiting resistor R5 is connected between the inverting input terminal of the comparator U1A and the common connection terminal of the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4, a current limiting resistor R11 is connected between the output terminal of the comparator U1A and the power supply VCC, and a current limiting resistor R12 is connected between the output terminal of the comparator U1A and the base of the transistor Q2.
7. The piezoelectric ceramic detection circuit according to claim 3, characterized in that: A current limiting resistor R7 is connected between the base of the transistor Q1 and the external processor, a discharge resistor R8 is connected to the base of the transistor Q1, and the other end of the discharge resistor R8 is grounded, a current limiting resistor R9 is connected between the emitter of the transistor Q2 and the power supply VCC, and a third voltage dividing resistor R10 is connected between the base and emitter of the transistor Q2.
8. A piezoelectric ceramic detection system, characterized in that: It comprises a central processing unit and the piezoelectric ceramic detection circuit described in any one of claims 1 to 7, wherein the output end of the comparator U1A in the piezoelectric ceramic detection circuit is connected to the signal input end of the central processing unit, and the base of the transistor Q1 in the piezoelectric ceramic detection circuit is connected to the signal control end of the central processing unit.