Multi-channel control expansion board based on PowerPC processing chip and FPGA chip

Abstract

The utility model relates to the field of communication technology, and specifically to a multi-channel control expansion board based on a PowerPC processing chip and an FPGA chip, including a main control chip, multiple basic processing modules, and multiple interfaces; the main control chip is used to process sensor data and upload the data to a monitoring terminal; the basic processing module can not only locate the position of a faulty sensor, but also maintain the continuity of signal acquisition, effectively avoiding signal interruption caused by sensor failure; the interface can simultaneously connect multiple sensors, thereby achieving all-round monitoring of the aircraft's operating status. The utility model solves the technical problem of quickly locating the position of a faulty sensor while ensuring the continuity of signal acquisition.

Description

Technical Field

[0001] The utility model relates to the technical field of communication, in particular to a multi-channel control expansion board based on a PowerPC processing chip and an FPGA chip. Background Art

[0002] With the continuous progress of electronic science and technology, the demand for signal acquisition equipment in the aerospace field is growing, and the pursuit of highly integrated and complex signal acquisition equipment has become a key trend in the development of the industry. In order to meet the complex and ever-changing aerospace missions, signal acquisition systems are generally equipped with multi-channel control expansion boards. Although the existing expansion boards can connect multiple sensors, they ignore the huge risks that may be caused by sensor failures, which will pose a potential threat to flight safety.

[0003] The Chinese utility model patent with the name of "A serial port expansion board" and the publication number CN213457827U has been published. The patent includes a control chip, a dial port, and a communication port. While expanding multiple interfaces, the utility model patent can also locate the fault point, reducing the difficulty of troubleshooting. However, for the sensors on the aircraft, the expansion board not only needs to locate the position of the faulty sensor, but also should ensure the normal operation of the signal collection work that the faulty sensor is responsible for, thereby ensuring the safety and stability of the aircraft. Utility Model Content

[0004] The purpose of this application is to provide a multi-channel control expansion board based on a PowerPC processing chip and an FPGA chip, which solves the technical problem of quickly locating the position of a faulty sensor while ensuring the continuity of signal acquisition.

[0005] In order to solve the above technical problems, the solution adopted by this application is as follows:

[0006] The utility model provides a multi-channel control expansion board based on a PowerPC processing chip and an FPGA chip, comprising a main control chip and a plurality of interfaces connected to the main control chip; the utility model is characterized in that: it also comprises a basic processing module, one input end and two input ends of the basic processing module are respectively connected to the interfaces, and the output end of the basic processing module is connected to the input end of the main control chip;

[0007] The basic processing module includes a differential amplifier circuit and a comparison switching circuit; the output end of the differential amplifier circuit is connected to an input end of the comparison switching circuit; an input end of the differential amplifier circuit serves as an input end of the basic processing module, and the second input end of the differential amplifier circuit serves as the second input end of the basic processing module; the output end of the comparison switching circuit serves as the output end of the basic processing module;

[0008] The differential amplifier circuit includes a first-stage differential amplifier circuit and a second-stage differential amplifier circuit, wherein one input end of the first-stage differential amplifier circuit serves as one input end of the differential amplifier circuit, and the second input end of the first-stage differential amplifier circuit serves as the second input end of the differential amplifier circuit; the output end of the first-stage differential amplifier circuit is connected to the input end of the second-stage differential amplifier circuit; the output end of the second-stage differential amplifier circuit serves as the output end of the differential amplifier circuit;

[0009] The comparison switching circuit comprises a comparison circuit, a switching circuit, and a fault indication circuit. An input end of the comparison circuit serves as an input end of the comparison switching circuit, and an output end of the comparison circuit, an input end of the switching circuit, and an input end of the fault indication circuit are connected; two input ends of the switching circuit are connected to an input end of a differential amplifier circuit, and three input ends of the switching circuit are connected to two input ends of the differential amplifier circuit; and an output end of the switching circuit serves as an output end of the comparison switching circuit;

[0010] The switching circuit includes a field effect transistor, two field effect transistors, and a NOT gate. The source of the field effect transistor is set as the second input terminal of the switching circuit, the gate thereof is connected to the negative electrode of the NOT gate, and the drain thereof is connected to the drain of the second field effect transistor; the source of the two field effect transistors is set as the third input terminal of the switching circuit, the gate thereof is connected to the positive electrode of the NOT gate, and the input terminal is set here as the input terminal of the switching circuit.

[0011] In some embodiments, a basic protection circuit is also included, and one input terminal of the differential amplifier circuit is connected to two input terminals of the switching circuit through the basic protection circuit, and the two input terminals of the differential amplifier circuit are connected to three input terminals of the switching circuit through the basic protection circuit.

[0012] In some embodiments, the basic protection circuit includes an isolation circuit and a delay circuit, the input end of the isolation circuit serves as the input end of the basic protection circuit, the output end of the isolation circuit is connected to the input end of the delay circuit, and the output end of the delay circuit serves as the output end of the basic protection circuit.

[0013] In some embodiments, the delay circuit is an RC delay circuit.

[0014] In some embodiments, the output end of the first-stage differential amplifier circuit is connected to a filter capacitor.

[0015] In some embodiments, the switching circuit further includes a limiting resistor, and the limiting resistor is connected in series with the input terminal of the switching circuit.

[0016] In some embodiments, the main control chip includes a PowerPC processing chip and an FPGA chip. The signal input end of the FPGA chip is set as the input end of the main control chip, and the signal transmission end of the FPGA chip is connected to the signal transmission end of the PowerPC processing chip; the signal output end of the PowerPC processing chip is set as the output end of the main control chip.

[0017] In some embodiments, a power module is also included, and the power module is connected to the main control chip and the basic processing module respectively.

[0018] The technical solution of the present application has at least the following advantages and beneficial effects:

[0019] 1. The utility model can not only locate the position of the faulty sensor, but also maintain the continuity of signal acquisition, effectively avoiding signal interruption caused by sensor failure, and ensuring safe monitoring and stable control of the aircraft during flight; the expansion board is provided with multiple interfaces, which can connect multiple sensors at the same time, thereby realizing all-round monitoring of the aircraft's operating status;

[0020] 2. FPGA has the ability of parallel processing and can process multiple tasks or data at the same time; PowerPC is responsible for overall control and management as the main processor; in the present invention, the combined use of PowerPC and FPGA can significantly improve the performance of the expansion board in processing data and adapt to a wide range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a signal flow chart of the utility model;

[0022] Figure 2 This is a differential amplifier circuit diagram of the utility model;

[0023] Figure 3 This is a comparison switching circuit diagram of the utility model;

[0024] Figure 4 This is the basic protection circuit diagram of the utility model. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0026] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. If the terms "center", "upper", "lower", "inner", "outer", etc. indicate an orientation or position relationship based on the orientation or position relationship shown in the figure, or the orientation or position relationship in which the product of the application is usually placed when in use, it is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. It should also be noted that unless otherwise clearly specified and limited, if the terms "set", "install", and "connect" appear, they should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a connection between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0027] Example 1

[0028] Please refer to Figure 1-Figure 4 The utility model provides a multi-channel control expansion board based on PowerPC processing chip and FPGA chip, which is the same as the prior art and includes a main control chip and multiple interfaces connected to the main control chip; different from the prior art, it also includes multiple basic processing modules.

[0029] To facilitate understanding of the basic processing module, this embodiment is described by taking a basic processing module to process two sensors of the same type; for ease of description, a working sensor is called a working sensor, and a sensor used to replace a working sensor is called a standby sensor.

[0030] It should be noted that, in this embodiment, the main control chip includes a PowerPC processing chip and an FPGA chip; the signal input end of the FPGA chip is set to the input end of the main control chip, and the signal transmission end of the FPGA chip is connected to the signal transmission end of the PowerPC processing chip to realize data interaction; the signal output end of the PowerPC processing chip is set to the output end of the main control chip; after the FPGA collects the data from the sensor, the data is transmitted to the PowerPC processing chip, and the PowerPC processing chip processes and analyzes the data, and sends the results to the monitoring end after completion.

[0031] It needs to be explained that FPGA has the ability of parallel processing and can process multiple tasks or data at the same time; PowerPC, as the main processor, is responsible for overall control and management; the combined use of PowerPC and FPGA can significantly improve the performance of the expansion board in processing data and adapt to a wide range of application scenarios.

[0032] In this embodiment, the basic processing module is provided with two input terminals, one input terminal and the second input terminal are respectively connected to the interface, the working sensor and the standby sensor are respectively connected to the one input terminal and the second input terminal of the basic processing module through different interfaces; the output terminal of the basic processing module is connected to the input terminal of the main control chip.

[0033] The basic processing module includes a differential amplifier circuit and a comparison switching circuit;

[0034] The output end of the differential amplifier circuit is connected to an input end of the comparison switching circuit; an input end of the differential amplifier circuit serves as an input end of the basic processing module, and the second input end of the differential amplifier circuit serves as the second input end of the basic processing module; the output end of the comparison switching circuit serves as the output end of the basic processing module;

[0035] The differential amplifier circuit includes a primary differential amplifier circuit and a secondary differential amplifier circuit;

[0036] One input end of the first differential amplifier circuit is used as one input end of the differential amplifier circuit, and the second input end thereof is used as the second input end of the differential amplifier circuit; the output end of the first differential amplifier circuit is connected to the input end of the second differential amplifier circuit; the output end of the second differential amplifier circuit is used as the output end of the differential amplifier circuit;

[0037] Further, such as Figure 2 As shown, the differential amplifier circuit includes operational amplifiers U1 and U2, a filter capacitor C1, and resistors R1, R2, R3, R4, R5, R6, R7, and R8; the filter capacitor C1 functions as a filter;

[0038] Among them, the first-stage differential amplifier circuit includes an operational amplifier U1, resistors R1, R2, R3, and R4; the second-stage differential amplifier circuit includes an operational amplifier U2, resistors R5, R6, R7, and R8;

[0039] Specifically, in the differential amplifier circuit, one end of the resistor R1 is set as the UIN1 input end, and the UIN1 input end is one input end of the differential amplifier circuit; the other end of the resistor R1, one end of the resistor R3, and the pin 2 of the operational amplifier U1 are connected; one end of the resistor R2 is set as the UIN2 input end, and the UIN2 input end is the second input end of the differential amplifier circuit; the other end of the resistor R2, one end of the resistor R4, and the pin 3 of the operational amplifier U1 are connected, and the other end of the resistor R4 is grounded; the pin 8 of the operational amplifier U1 is connected to the power supply, the pin 4 is grounded, the pin 1 of the operational amplifier U1, the other end of the resistor R3, and the filter One end of the filter capacitor C1 and one end of the resistor R5 are connected; the other end of the resistor R5, one end of the resistor R7, and the pin 2 of the operational amplifier U2 are connected; one end of the resistor R6 is connected to the power supply, the other end of the resistor R6, the pin 3 of the operational amplifier U3, and one end of the resistor R8 are connected, and the other end of the resistor R8 is connected to the other end of the filter capacitor C1 and grounded; pin 8 of the operational amplifier U2 is connected to the power supply, pin 4 is grounded, pin 1 of the operational amplifier U2 is connected to the resistor R7, and an output end is set here, which is called the UOUT1 output end, and the UOUT1 output end is the output end of the differential amplifier circuit.

[0040] The comparison switching circuit includes a comparison circuit, a switching circuit, and a fault indication circuit;

[0041] An input end of the comparison circuit is used as an input end of the comparison switching circuit, and an output end of the comparison circuit, an input end of the switching circuit, and an input end of the fault indication circuit are connected; a second input end of the switching circuit is connected to an input end of the differential amplifier circuit, and a third input end of the switching circuit is connected to a second input end of the differential amplifier circuit; an output end of the switching circuit is used as an output end of the comparison switching circuit;

[0042] The switching circuit includes a first-effect transistor, a second field-effect transistor, and a NOT gate. The source of the first-effect transistor is set as the second input terminal of the switching circuit, the gate thereof is connected to the negative electrode of the NOT gate, and the drain thereof is connected to the drain of the second field-effect transistor; the source of the second field-effect transistor is set as the third input terminal of the switching circuit, the gate thereof is connected to the positive electrode of the NOT gate, and the input terminal is set here as the input terminal of the switching circuit;

[0043] The switching circuit also includes a limiting resistor which is connected in series with the input terminal of the switching circuit.

[0044] Further, such as Figure 3 As shown, the comparison switching circuit includes operational amplifiers U3 and U4, diodes D1 and D2, indicator light LED1, resistors R9, R10, R11, R12, R14, R16 and R17, limiting resistor R13, field effect transistors Q1 and Q2, and NOT gate U5; indicator light LED1 is used for fault location to reduce the difficulty of later fault troubleshooting;

[0045] Among them, the comparison circuit includes operational amplifiers U3, U4, diodes D1, D2, resistors R9, R10, R11, R12; the switching circuit includes a limiting resistor R13, resistors R16, R17, field effect transistors Q1, Q2, and a NOT gate U5; the limiting resistor R13 is used to limit the voltage signal output by the switching circuit; the fault indication circuit includes a resistor R14 and an indicator light LED1.

[0046] Specifically, in the comparison switching circuit, pin 3 of the operational amplifier U3 is connected to pin 2 of the operational amplifier U4, and an input terminal is set here, which is called UIN3 input terminal, and the UIN3 input terminal is an input terminal of the comparison switching circuit; one end of the resistor R9 is connected to the power supply, and the other end of the resistor R9, pin 2 of the operational amplifier U3, and one end of the resistor R10 are connected, and the resistor R10 is grounded; one end of the resistor R11 is connected to the power supply, and the other end of the resistor R11, one end of the resistor R12, and pin 3 of the operational amplifier U4 are connected, and the other end of the resistor R12 is grounded; pin 8 of the operational amplifier U3 is connected to the power supply, pin 4 is grounded, and pin 1 of the operational amplifier U3 is connected to the positive electrode of the diode; pin 8 of the operational amplifier U4 is connected to the power supply, pin 4 is grounded, and pin 1 of the operational amplifier U4 is connected to the positive electrode of the diode D2; the cathode of the diode D1, the cathode of the diode D2, and the cathode of the resistor R14 are connected. One end is connected to one end of the limiting resistor R13; the other end of the resistor R14 is connected to the positive electrode of the indicator light LED1, and the negative electrode of the indicator light LED1 is grounded; the other end of the limiting resistor R13, the positive electrode of the NOT gate U5, and one end of the resistor R17 are connected, the other end of the resistor R17 is connected to the gate of the field effect tube Q1, the source of the field effect tube Q1 is set to the input end, which is called the UIN4 input end, and the UIN4 input end is the three input ends of the comparison switching circuit; the negative electrode of the NOT gate U5 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the gate of the field effect tube Q2, the source of the field effect tube Q2 is set to the input end, which is called the UIN5 input end, and the UIN5 input end is the second input end of the comparison switching circuit; the drain of the field effect tube Q1 is connected to the drain of the field effect tube Q2, and an output end is set here, which is called the UIO1 output end, and the UIO1 output end is the output end of the comparison switching circuit.

[0047] In order to facilitate the understanding of the processing module, the workflow of the processing module is now explained:

[0048] The UIN1 input end of the first-stage differential amplifier circuit receives the signal collected by the working sensor through the interface, and the UIN2 input end receives the signal collected by the standby sensor through the interface. The first-stage differential amplifier circuit differentially amplifies the two signals to obtain a difference signal;

[0049] After the secondary differential amplifier circuit differentially amplifies the difference signal, a positive voltage signal is obtained, and the positive voltage signal is transmitted from the UOUT1 output terminal of the secondary differential amplifier circuit to the comparison circuit of the comparison switching circuit;

[0050] The comparison circuit compares the received positive voltage signal. If the positive voltage signal is within the threshold range, it indicates that the working sensor is working normally. The UIN3 input terminal receives the signal collected by the working sensor and transmits it to the FPGA chip from the UIO1 output terminal. If the positive voltage signal is outside the threshold range, it indicates that the working sensor is working abnormally. The comparison circuit sends a control signal to the switching circuit and the fault indication circuit.

[0051] After the switching circuit receives the signal, it switches the data transmission channel and isolates the working sensor. At the same time, the standby sensor starts to take over the working sensor to transmit the collected signal. The UIN4 input end receives the signal collected by the working sensor and transmits it from the UIO1 output end to the FPGA chip. At the same time, the fault indication circuit works to help locate the fault point.

[0052] In this embodiment, two basic protection circuits are also provided. One input terminal of the differential amplifier circuit is connected to two input terminals of the switching circuit through one basic protection circuit, that is, the two input terminals of the differential amplifier circuit are connected to three input terminals of the switching circuit through another basic protection circuit.

[0053] The basic protection circuit includes an isolation circuit and a delay circuit. The input end of the isolation circuit serves as the input end of the basic protection circuit. The output end of the isolation circuit is connected to the input end of the delay circuit. The output end of the delay circuit serves as the output end of the basic protection circuit.

[0054] It needs to be explained that the delay circuit is an RC delay circuit.

[0055] Further, such as Figure 4 As shown, the basic protection circuit includes an operational amplifier U6, a resistor R15, and a capacitor C2; wherein the isolation circuit includes the operational amplifier U6; the RC delay circuit includes the resistor R15 and the capacitor C2; and the RC delay circuit is used for delay.

[0056] Specifically, in the basic protection circuit, pin 3 of the operational amplifier U6 is set as an input terminal, which is called the UIN6 input terminal, and the UIN6 input terminal is the input terminal of the protection circuit. Pin 7 of the operational amplifier U3 is connected to the power supply and pin 4 is grounded. Pin 2 of the operational amplifier U3, pin 6 of the operational amplifier U6, and one end of the resistor R15 are connected. The other end of the resistor R15 is connected to one end of the capacitor C2, and an output terminal is set here, which is called the UIO2 output terminal, and the UIO2 output terminal is the output terminal of the protection circuit; the other end of the capacitor C2 is grounded.

[0057] It needs to be explained that the UIN5 input terminal receives the signal collected by the working sensor, which passes through the isolation circuit and the delay circuit in sequence, and is finally output to the UIN3 input terminal through the UIO2 output terminal; the workflow of the signal collected by the standby sensor in the basic protection circuit is the same as that of the working sensor.

[0058] This embodiment also includes a power module, which is connected to the main control chip and the basic processing module respectively, and is used to provide power to the main control chip and the basic processing module.

[0059] So far, various embodiments of the present invention have been described in detail. In order to avoid obscuring the concept of the present invention, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution of the present invention, and the scope of the present invention is defined by the attached claims.

Claims

1. A multi-channel control expansion board based on a PowerPC processing chip and an FPGA chip, comprising a main control chip and a plurality of interfaces connected to the main control chip; characterized in that: It also includes a plurality of basic processing modules, wherein one input end and two input ends of the basic processing modules are respectively connected to the interface, and the output end of the basic processing module is connected to the input end of the main control chip; The basic processing module includes a differential amplifier circuit and a comparison switching circuit; the output end of the differential amplifier circuit is connected to an input end of the comparison switching circuit; an input end of the differential amplifier circuit serves as an input end of the basic processing module, and the second input end of the differential amplifier circuit serves as the second input end of the basic processing module; the output end of the comparison switching circuit serves as the output end of the basic processing module; The differential amplifier circuit includes a first-stage differential amplifier circuit and a second-stage differential amplifier circuit, wherein one input end of the first-stage differential amplifier circuit serves as one input end of the differential amplifier circuit, and the second input end of the first-stage differential amplifier circuit serves as the second input end of the differential amplifier circuit; the output end of the first-stage differential amplifier circuit is connected to the input end of the second-stage differential amplifier circuit; the output end of the second-stage differential amplifier circuit serves as the output end of the differential amplifier circuit; The comparison switching circuit comprises a comparison circuit, a switching circuit, and a fault indication circuit. An input end of the comparison circuit serves as an input end of the comparison switching circuit, and an output end of the comparison circuit, an input end of the switching circuit, and an input end of the fault indication circuit are connected; two input ends of the switching circuit are connected to an input end of a differential amplifier circuit, and three input ends of the switching circuit are connected to two input ends of the differential amplifier circuit; and an output end of the switching circuit serves as an output end of the comparison switching circuit; The switching circuit includes a field effect transistor, two field effect transistors, and a NOT gate. The source of the field effect transistor is set as the second input terminal of the switching circuit, the gate thereof is connected to the negative electrode of the NOT gate, and the drain thereof is connected to the drain of the second field effect transistor; the source of the two field effect transistors is set as the third input terminal of the switching circuit, the gate thereof is connected to the positive electrode of the NOT gate, and the input terminal is set here as the input terminal of the switching circuit.

2. The multi-channel control expansion board based on PowerPC processing chip and FPGA chip according to claim 1, characterized in that: It also includes a basic protection circuit, through which one input end of the differential amplifier circuit is connected to two input ends of the switching circuit, and through which two input ends of the differential amplifier circuit are connected to three input ends of the switching circuit.

3. The multi-channel control expansion board based on PowerPC processing chip and FPGA chip according to claim 2, characterized in that: The basic protection circuit includes an isolation circuit and a delay circuit. The input end of the isolation circuit serves as the input end of the basic protection circuit. The output end of the isolation circuit is connected to the input end of the delay circuit. The output end of the delay circuit serves as the output end of the basic protection circuit.

4. The multi-channel control expansion board based on PowerPC processing chip and FPGA chip according to claim 3, characterized in that: The delay circuit is an RC delay circuit.

5. The multi-channel control expansion board based on PowerPC processing chip and FPGA chip according to claim 1, characterized in that: The output end of the first-stage differential amplifier circuit is connected with a filter capacitor.

6. The multi-channel control expansion board based on PowerPC processing chip and FPGA chip according to claim 1, characterized in that: The switching circuit further includes a limiting resistor, which is connected in series with the input terminal of the switching circuit.

7. The multi-channel control expansion board based on PowerPC processing chip and FPGA chip according to claim 1, characterized in that: The main control chip includes a PowerPC processing chip and an FPGA chip. The signal input end of the FPGA chip is set as the input end of the main control chip, and the signal transmission end of the FPGA chip is connected to the signal transmission end of the PowerPC processing chip; the signal output end of the PowerPC processing chip is set as the output end of the main control chip.

8. The multi-channel control expansion board based on PowerPC processing chip and FPGA chip according to claim 1, characterized in that: It also includes a power supply module, which is connected to the main control chip and the basic processing module respectively.

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