Element structure and joint assembly

Abstract

The utility model provides an element structure and a joint assembly, the element structure comprises a voltage regulator circuit, and the voltage regulator circuit comprises a first semiconductor tube core which comprises a pulse width modulation (PWM) circuit and is connected to a PWM voltage output node generating pulse voltage output; a series connection of inductors is connected with a parallel connection circuit that includes a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each capacitor-switch assembly includes a respective series connection of a respective capacitor and a respective switch; and each switch in the capacitor-switch assembly is located within the first semiconductor die.

Description

Technical Field

[0001] The embodiment of the utility model relates to a component structure and a joint assembly. Background Art

[0002] A voltage regulator is a semiconductor circuit that generates a constant output voltage. In some cases, a voltage regulator can use a switching circuit and a voltage stabilization circuit to output a voltage lower than the power supply voltage. Utility Model Content

[0003] The present invention provides a component structure including a voltage regulator circuit. The voltage regulator circuit includes: a first semiconductor die including a pulse width modulation (PWM) circuit, the PWM circuit including a first group of field effect transistors located on a first semiconductor substrate and connected to a PWM voltage output node that generates a pulse voltage output; and a series connection and parallel connection circuit of an inductor, the parallel connection circuit including a parallel connection of a capacitor-switch assembly, wherein: a first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each capacitor-switch assembly includes a corresponding series connection of a corresponding capacitor and a corresponding switch; and each switch in the capacitor-switch assembly is located in the first semiconductor die.

[0004] In some embodiments, a second semiconductor die bonded to the first semiconductor die is further included, wherein each capacitor in the capacitor-switch assembly is located in the second semiconductor die. In some embodiments, the first semiconductor die includes a first dielectric material layer, a first metal interconnect structure and a first bonding pad are located in the first dielectric material layer; the second semiconductor die includes a second dielectric material layer, a second metal interconnect structure and a second bonding pad are located in the second dielectric material layer; and the second bonding pad is bonded to a corresponding one of the first bonding pads by metal-to-metal bonding. In some embodiments, the first semiconductor die includes a first dielectric material layer, a first metal interconnect structure and a first bonding pad are located in the first dielectric material layer; and the switch in the capacitor-switch assembly includes a phase change memory (PCM) switch, the PCM switch includes a corresponding phase change memory (PCM) material portion and a heater component configured to heat the PCM material portion. In some embodiments, the first semiconductor die includes a PCM programming transistor, which is configured to control the flow of current through a corresponding heater component in the PCM switch. In some embodiments, the switch in the capacitor-switch assembly includes a second group of field effect transistors located on the first semiconductor substrate and configured to provide an electrical connection or an electrical disconnection between a corresponding pair of first metal interconnect structures in the first semiconductor die. In some embodiments, the first source / drain region of each field effect transistor selected from the second group of field effect transistors is electrically connected to an electrical node of the inductor; and the second source / drain region of each field effect transistor selected from the second group of field effect transistors is electrically connected to an electrical node of a corresponding capacitor in the capacitor-switch assembly. In some embodiments, it also includes: a second group of field effect transistors located on the first semiconductor substrate; and a switch control circuit located on the first semiconductor substrate and configured to control the opening and closing of each switch in the capacitor-switch assembly by applying a gate voltage to the field effect transistor in the second group of field effect transistors. In some embodiments, the switch control circuit is configured to receive a value of a target direct current (DC) output voltage for the voltage regulator circuit; the switch control circuit includes a memory array, the memory array containing a lookup table of the gate voltage values ​​for each value of the target DC output voltage; and the switch control circuit is configured to use the lookup table and the received value of the target DC output voltage to generate the gate voltage for the field effect transistor within the second group of field effect transistors.

[0005] An embodiment of the utility model provides a bonding assembly including: a voltage regulator circuit; a first semiconductor die, including a pulse width modulation (PWM) circuit, the PWM circuit including a first group of field effect transistors located on a first semiconductor substrate and connected to a PWM voltage output node that generates a pulse voltage output; a second semiconductor die containing a capacitor therein and bonded to the first semiconductor die; and a capacitor-switch assembly, each capacitor-switch assembly including a corresponding series connection of a corresponding capacitor and a corresponding switch, wherein: the voltage regulator circuit includes a series connection of an inductor and a parallel connection circuit, and the parallel connection circuit includes a parallel connection of the capacitor-switch assemblies.

[0006] Based on the above, the present invention relates to a component structure and a joint assembly including a voltage regulator circuit, wherein the voltage regulator circuit has a variable output capacitor, which can be changed and programmed as needed based on an external output or a programming parameter that can be provided during the operation of the voltage regulator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 4 is a vertical cross-sectional view of a first semiconductor die after forming a first semiconductor element, a first metal interconnect structure and a first dielectric material layer according to the first embodiment of the present invention.

[0009] Figure 2 is a vertical cross-sectional view of the first semiconductor die after forming a phase change material (PCM) switch according to the first embodiment of the present invention.

[0010] Figure 3 is a perspective view of a PCM switch that can be used in the first structure.

[0011] Figure 4 is a vertical cross-sectional view of the first structure after forming an additional first metal interconnect structure, a first bonding pad, and an additional first dielectric material layer according to the first embodiment of the present invention.

[0012] Figure 5 is a vertical cross-sectional view of the second semiconductor die after forming an inductor and a dielectric material layer on the carrier substrate according to the first embodiment of the present invention.

[0013] Figure 6 is a vertical cross-sectional view of the second semiconductor die after forming an inductor and additional dielectric material layers according to the first embodiment of the present invention.

[0014] Figure 7 is a vertical cross-sectional view of the second semiconductor die after forming a capacitor according to the first embodiment of the present invention.

[0015] Figure 8 It is a vertical cross-sectional view of the second semiconductor die after forming a second metal interconnect structure and a second dielectric material layer according to the first embodiment of the present invention.

[0016] Fig. 9 is a vertical cross-sectional view of the first bonding assembly after bonding the second semiconductor die to the first semiconductor die according to the first embodiment of the present invention.

[0017] Fig.10 is a vertical cross-sectional view of the first bonding assembly after the carrier wafer is removed according to the first embodiment of the present invention.

[0018] Fig.11 is a vertical cross-sectional view of an alternative configuration of a first semiconductor die after forming a first semiconductor element, a first metal interconnect structure, and a first dielectric material layer according to a second embodiment of the present invention.

[0019] Fig.12 is a vertical cross-sectional view of an alternative configuration of the first semiconductor die after forming additional first metal interconnect structures, first bonding pads, and additional first dielectric material layers according to the second embodiment of the present invention.

[0020] Fig.13 is a vertical cross-sectional view of a second bonding assembly after bonding a second semiconductor die to an alternative configuration of a first semiconductor die according to a second embodiment of the present invention.

[0021] Fig.14 is a vertical cross-sectional view of the second bonding assembly after the carrier wafer is removed according to the second embodiment of the present invention.

[0022] Fig.15A It is a general circuit diagram of the voltage regulator circuit of the utility model.

[0023] Fig. 15B is a circuit diagram of a voltage regulator circuit of the present utility model, wherein the switch may include a PCM switch of the first embodiment of the present utility model.

[0024] Fig. 15C is a circuit diagram of a voltage regulator circuit of the present utility model, wherein the switch may include a field effect transistor of the second embodiment of the present utility model.

[0025] Fig.16 It is a diagram showing components of a voltage regulator circuit of the present invention.

[0026] Fig.17 is a flow chart showing general processing steps for manufacturing a component structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse component numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0028] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise expressly stated, elements with the same element number refer to the same element and are assumed to have the same material composition and the same thickness range.

[0029] Various embodiments of the present invention relate to a power circuit, such as a voltage regulator circuit including a bonded assembly of two semiconductor dies. According to one aspect of the present invention, the voltage regulator circuit of the present invention can have a variable output capacitor that can be varied and programmed as needed based on an external output or a programming parameter that can be provided during operation of the voltage regulator circuit.

[0030] A voltage regulator circuit may be used to generate a noise-free and regulated DC supply voltage (which may be referred to as a core voltage and may be provided to logic elements in a logic core of a semiconductor die) from a noisy and unregulated DC supply voltage provided by a printed circuit board (PCB). The voltage regulator circuit uses an inductor, a capacitor, and a switch to regulate a noisy input voltage to a noise-free output voltage. The strength of the output voltage is generally controlled by a duty cycle D of the PCM circuit. A duty cycle refers to the fraction of the duration that a voltage applied to an input node of the PCM circuit is transmitted to an output node during each cycle of the PCM circuit (i.e., one on operation and one off operation). A series connection of an inductor and at least one capacitor may be connected to an output node of the PCM circuit, and an output voltage of the voltage regulator circuit may be provided at a node between the node between the inductor and the at least one capacitor. The ripple current (ΔI o ) is given by:

[0031]

[0032] The smaller capacitance of the at least one capacitor reduces power consumption, while the larger capacitance of the at least one capacitor reduces voltage ripple in the output node. The larger capacitance also delays the switching time from the light load operation mode to the heavy load operation mode.

[0033] The voltage regulator circuit of various embodiments of the present invention may include a plurality of capacitors that may be individually connected and / or disconnected to a regulated voltage output node via switches. Thus, the output capacitance of the voltage regulator circuit may be optimized during operation of the circuit to provide an optimal capacitance level, which depends on the strength of the output voltage and on the power load on the voltage regulator circuit.

[0034] Typically, the optimal output capacitance of a voltage regulator circuit can minimize the ripple current at a target output voltage. In various embodiments of the voltage regulator circuit of the present utility model, the ability to provide a variable output capacitance to the voltage regulator circuit can be provided by a set of switches provided in a first semiconductor die that also includes a pulse width modulation (PWM) circuit. The variable output capacitance of the voltage regulator circuit of this embodiment can provide a wide range for programmable adjustable output voltage, while minimizing ripple current and reducing power consumption by selecting the optimal output capacitance for each selected value of the adjustable output voltage.

[0035] In the voltage regulator circuit of various embodiments, the switch may include a phase change material (PCM) switch or may include a field effect transistor switch. In embodiments using a PCM switch, the PCM switch may be switched between an on state and an off state by passing a suitable programming current to a heater assembly connected to a corresponding phase change material portion within the PCM switch.

[0036] According to one aspect of the present invention, a pulse width modulation circuit and a switch may be formed in a first semiconductor die, and a capacitor and an inductor may be formed in a second semiconductor die. A first semiconductor die array may be provided in a first wafer, and a second semiconductor die array may be provided in a second wafer, and the two wafers may be bonded to each other by wafer-to-wafer bonding, which may use metal-to-metal and optionally dielectric-to-dielectric bonding. Various embodiments of the present invention are now described with reference to the accompanying drawings.

[0037] Figure 1 962, 966, and a first dielectric material layer 965 are formed according to the first embodiment of the present invention. The first semiconductor die 900 may be one of a plurality of semiconductor dies within a two-dimensional periodic array of semiconductor dies formed on a first semiconductor wafer, such as a commercially available single crystal silicon wafer. The first semiconductor wafer may include a first semiconductor substrate 901, which may be a single crystal silicon wafer. It should be understood that only a portion of the first semiconductor die 900 is shown, and the first semiconductor die 900 may include many other semiconductor circuits, which may include logic circuits and / or memory circuits. Therefore, this portion of the first semiconductor die 900 may be incorporated into a larger semiconductor die, including additional semiconductor elements, such as, but not limited to, complementary metal oxide semiconductor (CMOS) elements.

[0038] The illustrated portion of the first semiconductor die 900 includes component members 902 that can be used to provide a voltage regulator circuit according to an embodiment of the present invention. The component members 902 can include field effect transistors 910, each of which includes a corresponding pair of source / drain regions 912, a corresponding semiconductor channel 914, a corresponding gate dielectric 915, a corresponding gate electrode 916, and optionally a corresponding dielectric gate spacer 917. Isolation trenches 907 can also separate and isolate the component members 902.

[0039] According to one aspect of the present invention, the first semiconductor die 900 may include a pulse width modulation (PWM) circuit 920. The PWM circuit 920 may include a first group of field effect transistors 910 located on the first semiconductor substrate 901. The PWM circuit 920 may include a series connection of two field effect transistors 910 with complementary connected gates, that is, one gate turns on the corresponding field effect transistor, and the other gate turns on the other field effect transistor. The operating principle of the PWM circuit 920 is well known in the art. In essence, the output node of the PWM circuit 920 is the middle node where the two source / drain regions of the two field effect transistors are electrically connected, and the output voltage is a square wave of a selected duty cycle D, which is programmable according to the parameters provided to the control circuit, which controls the voltage pattern applied to the two gate electrodes of the PWM circuit 920.

[0040] According to an embodiment of the present invention, the first semiconductor die 900 may include a programming pulse generator circuit 930 that includes a second subset of field effect transistors 910. The programming pulse generator circuit 930 may include PCM programming transistors (which are a subset of the second subset of field effect transistors 910) that are configured to control current flow through a corresponding one of the heater lines in a subsequently formed PCM switch. In other words, some of the field effect transistors 910 in the programming pulse generator circuit 930 are PCM programming transistors.

[0041] The programming pulse generator circuit 930 may include a plurality of output nodes configured to provide two types of programming pulses for a subsequently formed phase change memory (PCM) switch. The two types of programming pulses may include an amorphization programming pulse (off-state inducing pulse) that provides a short duration pulse with an abrupt pulse end mode, such as a duration of less than 1 microsecond, which may result in amorphization of a corresponding phase change material portion in a corresponding PCM switch. The two types of programming pulses may include a crystallization programming pulse (on-state inducing pulse) that provides a longer duration pulse with an optional gradual pulse end mode, such as a duration of more than 1 microsecond with a stepped pulse end, which may result in amorphization of a corresponding phase change material portion in a corresponding PCM switch.

[0042] In addition, the semiconductor die 900 may include a switch control circuit 940 configured to provide circuit operation instructions to actuate various subsequently formed PCM switches. For example, the switch control circuit 940 may provide circuit operation instructions to the programming pulse generator circuit 930 so that the second subset of the field effect transistors 910 provides a selected programming pulse to each of the subsequently formed PCM switches. The switch control circuit 940 may include a control logic circuit 94L and a memory array 94M.

[0043] The duty cycle of the pulse width modulation (PWM) circuit 920 can be determined based on a target output voltage, which can be predetermined or can be changed during operation of the voltage regulator circuit, for example, by instructions from a processor core or from a program. A lookup table in the semiconductor die can include information on the connections and disconnections of each capacitor for each value of the target output voltage. The lookup table can include a preprogrammed array of memory elements (e.g., static random access memory cells or one-time programmable (OTP) memory components). The switch control circuit 940 can provide appropriate control voltages and / or other circuit operation instructions to activate the various switches 980 (see Figure 2 ).

[0044] In one embodiment, the switch control circuit 940 may be located on the first semiconductor substrate 901 and may be configured to control the capacitor-switch assembly (750 (see FIG. 7 )) by applying a gate voltage to the field effect transistor 910 of the second group of field effect transistors 910 in the programming pulse generator circuit 930. Fig.10 ) within each switch 980 (see Figure 2 ) is turned on and off. In one embodiment, the switch control circuit 940 can be configured to receive a value of a target direct current (DC) output voltage of the voltage regulator circuit, and the switch control circuit 940 includes a memory array 94M, and the memory array 94M contains a lookup table of gate voltage values ​​for each value of the target DC output voltage. The switch control circuit 940 can be configured to generate a gate voltage for the field effect transistor 910 in the second group of field effect transistors 910 using the lookup table and the received value of the target DC output voltage.

[0045] The first metal interconnect structure (962, 966) and the first dielectric material layer 965 may be formed on various semiconductor elements formed on the first semiconductor substrate 901. The first metal interconnect structure (962, 966) may include a first metal via structure 962 and a first metal line structure 966. The first dielectric material layer 965 includes interconnect level dielectric (ILD) materials known in the art, including, for example, undoped silicate glass, doped silicate glass, silicon nitride, porous or non-porous organic silicate glass, silicon oxynitride, silicon carbide nitride, dielectric metal oxide, etc. The first metal interconnect structure (962, 966) may be wired to provide necessary functions to each circuit.

[0046] According to one aspect of the present invention, the conductive path provided by the first metal interconnect structure (962, 966) includes a connection for a power input node of the PWM circuit 920, which is connected to a power input from a printed circuit board (not shown) when the first semiconductor die is electrically connected to the printed circuit board.

[0047] The output nodes of the PWM circuit 920 include a PWM voltage output node N_pwmvo that generates a pulse voltage output. Therefore, the output nodes of the first group of field effect transistors 910 are connected to the PWM voltage output node N_pwmvo and can be the same as the PWM voltage output node N_pwmvo. In addition, a subset of the first metal line structure 966 constitutes an output bus metal line structure 966O, which is a regulated output node, namely, a regulated output node N_rvo. Figure 2 and Figure 3 , phase change material (PCM) switches ( 9801 , 9802 , 9803 , 9804 ) may be formed at a metal interconnect level in the first semiconductor die 900 . Figure 2 A portion of a first semiconductor die 900 is shown, Figure 3 A perspective view of a PCM switch 980 is shown, which may be Figure 2 Any one of the PCM switches (9801, 9802, 9803, 9804) shown. The plurality of switches 980 may be configured to connect or disconnect the corresponding capacitors (to be provided at a subsequent process step) of the voltage regulator circuit to or from the output node of the voltage regulator circuit, i.e., the regulated output node N_rvo. In the exemplary example, the PCM switches 980 (9801, 9802, 9803, 9804, collectively referred to as 980) include a first PCM switch 9801, a second PCM switch 9802, a third PCM switch 9803, and a fourth PCM switch 9804.

[0048] Each PCM switch 980 includes a corresponding variable resistance component 984 and a corresponding heater component 982. The variable resistance component 984 includes a phase change memory (PCM) material portion 984P, a first PCM contact electrode 984E1 contacting a first end of the PCM material portion 984P, and a second PCM contact electrode 984E2 contacting a second end of the PCM material portion 984P. The heater component 982 may be located below or above a middle portion of the PCM material portion 984P and is configured to heat the PCM material portion 984P. The heater component 982 may include a stack of a thermally conductive and electrically insulating liner 982I and a heater wire 982H. The thermally conductive and electrically insulating liner 982I may contact a middle portion of the PCM material portion 984P. In one embodiment, the heater component 984 may be embedded in a layer of the first dielectric material layer 965.

[0049] PCM material portion 984P includes phase change memory material. As used herein, "phase change memory material" refers to a material having at least two different phases that provide different resistivities. Phase change memory (PCM) material can be used to store information as a resistivity state of a material, which can be in different resistivity states corresponding to different phases of the material. Different phases may include an amorphous state with a high resistivity and a crystalline state with a low resistivity (i.e., a resistivity lower than that of the amorphous state). Phase change memory materials include, but are not limited to, germanium antimony telluride (GST) compounds such as Ge2Sb2Te5 or GeSb2Te4, germanium antimony compounds, indium germanium telluride compounds, aluminum selenium telluride compounds, indium selenium telluride compounds, and aluminum indium selenium telluride compounds.

[0050] The first PCM contact electrode 984E1 and the second PCM contact electrode 984E2 include a metal material, such as a conductive metal nitride (such as TiN, TaN, WN, MoN, etc.), a conductive metal carbide (such as TiC, TaC, WC, etc.), a single metal (such as Ti, Ta, W, Mo, Co, Ru, Cu, etc.), an intermetallic alloy, or a combination or a stack thereof. The thermally conductive and electrically insulating liner 982I may include, for example, aluminum nitride. The heater wire 982H includes a suitable metal material, such as TiN, TaN, WN, Ti, Ta, W, Mo, etc.

[0051] Reference Figure 4 , additional first metal interconnect structures (962, 966), first bonding pads 988, and additional first dielectric material layers 965 may be formed above the PCM switch 980. The first bonding pads 988 may be formed on the topmost layer of the first dielectric material layer 965, which is referred to herein as a first bonding level dielectric layer (not separately shown). The first bonding pads 988 may include a pair of inductor connection bonding pads 988L, at least one electrical ground bonding pad 988G, and a plurality of capacitor-connection bonding pads 988C.

[0052] Both ends of the heater wire 982H may contact a corresponding one of the first metal interconnect structures (962, 966), which may be a pair of first metal via structures 962 or a pair of first metal line structures 966. Each of the first PCM contact electrode 984E1 and the second PCM contact electrode 984E2 may contact a corresponding one of the first metal interconnect structures (962, 966), which may be a pair of first metal via structures 962 or a pair of first metal line structures 966.

[0053] For each PCM switch 980, one end of each heater line may be connected to electrical ground, while the other end of each heater line may be connected to the output node of the corresponding PCM programming transistor in the programming pulse generator circuit 930. The electrical connections between the heater lines and the PCM programming transistors (which may include a subset of the first metal interconnect structures (962, 966) not shown) are Figure 4 For each PCM switch 980, the contact electrode (eg Figure 3 The first PCM contact electrode 984E1 shown can be electrically connected to the output bus metal line structure 966O (which is a regulated output node, ie, regulated output node N_rvo), while another contact electrode (eg Figure 3 The second PCM contact electrode 984E2 shown can be electrically connected to a corresponding one of the capacitor connection pads 988C. One of the inductor connection pads 988L can be electrically connected to the first metal interconnect structure (962, 966) embodying the PWM voltage output node N_pwmvo. The other of the inductor connection pads 988L is electrically connected to the output bus metal line structure 966O. At least one electrical grounding pad 988G can be electrically connected to the other electrical ground node (one of the connections is schematically shown by a double dotted line).

[0054] Generally, a first semiconductor die 900 is provided, which includes a first semiconductor substrate 901, a pulse width modulation (PWM) circuit 920 including a first set of field effect transistors 910 located on the first semiconductor substrate 901, and a first metal interconnect structure (962, 966) and a first bonding pad 988 located in a first dielectric material layer 965. The PWM circuit 920 includes a PWM voltage output node N_pwmvo that generates a pulse voltage output. A PCM switch 980 can be formed in the first dielectric material layer 965.

[0055] Reference Figure 5 According to the first embodiment of the present invention, a second semiconductor die 700 may be formed on a carrier wafer 701. The second semiconductor die 700 may be one of the semiconductor dies in a two-dimensional periodic array of semiconductor dies formed on the carrier wafer 701. The carrier wafer 701 may be a semiconductor wafer, an insulating material wafer, or a conductive material layer, and may or may not have the same size as the first semiconductor wafer including the first semiconductor substrate 901. It should be understood that only a portion of the second semiconductor die 700 is shown, and the second semiconductor die 700 may include more examples of passive components than those shown in the subsequent drawings of the present invention.

[0056] A dielectric matrix layer, referred to herein as an inductor-level dielectric matrix layer 715, may be formed on the top surface of the carrier wafer 701. The inductor-level dielectric matrix layer 715 may include undoped silicate glass, doped silicate glass, silicon nitride, or any other dielectric material that may be formed with a planar surface over the carrier wafer 701. The thickness of the inductor-level dielectric matrix layer 715 may range from 300 nm to 3,000 nm, although lesser and greater thicknesses may also be used.

[0057] Optionally, at least one recessed area may be formed in the upper portion of the inductor-grade dielectric matrix layer 715, and may be filled with a high permeability material (e.g., iron), the relative permeability of which may be between 1000 and 1000000, for example, from 2,000 to 10,000. Excessive portions of the high permeability material may be removed, for example, by chemical mechanical polishing (CMP) from above the horizontal plane including the top surface of the inductor-grade dielectric matrix layer 715. The remaining portion of the high permeability material constitutes the inductor core structure 725. In one embodiment, the inductor core structure 725 may have a shape of an annular plate.

[0058] A groove having an inductor wiring pattern may be formed in the upper portion of the inductor core structure 725 such that an end of the groove is formed within the upper portion of the inductor-level dielectric matrix layer 715. A dielectric liner (not shown) may be deposited to provide electrical isolation of a conductive material subsequently deposited in the groove from the material of the inductor core structure 725. At least one conductive material, such as a metal barrier material (e.g., TiN, TaN, WN, or MoN) and a highly conductive metal fill material (e.g., Cu, Ag, or Al) may be deposited in the groove, and excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the inductor-level dielectric material layer 715. The remaining portion of the at least one conductive material filling the groove constitutes the inductor 728.

[0059] Although the present invention is described using the configuration of inductor 728, any other type of inductor known in the art may be constructed on carrier wafer 701. The present invention is not limited to any particular type of inductor structure, as long as inductor 728 can be formed on carrier wafer 701.

[0060] Reference Figure 6, a first dielectric cap layer 731 may be deposited over the inductor 728, and an optional high permeability cap structure 735 including a high permeability material (e.g., iron) may be formed over the inductor 728. A cap dielectric matrix layer 733 including a dielectric material may be formed around the high permeability cap structure 735, and a second dielectric cap layer 741 may be deposited over the high permeability cap structure 735 and the cap dielectric matrix layer 733. A planar spacer dielectric layer 743 may be formed over the second dielectric cap layer 741. The planar spacer dielectric layer 743 includes a dielectric material such as silicon oxide or silicon nitride, and may have a thickness ranging from 100 nm to 3,000 nm, although smaller and larger thicknesses may also be used.

[0061] Reference Figure 7 , a capacitor matrix layer 745 may be formed over the planar spacer dielectric layer 743. Depending on the design of the subsequently formed capacitor, the capacitor matrix layer 745 may include an insulating material, a semiconductor material, or a conductive material. The thickness of the capacitor matrix layer 745 may range from 500 nm to 10,000 nm, although smaller and greater thicknesses may also be used.

[0062] The inductor connection via structure 742 can be formed through the capacitor matrix layer 745, for example, by forming a via cavity and filling the via cavity with at least one conductive material. The inductor connection via structure 742 can contact the corresponding end of the inductor 728. In an embodiment where the capacitor matrix layer 745 includes a semiconductor material or a conductive material, an insulating liner (not shown) can be formed around the periphery of each via cavity before forming the inductor connection via structure 742.

[0063] A plurality of capacitors 750 may be formed in or on the capacitor matrix layer 745. In the illustrative example, a deep trench having a depth not exceeding the thickness of the capacitor matrix layer 745 may be formed in the capacitor matrix layer 745, and at least two electrode material layers interleaved with at least one node dielectric layer may be deposited in the deep trench by a corresponding conformal deposition process. The at least two electrode material layers and the at least one node dielectric layer may then be patterned to form a plurality of continuous groups of at least two electrodes and at least one node dielectric. Each continuous group of at least two electrodes and at least one node dielectric constitutes a capacitor 750. In the illustrative example, each capacitor 750 includes a first electrode 752, a node dielectric 754, and a second electrode 756.

[0064] The capacitors 750 may be formed to have the same capacitance value or different capacitance values. In one embodiment, the capacitor 750 may be formed to have a capacitance value that is the product of a unit value of capacitance and a non-negative integer power of 2 (e.g., 1, 2, 4, 8, 16, 32, 64, etc.). In the illustrative example, the capacitor 750 includes a first capacitor 7501 having a capacitance 8 times that of the fourth capacitor 7504, a second capacitor 7502 having a capacitance 4 times that of the fourth capacitor 7504, a third capacitor 7503 having a capacitance 2 times that of the fourth capacitor 7504, and a fourth capacitor 7504.

[0065] Although the present invention is described using deep trench capacitors, each of which includes two electrodes (752, 756) and a node dielectric 754, embodiments using other types of capacitors are clearly contemplated herein. The present invention is not limited to any particular type of capacitor, as long as multiple capacitors can be formed on the carrier wafer 701.

[0066] Reference Figure 8 , a second metal interconnect structure (762, 766) and a second dielectric material layer 765 may be formed on the capacitor 750. The second metal interconnect structure (762, 766) may include a second metal via structure 762 and a second metal line structure 766. The second metal via structure 762 may include an inductor connection metal via structure 762L, a capacitor connection metal via structure 762C, and an electrical grounding metal via structure 762G. The second metal line structure 766 may include an inductor connection metal line structure 766L, a capacitor connection metal line structure 766C, and an electrical grounding metal line structure 766G. The second dielectric material layer 765 includes interconnect level dielectric (ILD) materials known in the art, including, for example, undoped silicate glass, doped silicate glass, silicon nitride, porous or non-porous organic silicate glass, silicon oxynitride, silicon carbide nitride, dielectric metal oxide, etc. A second metal interconnect structure ( 762 , 766 ) may be routed to provide electrical connections to inductor 728 and capacitor 750 .

[0067] The second bonding pads 788 may be formed in the topmost layer of the second dielectric material layer 765, which is referred to herein as a second bonding level dielectric layer (not shown separately). The second bonding pads 788 may include a pair of inductor connection bonding pads 788L, at least one electrically grounded bonding pad 788G, and a plurality of capacitor connection bonding pads 788C. The pattern of the second bonding pads 788 may be a mirror image pattern of the pattern of the first bonding pads 988.

[0068] Generally, a second semiconductor die 700 is provided that includes a capacitor 750 and a second metal interconnect structure (762, 766) in a second dielectric material layer 765 and a second bonding pad 788. The second semiconductor die 700 may additionally include an inductor 728.

[0069] Reference Fig. 9 , the second semiconductor die 700 can be bonded to the first semiconductor die 900. In one embodiment, the two-dimensional array of second semiconductor dies 700 located on the carrier wafer 701 can be bonded to the two-dimensional array of first semiconductor dies 900 sharing the first semiconductor substrate 901 using a wafer-to-wafer bonding process. In one embodiment, the bonding between the second semiconductor die 700 and the first semiconductor die 900 can be achieved by metal-to-metal bonding (e.g., copper-to-copper bonding) between a mating pair of first bonding pads 988 and second bonding pads 788. Optionally, the topmost layer selected from the first dielectric material layer 965 and the topmost layer selected from the second dielectric material layer 765 can be bonded to each other by dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding).

[0070] Capacitor 750, second metal interconnect structure (762, 766), second bonding pad 788, first bonding pad 988, first metal interconnect structure (962, 966), and PCM switch 980 can be arranged so that a series connection of a corresponding one of capacitors 750 and a corresponding one of PCM switches 980 is formed between a regulated output node N_rvo (including an output bus metal line structure 966O in the first semiconductor die 900) and electrical ground (including the first metal interconnect structure (962, 966), the first bonding pad 988, the second bonding pad 788, and a subset of the second metal interconnect structure (762, 766)). For example, the combination of the first PCM switch 9801 and the first capacitor 7501 forms a first series connection; the combination of the second PCM switch 9802 and the second capacitor 7502 forms a second series connection; the combination of the third PCM switch 9803 and the third capacitor 7503 forms a third series connection; the combination of the fourth PCM switch 9804 and the fourth capacitor 7504 forms a fourth series connection.

[0071] A corresponding capacitor 750 is connected in series with each of the corresponding PCM switches 980 to form a capacitor-switch assembly (750, 980). Each capacitor-switch assembly (750, 980) has a first end node that can be connected to the regulated output node N_rvo (including the output bus metal line structure 966O in the first semiconductor die 900), and has a second end node that can be connected to electrical ground. Therefore, the capacitor-switch assemblies (750, 980) are connected to each other in parallel to provide a parallel connection structure including multiple capacitor-switch assemblies (750, 980).

[0072] According to one aspect of the present invention, each capacitor 750 in the capacitor-switch assembly ( 750 , 980 ) is located in the second semiconductor die 700 , and each PCM switch in the capacitor-switch assembly ( 750 , 980 ) is located in the first semiconductor die 900 .

[0073] Typically, the bonded assembly (900, 700) includes a first semiconductor die 900 including a pulse width modulation (PWM) circuit 920 including a first set of field effect transistors 910 located on a first semiconductor substrate 901 and connected to a PWM voltage output node N_pwmvo that generates a pulse voltage output. The bonded assembly (900, 700) includes a second semiconductor die 700 including a capacitor 750 therein and bonded to the first semiconductor die 900. The capacitor-switch assembly (750, 980) is located within the bonded assembly (900, 700). Each capacitor-switch assembly (750, 980) includes a corresponding series connection of a corresponding one of the capacitors 750 and a corresponding switch 980. The voltage regulator circuit includes a series connection SC of an inductor 728 and a parallel connection circuit including a parallel connection of the capacitor-switch assemblies (750, 980).

[0074] In one embodiment, the bonding interface between the second bonding pad 788 and the first bonding pad 988 is located in a bonding plane (which may be a horizontal plane), and one of the second dielectric material layers 765 is bonded to one of the first dielectric material layers 965 via dielectric-to-dielectric bonding.

[0075] In one embodiment, the joint assembly (900, 700) includes a voltage regulator circuit including a series connection of a PWM circuit 920 and an inductor 728 and a parallel connection circuit. The parallel connection circuit includes a parallel connection of capacitor-switch assemblies (750, 980). A first end of the series connection is connected to the PWM voltage output node N_pwmvo, and a second end of the series connection is connected to electrical ground.

[0076] Reference Fig.10 , the carrier wafer 701 may be separated from the bonded assembly including the first semiconductor die 900 and the second semiconductor die 700. The bonded assembly may include a two-dimensional array of the first semiconductor die 900 and a two-dimensional array of the second semiconductor die 700. In this embodiment, a suitable sawing process may be performed to saw the bonded assembly into a plurality of bonded pairs of the corresponding first semiconductor die 900 and the corresponding second semiconductor die 700.

[0077] Reference Fig.11, by forming a transistor switch 981 made of a field effect transistor 910 instead Figure 1 , an alternative embodiment configuration of the first semiconductor die 900 may be derived from the programming pulse generator circuit 930 shown in FIG. Figure 1 The first semiconductor die 900 is shown in FIG. In this embodiment, a transistor switch 981 formed by a field effect transistor 910 can be used to electrically connect or disconnect the corresponding capacitor to a regulated output node subsequently provided in the first semiconductor die 900 .

[0078] As described above, the first semiconductor die 900 includes a pulse width modulation (PWM) circuit 920, and the first set of field effect transistors 910 are located on the first semiconductor substrate 901 and connected to the PWM voltage output node N_pwmvo that generates a pulse voltage output. In an alternative embodiment configuration of the first semiconductor die 900, the transistor switch 981 includes a second set of field effect transistors 910 located on the first semiconductor substrate 901 and configured to provide an electrical connection or electrical disconnection between a corresponding pair of first metal interconnect structures (962, 966) in the first metal interconnect structure (962, 966). In this embodiment, one of the electrical nodes to be connected or disconnected is electrically connected to the first source / drain region in the field effect transistor 910, and the other of the electrical nodes to be connected or disconnected is electrically connected to the second source / drain region in the field effect transistor 910. For example, the transistor switch 981 may include a first transistor switch 9811, a second transistor switch 9812, a third transistor switch 9813, a fourth transistor switch 9814, etc.

[0079] Typically, the switch control circuit 940 may be located on the first semiconductor substrate 901 and may be configured to control the opening and closing of each transistor switch 981 in the capacitor-switch assembly (750, 981) by applying a gate voltage to the field effect transistor 910 in the second group of field effect transistors 910. In one embodiment, the switch control circuit 940 is configured to receive a value of a target direct current (DC) output voltage of the voltage regulator circuit; the switch control circuit 940 includes a memory array 94M, the memory array 94M contains a lookup table of gate voltage values ​​for each value of the target DC output voltage; and the switch control circuit 940 is configured to generate a gate voltage for the field effect transistor 910 in the second group of field effect transistors 910 of the field effect transistor 910 using the lookup table and the received value of the target DC output voltage.

[0080] Reference Fig.12, additional first metal interconnect structures (962, 966), first bonding pads 988, and additional first dielectric material layers 965 may be formed. The first bonding pads 988 may be formed in the topmost layer of the first dielectric material layer 965, which is referred to herein as a first bonding level dielectric layer (not separately shown). The first bonding pads 988 may include a pair of inductor connection bonding pads 988L, at least one electrical ground bonding pad 988G, and a plurality of capacitor-connection bonding pads 988C.

[0081] The conductive path provided by the first metal interconnect structure (962, 966) includes a connection for a power input node of the PWM circuit 920, which is connected to a power input from a printed circuit board (not shown) when the first semiconductor die is electrically connected to the printed circuit board. The output nodes of the PWM circuit 920 include a PWM voltage output node N_pwmvo that generates a pulse voltage output. Therefore, the output node of the first group of field effect transistors 910 is connected to the PWM voltage output node N_pwmvo and can be the same as the PWM voltage output node N_pwmvo. In addition, a subset of the first metal line structure 966 constitutes an output bus metal line structure 966O, which is a regulated output node, namely, a regulated output node N_rvo.

[0082] The first electrical node of each transistor switch 981 can be electrically connected to the output bus metal line structure 966O (which is a regulated output node, i.e., regulated output node N_rvo), and the second electrical node of each transistor switch 981 can be electrically connected to a corresponding one of the capacitor connection pads 988C. Portions of the conductive path that are not explicitly shown are schematically represented by dashed lines. One of the inductor connection pads 988L is electrically connected to the first metal interconnect structure (962, 966) that embodies the PWM voltage output node N_pwmvo. Another of the inductor connection pads 988L is electrically connected to the output bus metal line structure 966O. At least one electrical grounding pad 988G can be electrically connected to other electrical grounding nodes (one of which is schematically shown by a double dotted line).

[0083] Generally, a first semiconductor die 900 is provided, which includes a first semiconductor substrate 901, a pulse width modulation (PWM) circuit 920 including a first set of field effect transistors 910 located on the first semiconductor substrate 901, and a first metal interconnect structure (962, 966) and a first bonding pad 988 located on a first dielectric material layer 965. The PWM circuit 920 includes a PWM voltage output node N_pwmvo that generates a pulse voltage output. A transistor switch 981 can be formed on the first semiconductor substrate 901.

[0084] Reference Fig.13, the second semiconductor die 700 can be bonded to an alternative embodiment configuration of the first semiconductor die 900. Fig. 9 The described processing steps can be used to influence the joining process.

[0085] Capacitor 750, second metal interconnect structure (762, 766), second bonding pad 788, first bonding pad 988, first metal interconnect structure (962, 966), and transistor switch 981 can be arranged so that a series connection of a corresponding one of capacitor 750 and a corresponding one of transistor switch 981 is formed between regulated output node N_rvo (including output bus metal line structure 966O in first semiconductor die 900) and electrical ground (including first metal interconnect structure (962, 966), first bonding pad 988, second bonding pad 788, and a subset of second metal interconnect structure (762, 766)). For example, a combination of first transistor switch 9811 and first capacitor 7501 forms a first series connection; a combination of second transistor switch 9812 and second capacitor 7502 forms a second series connection; a combination of third transistor switch 9813 and third capacitor 7503 forms a third series connection; a combination of fourth transistor switch 9814 and fourth capacitor 7504 forms a fourth series connection.

[0086] The respective capacitors 750 are connected in series with each of the respective transistor switches 981 to form capacitor-switch assemblies (750, 981). Each capacitor-switch assembly (750, 981) has a first end node connectable to the regulated output node N_rvo (comprising the output bus metal line structure 966O in the first semiconductor die 900) and has a second end node connectable to electrical ground. Thus, the capacitor-switch assemblies (750, 981) are connected to each other in parallel to provide a parallel connection structure including a plurality of capacitor-switch assemblies (750, 981).

[0087] According to one aspect of the present invention, each capacitor 750 in the capacitor-switch assembly (750, 981) is located in the second semiconductor die 700, and each transistor switch in the capacitor-switch assembly (750, 981) is located in the first semiconductor die 900.

[0088] Typically, the bonded assembly (900, 700) includes a first semiconductor die 900 including a pulse width modulation (PWM) circuit 920 including a first set of field effect transistors 910 located on a first semiconductor substrate 901 and connected to a PWM voltage output node N_pwmvo that generates a pulse voltage output. The bonded assembly (900, 700) includes a second semiconductor die 700 including a capacitor 750 therein and bonded to the first semiconductor die 900. The capacitor-switch assembly (750, 981) is located within the bonded assembly (900, 700). Each capacitor-switch assembly (750, 981) includes a corresponding series connection of a corresponding one of the capacitors 750 and a corresponding switch 981. The voltage regulator circuit includes a series connection SC in the inductor 728 and a parallel connection circuit, the parallel connection circuit including a parallel connection of the capacitor-switch assemblies (750, 981).

[0089] In one embodiment, the bonding interface between the second bonding pad 788 and the first bonding pad 988 is located in a bonding plane (which may be a horizontal plane), and one of the second dielectric material layers 765 is bonded to one of the first dielectric material layers 965 via dielectric-to-dielectric bonding.

[0090] In one embodiment, the joint assembly (900, 700) includes a voltage regulator circuit, which includes a series connection of a PWM circuit 920 and an inductor 728 and a parallel connection circuit. The parallel connection circuit includes a parallel connection of capacitor-switch assemblies (750, 981). The first end of the series connection is connected to the PWM voltage output node N_pwmvo, and the second end of the series connection is connected to electrical ground.

[0091] Reference Fig.14 , the carrier wafer 701 may be separated from the bonded assembly including the first semiconductor die 900 and the second semiconductor die 700. The bonded assembly may include a two-dimensional array of the first semiconductor die 900 and a two-dimensional array of the second semiconductor die 700. In this embodiment, a suitable sawing process may be performed to saw the bonded assembly into a plurality of bonded pairs of the corresponding first semiconductor die 900 and the corresponding second semiconductor die 700.

[0092] Fig.15A It is a general circuit diagram of the voltage regulator circuit of the utility model. Fig. 15B is a circuit diagram of a voltage regulator circuit according to an embodiment of the present invention, wherein the switch may include a PCM switch 980 (denoted as P1, P2, P3) according to the first embodiment of the present invention. Fig. 15Cis a circuit diagram of a voltage regulator circuit according to an embodiment of the present invention, wherein the switch may include a field effect transistor 910 (denoted as T1, T2, T3) of the second embodiment of the present invention. The capacitor 750 is denoted as C1, C2, C3, and the inductor 728 is denoted as L. Although Figure 15A-Figure 15C The circuit diagram of FIG. 1 shows three capacitor-switch assemblies (CSA1, CSA2, CSA3), but it should be understood that the total number of capacitor-switch assemblies (CSA1, CSA2, CSA3) can be any number greater than 1, such as from 2 to 1,000,000, and / or from 3 to 1,000, and / or from 4 to 256. In addition, the capacitance of each capacitor (C1, C2, C3, etc.) can be a unit capacitance and a corresponding non-negative power of 2.

[0093] generally, Fig.10 or Fig.14 The illustrated bonded assembly (900, 700) includes a voltage regulator circuit including a series connection SC of a PWM circuit 920 and an inductor 728 and a parallel connection circuit PC including a parallel connection of capacitor-switch assemblies (750, 980). Each switch within the capacitor-switch assemblies (750, 980) may be located within the first semiconductor die 900.

[0094] Typically, each capacitor-switch assembly (750, 980) includes a respective series connection of a respective capacitor 750 and a respective switch 980; each switch (980, 981) within the capacitor-switch assembly (750, 980) is located within the first semiconductor die 900; the capacitor 750 may be located in the second semiconductor die 700; and the inductor 728 may be located in the second semiconductor die 700. A first end node of the series connection SC is connected to the PWM voltage output node N_pwmvo; and a second end node of the series connection SC is connected to electrical ground.

[0095] Reference Fig.16 , which shows the components of the voltage regulator circuit of an embodiment of the present invention. The switch control circuit 940 may include various semiconductor components that can provide the functions of determining the target voltage output Vo and the duty cycle D required by the PWM circuit 920, a lookup table and a cache register for retrieving a set of control instructions corresponding to the target voltage output Vo, and a control logic circuit that can generate a set of control voltages to be transmitted to the second subset of field effect transistors 910 (which can be provided in the programming pulse generator circuit 930 or in the transistor switch 980).

[0096] Reference Fig.17, a flow chart illustrates general processing steps for manufacturing a component structure according to an embodiment of the present invention.

[0097] Referring to step 1710 and Figure 1-Figure 4 and Figure 11-Figure 14 , providing a first semiconductor die 900, the first semiconductor die 900 includes a first semiconductor substrate 901, a pulse width modulation (PWM) circuit 920 including a first group of field effect transistors 910 located on the first semiconductor substrate 901, and a first metal interconnect structure (962, 966) and a first bonding pad 988 located in a first dielectric material layer 965, wherein the PWM circuit 920 includes a PWM voltage output node N_pwmvo for generating a pulse voltage output.

[0098] Refer to step 1720 and Figure 5-Figure 8 , a second semiconductor die 700 including a capacitor 750 is provided, and the second semiconductor die 700 also includes a second metal interconnect structure ( 762 , 766 ) and a second bonding pad 788 located in a second dielectric material layer 765 .

[0099] Refer to step 1730 and Fig. 9 , Fig.10 as well as Fig.15A , Fig. 15B , Fig. 15C and Fig.16 , a bonded assembly is formed by bonding the second semiconductor die 700 to the first semiconductor die 900. The bonded assembly includes capacitor-switch assemblies (CAS1, CSA2, CSA3), each capacitor-switch assembly (CAS1, CSA2, CSA3) including a corresponding series connection of a corresponding capacitor 750 and a corresponding switch (980, 981). The bonded assembly includes a voltage regulator circuit, which includes a series connection SC of a PWM circuit and an inductor 728 and a parallel connection circuit, which includes a parallel connection PC of the capacitor-switch assemblies (CAS1, CSA2, CSA3).

[0100] With reference to all the accompanying drawings, according to various embodiments of the present invention, there is provided a component structure including a voltage regulator circuit. The voltage regulator circuit includes: a first semiconductor die 900 including a pulse width modulation (PWM) circuit 920, the PWM circuit 920 including a first group of field effect transistors 910 located on a first semiconductor substrate 901 and connected to a PWM voltage output node N_pwmvo for generating a pulse voltage output; a series connection SC of an inductor 728 and a parallel connection circuit, the parallel connection circuit including a parallel connection SC of a capacitor-switch assembly {750, (980, 981)}, wherein a first end node of the series connection is connected to the PWM voltage output node N_pwmvo; a second end node of the series connection is connected to electrical ground; each capacitor-switch assembly {750, (980, 981)} includes a corresponding series connection of a corresponding capacitor 750 and a corresponding switch (980, 981); and each switch in the capacitor-switch assembly {750, (980, 981)} is located in the first semiconductor die 900.

[0101] In one embodiment, the device structure includes a second semiconductor die 700 bonded to a first semiconductor die 900 , wherein each capacitor 750 within the capacitor-switch assembly { 750 , ( 980 , 981 )} is located within the second semiconductor die 700 .

[0102] In one embodiment, the first semiconductor die 900 includes a first dielectric material layer 965, wherein a first metal interconnect structure (962, 966) and a first bonding pad 988 are located in the first dielectric material layer 965; the second semiconductor die 700 includes a second dielectric material layer 765, wherein a second metal interconnect structure (762, 766) and a second bonding pad 788 are located in the second dielectric material layer 765; the second bonding pad 788 is bonded to a corresponding one of the first bonding pads 988 by metal-to-metal bonding.

[0103] In one embodiment, the bonding interface between the second bonding pad 788 and the first bonding pad 988 is located within a bonding plane; and one of the second dielectric material layers 765 is bonded to one of the first dielectric material layers 965 by dielectric-to-dielectric bonding.

[0104] In one embodiment, the first semiconductor die 900 includes a first dielectric material layer 965, wherein a first metal interconnect structure (962, 966) and a first bonding pad 988 are located in the first dielectric material layer 965; the switch 980 in the capacitor-switch assembly (750, 980) includes a phase change memory (PCM) switch 980, and the PCM switch 980 includes a corresponding phase change memory (PCM) material portion 984P and a heater component 982 configured to heat the PCM material portion 984P. In one embodiment, the first semiconductor die 900 includes a PCM programming transistor, which is configured to control the current flowing through a corresponding one of the heater components in the PCM switch 980.

[0105] In one embodiment, the switch 981 within the capacitor-switch assembly (750, 981) includes a second set of field effect transistors 910 located on the first semiconductor substrate 901 and configured to provide an electrical connection or disconnection between a corresponding pair of first metal interconnect structures (962, 966) within the first semiconductor die 900. In one embodiment, a first source / drain region 912 of each field effect transistor 910 selected from the second set of field effect transistors 910 is electrically connected to an electrical node of the inductor 728; and a second source / drain region 912 of each field effect transistor 910 selected from the second set of field effect transistors 910 is electrically connected to an electrical node of a corresponding capacitor 750 within the capacitor-switch assembly (750, 981).

[0106] In one embodiment, the element structure includes: a second group of field effect transistors 910 located on a first semiconductor substrate 901; and a switch control circuit 940 located on the first semiconductor substrate 901, and configured to control the opening and closing of each switch (980, 981) in the capacitor-switch assembly {750, (980, 981)} by applying a gate voltage to the field effect transistor 910 in the second group of field effect transistors 910.

[0107] In one embodiment, the switch control circuit 940 is configured to receive a value of a target direct current (DC) output voltage for a voltage regulator circuit; the switch control circuit 940 includes a memory array 94M, which includes a lookup table of gate voltage values ​​for each value of the target DC output voltage; and the switch control circuit 940 is configured to use the lookup table and the received value of the target DC output voltage to generate a gate voltage for the field effect transistor 910 within the second group of field effect transistors 910.

[0108] According to one aspect of the utility model, a bonding assembly (900, 700) including a voltage regulator circuit is provided. The bonding assembly (900, 700) includes a first semiconductor die 900, the first semiconductor die 900 includes a pulse width modulation (PWM) circuit 920, the PWM circuit 920 includes a first group of field effect transistors 910 located on a first semiconductor substrate 901 and connected to a PWM voltage output node N_pwmvo that generates a pulse voltage output. The bonding assembly (900, 700) includes a second semiconductor die 700, the second semiconductor die 700 includes a capacitor 750 therein and is bonded to the first semiconductor die 900. The capacitor-switch assembly {750, (980, 981)} is located in the bonding assembly (900, 700), and each capacitor-switch assembly {750, (980, 981)} includes a corresponding series connection of a corresponding capacitor 750 and a corresponding switch (980, 981). The voltage regulator circuit includes a series connection SC of an inductor 728 and a parallel connection circuit including a parallel connection PC of capacitor-switch assemblies {750, (980, 981)}.

[0109] In one embodiment, each switch within the capacitor-switch assembly {750, (980, 981)} is located within the first semiconductor die 900.

[0110] In one embodiment, the first semiconductor die 900 includes a first dielectric material layer 965, wherein a first metal interconnect structure (962, 966) and a first bonding pad 988 are located in the first dielectric material layer 965; the switch 980 within the capacitor-switch assembly (750, 980) includes a phase change memory (PCM) switch 980, and the PCM switch 980 includes a corresponding phase change memory (PCM) material portion 984P and a heater component 982 configured to heat the PCM material portion 984P.

[0111] In one embodiment, the switch 981 within the capacitor-switch assembly (750, 981) includes a second set of field effect transistors 910 located on the first semiconductor substrate 901 and configured to provide an electrical connection or an electrical disconnection between a corresponding pair of first metal interconnect structures (962, 966) within the first semiconductor die 900.

[0112] In one embodiment, a second group of field effect transistors 910 are located on a first semiconductor substrate 901; and a switch control circuit 940 is located on the first semiconductor substrate 901 and is configured to control the opening and closing of each switch (980, 981) in the capacitor-switch assembly {750, (980, 981)} by applying a gate voltage to the field effect transistor 910 in the second group of field effect transistors 910; the switch control circuit 940 is configured to receive a value of a target direct current (DC) output voltage for a voltage regulator circuit; the switch control circuit 940 includes a memory array 94M, the memory array 94M containing a lookup table of gate voltage values ​​for each value of the target DC output voltage; and the switch control circuit 940 is configured to use the lookup table and the received value of the target DC output voltage to generate a gate voltage for the field effect transistor 910 in the second group of field effect transistors 910.

[0113] Various embodiments of the present invention can be used to provide a voltage regulator circuit with a programmable output capacitor, which can be advantageously used to maintain voltage fluctuations in the regulated output voltage within a predetermined specification range while minimizing power consumption at each setting of the target output voltage. The target output voltage can be changed during operation by instructions from an operating program or by other hardware-induced instructions.

[0114] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present invention, and various modifications, substitutions, and changes can be made to the present invention without departing from the spirit and scope of the present invention.

Claims

1. A component structure, comprising a voltage regulator circuit, characterized in that: The voltage regulator circuit comprises: The first semiconductor die includes a pulse width modulation circuit comprising a first set of field effect transistors located on the first semiconductor substrate and connected to a pulse width modulation voltage output node that generates a pulse voltage output; and a series connection of inductors and a parallel connection circuit, the parallel connection circuit comprising a parallel connection of capacitor-switch assemblies, in: The first end node of the series connection is connected to the pulse width modulated voltage output node; A second end node of the series connection is connected to electrical ground; Each capacitor-switch assembly comprises a respective series connection of a respective capacitor and a respective switch; and Each switch within the capacitor-switch assembly is located within the first semiconductor die.

2. The element structure according to claim 1, characterized in that: Also included is a second semiconductor die bonded to the first semiconductor die, wherein each capacitor within the capacitor-switch assembly is located within the second semiconductor die.

3. The device structure according to claim 2, characterized in that: The first semiconductor die includes a first dielectric material layer, a first metal interconnect structure and a first bonding pad are located in the first dielectric material layer; The second semiconductor die includes a second dielectric material layer, a second metal interconnect structure and a second bonding pad are located in the second dielectric material layer; and The second bonding pad is bonded to a corresponding one of the first bonding pads by metal-to-metal bonding.

4. The device structure according to claim 1, characterized in that: The first semiconductor die includes a first dielectric material layer, a first metal interconnect structure and a first bonding pad are located in the first dielectric material layer; and The switches within the capacitor-switch assembly include phase change memory switches including respective phase change memory material portions and a heater assembly configured to heat the phase change memory material portions.

5. The element structure according to claim 4, characterized in that: The first semiconductor die includes a phase change memory programming transistor configured to control current flow through a corresponding heater component in the phase change memory switch.

6. The element structure according to claim 1, characterized in that: The switches within the capacitor-switch assembly include a second set of field effect transistors located on the first semiconductor substrate and configured to provide an electrical connection or disconnection between a corresponding pair of first metal interconnect structures within the first semiconductor die.

7. The device structure according to claim 6, characterized in that: a first source / drain region of each field effect transistor selected from the second group of field effect transistors is electrically connected to an electrical node of the inductor; and A second source / drain region of each field effect transistor selected from the second group of field effect transistors is electrically connected to an electrical node of a corresponding capacitor in the capacitor-switch assembly.

8. The element structure according to claim 1, characterized in that: Also includes: A second group of field effect transistors is located on the first semiconductor substrate; as well as The switch control circuit is located on the first semiconductor substrate and is configured to control the opening and closing of each switch in the capacitor-switch assembly by applying a gate voltage to the field effect transistors in the second group of field effect transistors.

9. The device structure according to claim 8, characterized in that: The switch control circuit is configured to receive a value of a target DC output voltage for the voltage regulator circuit; The switch control circuit includes a memory array containing a lookup table of values ​​of the gate voltage for each value of the target DC output voltage; and The switch control circuit is configured to generate the gate voltage for the field effect transistor within the second group of field effect transistors using the lookup table and the received value of the target DC output voltage.

10. A joint assembly, characterized in that: include: Voltage regulator circuit; A first semiconductor die including a pulse width modulation circuit, the pulse width modulation circuit including a first set of field effect transistors located on a first semiconductor substrate and connected to a pulse width modulation voltage output node that generates a pulse voltage output; a second semiconductor die including a capacitor therein and bonded to the first semiconductor die; as well as Capacitor-switch assemblies, each capacitor-switch assembly comprising a respective series connection of a respective capacitor and a respective switch, wherein: The voltage regulator circuit includes a series connection of inductors and a parallel connection circuit, the parallel connection circuit including a parallel connection of the capacitor-switch assemblies.

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