SiC device capable of reducing conduction loss

Abstract

The utility model discloses a SiC device for reducing conduction loss, and relates to the technical field of semiconductors. The isolation dielectric layer covers the top surface of the gate Poly layer and extends downwards to be connected with the N + region; the middle part of the top surface of the silicon carbide Drift layer is provided with a source Poly layer, and the side part of the source Poly layer is provided with an ohmic contact alloy layer which is separated from the source Poly layer and is connected with the isolation dielectric layer; and an oxide dielectric layer extending upwards is arranged between the source Poly layer and the ohmic contact alloy layer. And the bottom of the ohmic contact alloy layer is in contact with the N + region and the P + region in the silicon carbide Drift layer, so that the P-base region, the N + region and the P + region have the same potential, and the voltage endurance capability of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC device with reduced conduction loss. Background Art

[0002] The higher thermal conductivity of silicon carbide (SiC) materials determines its high current density characteristics, and the higher bandgap width determines the high breakdown field strength and high operating temperature of SiC devices. In the future, SiC power devices will become the first choice for high-voltage, high-frequency and high-efficiency applications. Especially in the development and application of SiC MOSFET, compared with Si MOSFET and Si IGBT of the same power level, SiC MOSFET has greatly reduced on-resistance and switching loss, higher operating frequency, and its high-temperature operating characteristics have greatly improved high-temperature stability.

[0003] The body diode characteristics of SiC MOSFET lead to the bipolar degradation effect of the device, which increases the application risk of the device. At present, the industry's SiCMOSFET usually adopts the method of integrating Schottky diode (SBD) in the device to suppress the opening of the parasitic PN junction body diode to avoid the occurrence of bipolar degradation effect. In addition to the method of integrating SBD on SiC MOSFET by metal, the use of other heterojunctions to form diodes in SiCMOSFET is also one of the feasible methods. Heterojunctions have a wider choice of materials based on electrical parameters such as band gap, dielectric constant, electron affinity, and conductivity type, so they are gradually gaining attention.

[0004] In the existing patent literature, for example, the application published on June 30, 2023, “A SiC VDMOSFET device with integrated HJD and its preparation method”, application number 202310312836.4, includes: metallized drain, N+ substrate layer, N-epitaxial layer, P-base region, P+ injection region, N+ injection region, N-doped region, P+ polysilicon region, gate dielectric layer, N+ polysilicon gate and metallized source. Among them, the depths of the P-base region, the P+ injection region and the N-doped region are the same, the contact interface between the source and the P+ injection region, the N+ injection region and the P+ polysilicon region is an ohmic contact, and the interface between the P+ polysilicon region and the N-doped region is a heterojunction contact. Although the heterojunction diode structure is integrated into the device to improve the utilization rate of the cell area and reduce the gate capacitance, turn-on time and switching loss of the device, in actual use, the contact resistance between the source and the N+ injection area of ​​the device increases, thereby increasing the conduction loss of the device and affecting the overall performance of the device; at the same time, the reverse voltage resistance performance will also be reduced, thus affecting the long-term reliability of the device. Utility Model Content

[0005] The utility model designs a SiC device which turns on a heterojunction diode first during the device freewheeling process, thereby avoiding the bipolar degradation effect of SiC MOSFET and reducing the conduction loss with small freewheeling loss.

[0006] The technical solution of the utility model is:

[0007] Reduce the conduction loss of SiC devices, including the following from bottom to top:

[0008] Silicon carbide Sub layer;

[0009] The silicon carbide drift layer has a top surface provided with a P-base region extending downward; the top surface of the P-base region has an N+ region and a P+ region extending downward; the N+ region is connected to the P+ region; the bottom surface of the N+ region and the bottom surface of the P+ region are respectively spaced apart from the bottom surface of the P-base region;

[0010] A gate oxide layer is arranged on the top surface of the silicon carbide drift layer, extends from the edge of the device toward the center, and is connected to the P-base region and the N+ region respectively;

[0011] A gate Poly layer, arranged on the top surface of the gate oxide layer;

[0012] An isolation dielectric layer covers the top surface of the gate Poly layer and extends downward to connect with the N+ region; a source Poly layer is provided in the middle of the top surface of the silicon carbide Drift layer, and an ohmic contact alloy layer is provided on the side of the source Poly layer, which is spaced apart from the source Poly layer and connected with the isolation dielectric layer; an oxide dielectric layer extending upward is provided between the source Poly layer and the ohmic contact alloy layer;

[0013] The front electrode metal layer covers the isolation dielectric layer, the ohmic contact alloy layer, the oxide dielectric layer and the source level Poly layer.

[0014] Specifically, the bottom of the source-level Poly layer contacts the silicon carbide Drift layer to form a heterojunction body diode of the device.

[0015] Specifically, the bottom of the ohmic contact alloy layer contacts the N+ region and the P+ region in the silicon carbide Drift layer, making the P-base region, the N+ region and the P+ region have the same potential, thereby improving the withstand voltage capability of the device.

[0016] Specifically, the top surface of the oxide dielectric layer is located on the top surfaces of the source-level Poly layer and the ohmic contact alloy layer respectively.

[0017] Specifically, two sides of the oxide dielectric layer are placed on the source level Poly layer and the ohmic contact alloy layer.

[0018] Specifically, the bottom of the front electrode metal layer is connected to the source-level Poly layer and the ohmic contact alloy layer to form the source electrode of the device.

[0019] Specifically, the ohmic contact alloy layer is a nickel (Ni) ohmic contact alloy layer.

[0020] The utility model integrates a heterojunction diode in a SiC MOSFET device, avoiding the use of the original PN junction body diode as a current path during the freewheeling process of the SiC MOSFET, reducing the holes in the P region entering the drift layer to cause the recombination of holes and electrons, thereby causing the bipolar degradation effect. In addition, since the barrier height of the heterojunction can be adjusted by the doping concentration and interface charge of the material, and the conventional Schottky diode is greatly affected by the image force reduction effect and tunneling current, the heterojunction diode can obtain a higher conduction capability than the conventional SBD, and bring less loss during the freewheeling process of the SiC MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0022] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0023] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0024] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0025] Figure 5 It is a schematic diagram of the structure of step S500 of the utility model;

[0026] Figure 6 It is a structural schematic diagram of step S600 of the utility model;

[0027] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0028] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0029] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0030] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0031] Fig.11 It is a structural schematic diagram of step S1100 of the utility model;

[0032] In the figure, 1 is the silicon carbide Sub layer, 2 is the silicon carbide Drift layer, 3 is the P-base region, 4 is the N+ region, 5 is the P+ region, 6 is the gate oxide layer, 7 is the gate Poly layer, 8 is the isolation dielectric layer, 9 is the source Poly layer, 10 is the ohmic contact alloy layer, 11 is the oxide dielectric layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0033] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0034] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0035] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] A method for preparing a SiC device with reduced conduction loss comprises the following steps:

[0037] S100, refer to Figure 1 As shown, a silicon carbide drift layer 2 is epitaxially grown on the silicon carbide sub layer 1;

[0038] In this case, the conductivity types of the silicon carbide Sub layer 1 and the silicon carbide Drift layer 2 are both N-type.

[0039] S200, refer to Figure 2 As shown, a P-base region 3 is formed on the silicon carbide Drift layer 2 by Al ion implantation;

[0040] In step S200, the P-base region 3 has an N+ region 4 and a P+ region 5. To ensure the normal start-up of the device, the concentration range of the P-base region 3 is 1E17cm -2 -1E18cm -2 .

[0041] S300, refer to Figure 3 As shown, an N+ region 4 is formed on the P-base region 3 by N ion implantation;

[0042] S400, refer to Figure 4 As shown, a P+ region 5 connected to the N+ region 4 is formed on the P-base region 3 by Al ion implantation;

[0043] The N+ region 4 and the P+ region 5 are connected and in contact with each other to ensure the voltage resistance of the device during the reverse blocking process.

[0044] S500, refer to Figure 5 As shown, a gate oxide layer 6 is grown on the silicon carbide drift layer 2 by dry oxygen oxidation;

[0045] S600, refer to Figure 6 As shown, a layer of polysilicon is formed on the gate oxide layer 6 by deposition to form a gate Poly layer 7;

[0046] S700, reference Figure 7 As shown, an isolation dielectric layer 8 connected to the gate Poly layer 7, the gate oxide layer 6 and the N+ region 4 is formed by deposition on the gate Poly layer 7;

[0047] S800, reference Figure 8 As shown, a layer of P-type polysilicon is deposited again on the silicon carbide Drift layer 2 to form a source-level Poly layer 9;

[0048] The bottom of the source-level Poly layer 9 in step S800 is only in contact with the silicon carbide Drift layer 2 , forming a heterojunction diode of the device.

[0049] S900, refer to Fig. 9 As shown, an ohmic contact metal layer is formed on the silicon carbide Drift layer 2 by metal sputtering, and an ohmic contact alloy layer 10 is formed by annealing;

[0050] The bottom of the ohmic contact alloy layer 10 in step S900 contacts the N+ region 4 and the P+ region 5 in the silicon carbide drift layer 2, making the P-base region 3, the N+ region 4 and the P+ region 5 at the same potential, thereby improving the device's withstand voltage capability.

[0051] In this case, the ohmic contact metal layer is made on the top surface of the P+ region and the N+ region, which has the following advantages:

[0052] 1. Reduce the contact resistance between the source metal and the injection region, and reduce the conduction loss of the device.

[0053] 2. The ohmic contact alloy layer makes the P-base area, P+ area and N+ area have the same potential, thereby increasing the reverse voltage resistance performance of the device during the blocking process and improving the long-term reliability of the device.

[0054] 3. The device's surge current resistance capability is increased. Since an ohmic contact alloy layer is made on the top surface of the P+ region, the P+ region will also be opened as a leakage path when a large current impact occurs.

[0055] S1000, refer to Fig.10 As shown, an oxide dielectric layer 11 is formed by deposition between the source level Poly layer 9 and the ohmic contact alloy layer 10;

[0056] The oxide dielectric layer 11 of step S1000 overlaps on both sides on the source level Poly layer 9 and the ohmic contact alloy layer 10 to avoid incomplete deposition of the oxide dielectric layer 11 and formation of holes between the source level Poly layer 9 and the ohmic contact alloy layer 10. The overlapping distance is not set and is adjusted according to actual process conditions.

[0057] S1100, reference Fig.11 As shown, a front electrode metal layer 12 is formed on the device by metal sputtering.

[0058] In step S1100 , the bottom of the front electrode metal layer 12 is connected to the source-level Poly layer 9 and the ohmic contact alloy layer 10 to form the source electrode of the device.

[0059] Reduce the conduction loss of SiC devices, including the following from bottom to top:

[0060] Silicon carbide Sub layer 1;

[0061] A silicon carbide drift layer 2, a top surface of which is provided with a P-base region 3 extending downward; a top surface of the P-base region 3 is provided with an N+ region 4 and a P+ region 5 extending downward; the N+ region 4 is connected to the P+ region 5;

[0062] A gate oxide layer 6 is disposed on the top surface of the silicon carbide drift layer 2, extends from the edge of the device toward the center, and is connected to the P-base region 3 and the N+ region 4 respectively;

[0063] A gate Poly layer 7 is arranged on the top surface of the gate oxide layer 6;

[0064] An isolation dielectric layer 8 is covered on the top surface of the gate Poly layer 7 and extends downward to connect with the N+ region 4; a source Poly layer 9 is provided in the middle of the top surface of the silicon carbide Drift layer 2, and an ohmic contact alloy layer 10 is provided on the side of the source Poly layer 9 and is spaced from the source Poly layer 9 and connected with the isolation dielectric layer 8; an oxide dielectric layer 11 extending upward is provided between the source Poly layer 9 and the ohmic contact alloy layer 10;

[0065] The front electrode metal layer 12 covers the isolation dielectric layer 8 , the ohmic contact alloy layer 10 , the oxide dielectric layer 11 and the source level Poly layer 9 .

[0066] Beneficial effects of the utility model:

[0067] 1. Avoid the bipolar degradation effect of the device and reduce the device freewheeling loss: There is a PN junction body diode inside the conventional SiC MOSFET. During the freewheeling process of the device, the PN junction body diode will be turned on as a current path. Although this body diode protects the SiC MOSFET device, it will also easily cause the holes in the P region to enter the drift layer, resulting in the recombination of holes and electrons in the drift layer, causing the lattice defects in the material to spread and cause the bipolar degradation effect, which deteriorates the performance of the device. This utility model patent uses a heterojunction diode between P-type polysilicon and the drift layer to form a structure similar to a Schottky diode. Since the barrier height of polysilicon as a heterojunction can be adjusted by the doping concentration and interface charge of the material, it can achieve a lower conduction voltage drop than a conventional Schottky diode. During the freewheeling process of the MOSFET, the heterojunction diode is turned on first as a current path, thereby avoiding the bipolar degradation effect of the device and reducing the loss of the device during the freewheeling process.

Claims

1. Reduce conduction loss SiC device, characterized in that: Including setting from bottom to top: Silicon carbide Sub layer (1); A silicon carbide drift layer (2) is provided with a P-base region (3) extending downward on its top surface; an N+ region (4) and a P+ region (5) extending downward on the top surface of the P-base region (3); the N+ region (4) is connected to the P+ region (5); and a gap is provided between the bottom surface of the N+ region (4) and the bottom surface of the P+ region (5) and the bottom surface of the P-base region (3); A gate oxide layer (6) is arranged on the top surface of the silicon carbide drift layer (2), extends from the edge of the device toward the center, and is respectively connected to the P-base region (3) and the N+ region (4); A gate Poly layer (7) is arranged on the top surface of the gate oxide layer (6); an isolation dielectric layer (8) covering the top surface of the gate Poly layer (7) and extending downward to be connected to the N+ region (4); a source Poly layer (9) is provided in the middle of the top surface of the silicon carbide Drift layer (2); an ohmic contact alloy layer (10) is provided on the side of the source Poly layer (9) and is spaced apart from the source Poly layer and connected to the isolation dielectric layer (8); an oxide dielectric layer (11) extending upward is provided between the source Poly layer (9) and the ohmic contact alloy layer (10); The front electrode metal layer (12) covers the isolation dielectric layer (8), the ohmic contact alloy layer (10), the oxide dielectric layer (11) and the source-level Poly layer (9).

2. The SiC device with reduced conduction loss according to claim 1, characterized in that: The bottom of the source-level Poly layer (9) contacts the silicon carbide Drift layer (2) to form a heterojunction diode of the device.

3. The SiC device with reduced conduction loss according to claim 1, characterized in that: The bottom of the ohmic contact alloy layer (10) contacts the N+ region (4) and the P+ region (5) in the silicon carbide drift layer (2), so that the P-base region (3), the N+ region (4) and the P+ region (5) have the same potential, thereby improving the withstand voltage capability of the device.

4. The SiC device with reduced conduction loss according to claim 1, characterized in that: The top surface of the oxide dielectric layer (11) is respectively located on the top surfaces of the source-level Poly layer (9) and the ohmic contact alloy layer (10).

5. The SiC device with reduced conduction loss according to claim 1, characterized in that: The oxide dielectric layer (11) is overlapped on both sides of the source-level Poly layer (9) and the ohmic contact alloy layer (10).

6. The SiC device with reduced conduction loss according to claim 1, characterized in that: The bottom of the front electrode metal layer (12) is connected to the source-level Poly layer (9) and the ohmic contact alloy layer (10) to form a source electrode of the device.

7. The SiC device with reduced conduction loss according to claim 1, characterized in that: The ohmic contact alloy layer (10) is a nickel (Ni) ohmic contact alloy layer.

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