Pixel driving circuit and display device

Abstract

The utility model discloses a pixel driving circuit and a display device. The pixel driving circuit comprises a storage sub-circuit, a first control sub-circuit and a second control sub-circuit, the first control sub-circuit is electrically connected with the at least one reset signal line, the first node and the third node, and is configured to connect the first node with the third node under the control of the at least one reset signal line; the second control sub-circuit is electrically connected with a fourth reset signal line, a first power line and a fifth node, and is configured to provide a signal of the first power line to the fifth node on the basis of the fourth reset signal line; and the storage sub-circuit is electrically connected with the first node, the second node and the fifth node respectively and is configured to store voltage differences of signals among the first node, the second node and the fifth node.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a pixel driving circuit and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Utility Model Content

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a driving subcircuit, a light emitting control subcircuit, a storage subcircuit, a first control subcircuit, and a second control subcircuit;

[0005] A driving subcircuit, electrically connected to the first node, the second node and the third node respectively, and configured to provide a driving signal to the third node under the control of signals of the first node and the second node;

[0006] a light-emitting control subcircuit, electrically connected to at least one light-emitting signal line, and configured to output a driving signal under the control of a signal of at least one light-emitting signal line;

[0007] A first control subcircuit is electrically connected to at least one reset signal line, the first node and the third node respectively, and is configured to connect the first node and the third node under the control of the at least one reset signal line;

[0008] A second control subcircuit is electrically connected to the fourth reset signal line, the first power line and the fifth node respectively, and is configured to provide a signal of the first power line to the fifth node based on the fourth reset signal line;

[0009] The storage sub-circuit is electrically connected to the first node, the second node and the fifth node, respectively, and is configured to store a voltage difference of a signal between the first node, the second node and the fifth node.

[0010] In an exemplary embodiment, the storage subcircuit includes: a first capacitor and a second capacitor;

[0011] The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the second node;

[0012] The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the first node.

[0013] In an exemplary embodiment, the second control subcircuit includes: an eighth transistor;

[0014] A control electrode of the fourth transistor is electrically connected to the scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node;

[0015] A control electrode of the fifth transistor is electrically connected to the fourth reset signal line, a first electrode of the fifth transistor is electrically connected to the first power line, and a second electrode of the fifth transistor is electrically connected to the fifth node.

[0016] In an exemplary embodiment, the first control subcircuit is also electrically connected to the reference signal line, the second node and the first initial signal line, and is configured to provide the signal of the reference signal line to the second node and provide the signal of the first initial signal line to the first node or the third node under the control of the signal of at least one reset signal line.

[0017] In an exemplary embodiment, the at least one reset signal line includes: at least one of a first reset signal line, a second reset signal line, and a third reset signal line;

[0018] The first control subcircuit includes: a first transistor, a second transistor and a ninth transistor;

[0019] The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to one of the first node and the third node;

[0020] The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node;

[0021] The control electrode of the ninth transistor is electrically connected to the second reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

[0022] In an exemplary embodiment, the second reset signal line and the third reset signal line are different signal lines, or are the same signal line.

[0023] In an exemplary embodiment, further comprising: a third control subcircuit;

[0024] The third control subcircuit is electrically connected to the fifth reset signal line, the second initial signal line and the fourth node respectively, and is configured to provide the signal of the second initial signal line to the fourth node under the control of the signal of the fifth reset signal line;

[0025] The fifth reset signal line is the same signal line as one of the second reset signal line and the fourth reset signal line.

[0026] In an exemplary embodiment, it further includes: a writing subcircuit; the writing subcircuit is electrically connected to the scan signal line, the data signal line, and the second node, respectively, and is configured to provide a signal of the data signal line to the second node under the control of a signal of the scan signal line;

[0027] The light emitting control subcircuit is also electrically connected to the first power line, the second node, the third node and the fifth node; at least one light emitting signal line includes: a first light emitting signal line, the driving subcircuit includes: a third transistor, the writing subcircuit includes: a fourth transistor, and the light emitting control subcircuit includes: a fifth transistor and a sixth transistor;

[0028] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0029] A control electrode of the fourth transistor is electrically connected to the scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node;

[0030] The control electrode of the fifth transistor is electrically connected to the first light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node;

[0031] The control electrode of the sixth transistor is electrically connected to the first light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0032] In an exemplary embodiment, the at least one reset signal line includes: at least one of a first reset signal line and a third reset signal line;

[0033] The first control subcircuit includes: a first transistor and a second transistor;

[0034] The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to one of the first node and the third node;

[0035] The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0036] In an exemplary embodiment, the at least one reset signal line includes: a third reset signal line;

[0037] The first control subcircuit includes: a second transistor;

[0038] The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0039] In an exemplary embodiment, further comprising: a third control subcircuit;

[0040] The third control subcircuit is electrically connected to the fifth reset signal line, the second initial signal line and the fourth node respectively, and is configured to provide the signal of the second initial signal line to the fourth node under the control of the signal of the fifth reset signal line;

[0041] The fifth reset signal line is the same signal line as the fourth reset signal line, or is a different signal line from at least one of the first reset signal line, the third reset signal line and the fourth reset signal line.

[0042] In an exemplary embodiment, it further includes: a writing subcircuit; the writing subcircuit is electrically connected to the scan signal line, the data signal line, and the second node, respectively, and is configured to provide a signal of the data signal line to the second node under the control of a signal of the scan signal line;

[0043] The light-emitting control subcircuit is also electrically connected to the first power line, the second node, the third node and the fifth node; the at least one light-emitting signal line includes: a first light-emitting signal line and a second light-emitting signal line, the driving subcircuit includes: a third transistor, the writing subcircuit includes: a fourth transistor, and the light-emitting control subcircuit includes: a fifth transistor and a sixth transistor;

[0044] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0045] A control electrode of the fourth transistor is electrically connected to the scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node;

[0046] The control electrode of the fifth transistor is electrically connected to the first light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node;

[0047] The control electrode of the sixth transistor is electrically connected to the second light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0048] In an exemplary embodiment, it further includes: a writing subcircuit, the writing subcircuit is electrically connected to the scanning signal line and includes: a fourth transistor, the first control subcircuit includes: a second transistor, the second transistor is electrically connected to the first node and the third node respectively;

[0049] A time period during which the signal of the scanning signal line connected to the control electrode of the fourth transistor is an effective level signal does not overlap with a time period during which the signal of the reset signal line connected to the control electrode of the second transistor is an effective level signal.

[0050] In an exemplary embodiment, the start time of the period in which the signal of the scanning signal line connected to the control electrode of the fourth transistor is an effective level signal is later than the end time of the period in which the signal of the reset signal line connected to the control electrode of the second transistor is an effective level signal.

[0051] In an exemplary embodiment, further comprising: a bias subcircuit;

[0052] The bias subcircuit is electrically connected to at least one of the second node and the third node, the first reset signal line and the bias signal line, respectively, and is configured to provide a signal of the bias signal line to one of the second node and the third node under the control of a signal of the first reset signal line;

[0053] The bias subcircuit includes: a tenth transistor;

[0054] A control electrode of the tenth transistor is electrically connected to the first reset signal line, a first electrode of the tenth transistor is electrically connected to the bias signal line, and a second electrode of the tenth transistor is electrically connected to one of the second node and the third node.

[0055] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned pixel driving circuit.

[0056] In an exemplary embodiment, the present invention further comprises: a substrate and a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines, a plurality of scan signal lines, a plurality of reference signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of light emitting signal lines, a plurality of first power lines, a plurality of data signal lines, and a plurality of power connection lines disposed on the substrate, wherein at least one power connection line is electrically connected to at least one first power line;

[0057] At least one of the first reset signal line, the second reset signal line, the third reset signal line, the fourth reset signal line, the light emitting signal line, the first initial signal line, the second initial signal line, the reference signal line and the power connection line extends at least partially along the first direction, and at least one of the first power line and the data signal line extends at least partially along the second direction, and the first direction and the second direction intersect;

[0058] The orthographic projection of the first initial signal line on the substrate, the orthographic projection of the first reset signal line on the substrate, the orthographic projection of the third reset signal line on the substrate, the orthographic projection of the scanning signal line on the substrate, the orthographic projection of the luminous signal line on the substrate, the orthographic projection of the fourth reset signal line on the substrate, the orthographic projection of the second reset signal line on the substrate, the orthographic projection of the reference signal line on the substrate and the orthographic projection of the second initial signal line on the substrate are arranged in sequence along the second direction, and the orthographic projection of the power connection line on the substrate is located between the orthographic projection of the luminous signal line on the substrate and the orthographic projection of the fourth reset signal line on the substrate.

[0059] In an exemplary embodiment, it further includes: a driving circuit layer, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the pixel driving circuit includes: at least one transistor and at least one capacitor, the transistor includes: an active pattern, a control electrode, a first electrode and a second electrode, the capacitor includes: a first electrode plate and a second electrode plate;

[0060] The semiconductor layer includes: a first initial signal line, a second initial signal line, and an active pattern of at least one transistor located in at least one pixel driving circuit;

[0061] The first conductive layer includes: a light emitting signal line, a control electrode of at least one transistor located in at least one pixel driving circuit, and a second electrode plate of at least one capacitor;

[0062] The second conductive layer includes: a first plate of at least one capacitor located in at least one pixel driving circuit;

[0063] The third conductive layer includes: a first reset signal line, a second reset signal line, a third reset signal line, a fourth reset signal line, a scan signal line, a reference signal line, a power connection line, and a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit;

[0064] The fourth conductive layer includes: a data signal line and a first power line.

[0065] In an exemplary embodiment, the invention further includes: a shielding electrode located at the second conductive layer, the shielding electrode being electrically connected to the first initial signal line;

[0066] The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projections of the first initial signal line, the first reset signal line, the third reset signal line and the scan signal line on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0068] Figure 1 A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0069] Figure 2 A schematic structural diagram of a pixel driving circuit provided in an exemplary embodiment;

[0070] Figure 3 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 1 ;

[0071] Figure 4 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 2 ;

[0072] Figure 5 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 3 ;

[0073] Figure 6 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 4 ;

[0074] Figure 7 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 5 ;

[0075] Figure 8 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 6 ;

[0076] Fig. 9 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 7 ;

[0077] Fig.10 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 8 ;

[0078] Fig.11 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 9 ;

[0079] Fig.12for Figure 3 and Figure 4 The working timing of the pixel driving circuit provided Figure 1 ;

[0080] Fig.13 for Figure 3 and Figure 4 The working timing of the pixel driving circuit provided Figure 2 ;

[0081] Fig.14 for Figure 5 and Figure 6 The working timing diagram of the pixel driving circuit provided;

[0082] Fig.15 for Figure 7 and Figure 8 The working timing diagram of the pixel driving circuit provided;

[0083] Fig.16 for Fig. 9 and Fig.10 The working timing of the pixel driving circuit provided Figure 1 ;

[0084] Fig.17 for Fig. 9 and Fig.10 The working timing of the pixel driving circuit provided Figure 2 ;

[0085] Fig.18 for Fig. 9 and Fig.10 The working timing of the pixel driving circuit provided Figure 3 ;

[0086] Fig.19 is a schematic diagram of the structure of a display device;

[0087] Fig. 20 for Fig.19 A schematic diagram after forming a semiconductor layer pattern;

[0088] Fig.21 for Fig.19 A schematic diagram of a first conductive layer pattern;

[0089] Fig. 22 for Fig.19 A schematic diagram after forming a first conductive layer pattern;

[0090] Fig.23 for Fig.19 A schematic diagram of a second conductive layer pattern;

[0091] Fig.24 for Fig.19 A schematic diagram after forming a second conductive layer pattern;

[0092] Fig.25 for Fig.19 A schematic diagram after forming a fourth insulating layer pattern;

[0093] Fig.26 for Fig.19 A schematic diagram of a third conductive layer pattern;

[0094] Fig. 27 for Fig.19 A schematic diagram after forming a third conductive layer pattern;

[0095] Fig.28 for Fig.19 A schematic diagram after forming a first planar layer pattern;

[0096] Fig.29 for Fig.19 A schematic diagram of a fourth conductive layer pattern;

[0097] Fig.30 for Fig.19 Schematic diagram after forming the fourth conductive layer pattern. DETAILED DESCRIPTION

[0098] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0099] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0100] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0101] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0102] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0103] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0104] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0105] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0106] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0107] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0108] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0109] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0110] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0111] The display device includes: a plurality of sub-pixels, the sub-pixels include a pixel driving circuit and a light-emitting device, the pixel driving circuit is configured to drive the light-emitting device to emit light. The threshold compensation process and the data writing process in the pixel driving circuit occur together, so that the pixel driving circuit cannot achieve high-frequency driving.

[0112] To this end, the present disclosure provides a pixel driving circuit.

[0113] Figure 1 Schematic diagram of the structure of the pixel driving circuit provided by the embodiment of the present disclosure. Figure 1 As shown, the pixel driving circuit provided by the embodiment of the present disclosure may include: a driving subcircuit, a light emitting control subcircuit, a storage subcircuit, a first control subcircuit, and a second control subcircuit. Figure 1As shown, the driving subcircuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of the signal of the first node N1 and the second node N2; the light-emitting control subcircuit is electrically connected to at least one light-emitting signal line, and is configured to output a driving signal under the control of the signal of at least one light-emitting signal line EM; the first control subcircuit is electrically connected to at least one reset signal line Reset, the first node N1 and the third node N3, respectively, and is configured to connect the first node N1 and the third node N3 under the control of at least one reset signal line Reset; the second control subcircuit is electrically connected to the fourth reset signal line Reset4, the first power line VDD and the fifth node N5, respectively, and is configured to provide the signal of the first power line VDD to the fifth node N5 under the control of the signal of the fourth reset signal line Reset4; the storage subcircuit is electrically connected to the first node N1, the second node N2 and the fifth node N5, respectively, and is configured to store the voltage difference of the signal between the first node N1, the second node N2 and the fifth node N5.

[0114] In an exemplary embodiment, the pixel driving circuit is configured to drive the light emitting device L to emit light. The light emitting device L is connected to the fourth node N4 and the second power line VSS, respectively.

[0115] In an exemplary embodiment, the first power line VDD continuously provides a high level signal, and the second power line VSS continuously provides a low level signal.

[0116] In an exemplary embodiment, the light emitting device may include a current driven device, and a current light emitting diode may be used, such as a micro light emitting diode (Micro Light Emitting Diode, Micro LED for short) or a mini light emitting diode (Mini Light Emitting Diode, Mini LED for short) or an organic light emitting diode (Organic Light Emitting Diode, OLED for short) or a quantum dot light emitting diode (Quantum Light Emitting Diode, QLED for short). The typical size (e.g., length) of a Micro LED may be less than 100 μm, such as 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED may be about 100 μm to 300 μm, such as 120 μm to 260 μm.

[0117] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0118] In an exemplary embodiment, a first electrode of the light emitting device L is electrically connected to the fourth node N4 , and a second electrode of the light emitting device L is electrically connected to the second power line VSS.

[0119] In an exemplary embodiment, the organic light emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0120] The present invention can realize the independent occurrence of threshold compensation and data writing in the pixel driving circuit through the mutual cooperation between the driving subcircuit, the light control subcircuit, the storage subcircuit, the first control subcircuit and the second control subcircuit, and can improve the threshold compensation time in the pixel driving circuit, thereby realizing high-frequency driving of the pixel driving circuit.

[0121] In an exemplary embodiment, the at least one light emitting signal line may include a first light emitting signal line, or may include a first light emitting signal line and a second light emitting signal line.

[0122] In an exemplary embodiment, the at least one reset signal line may include at least two of a first reset signal line, a second reset signal line, a third reset signal line, and a fourth reset signal line.

[0123] At least one pixel driving circuit includes: at least one transistor. According to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages).

[0124] In an exemplary embodiment, the P-type transistor may be a low temperature polysilicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor. The active layer of the low temperature polysilicon thin film transistor uses low temperature polysilicon, and the active layer of the oxide thin film transistor uses an oxide semiconductor (Oxide). The low temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, can achieve low frequency driving, can reduce power consumption, and can improve display quality.

[0125] Figure 2 for Figure 1 An equivalent circuit diagram of a storage subcircuit and a second control subcircuit is provided. In an exemplary embodiment, as Figure 2 As shown, the storage subcircuit may include: a first capacitor C1 and a second capacitor C2. The first plate of the first capacitor C1 is electrically connected to the fifth node N5, and the second plate of the first capacitor C1 is electrically connected to the second node N2; the first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the first node N1.

[0126] In an exemplary embodiment, if Figure 2 As shown, the second control subcircuit may include: an eighth transistor T8, a control electrode of the eighth transistor T8 is electrically connected to the fourth reset signal line Reset4, a first electrode of the eighth transistor T8 is electrically connected to the first power line VDD, and a second electrode of the eighth transistor T8 is electrically connected to the fifth node N5.

[0127] In an exemplary embodiment, if Figure 1As shown, the pixel driving circuit may further include: a writing subcircuit, which is electrically connected to the scanning signal line Gate, the data signal line Data and the second node N2 respectively, and is configured to provide the signal of the data signal line Data to the second node N2 under the control of the signal of the scanning signal line Gate.

[0128] In an exemplary embodiment, if Figure 1 As shown, the pixel driving circuit may further include: a third control subcircuit. The third control subcircuit is electrically connected to the fifth reset signal line Reset5, the first reset signal line Reset1 and the bias signal line BIAS, respectively, and is configured to provide a signal of the bias signal line BIAS to one of the second node N2 and the third node N3 under the control of the signal of the first reset signal line Reset1.

[0129] In an exemplary embodiment, if Figure 1 As shown, the pixel driving circuit may further include: a bias subcircuit. The bias subcircuit is electrically connected to at least one of the second node N2 and the third node N3, the first reset signal line Reset1, and the bias signal line BIAS, respectively, and is configured to provide a signal of the bias signal line BIAS to one of the second node N2 and the third node N3 under the control of a signal of the first reset signal line Reset1.

[0130] In an exemplary embodiment, the bias subcircuit is configured to adjust the display afterimage, thereby ensuring the display effect of the display device where the pixel driving circuit is located.

[0131] In an exemplary embodiment, when at least one light-emitting signal line includes a first light-emitting signal line, the first control subcircuit is also electrically connected to the reference signal line REF, the second node N2 and the first initial signal line INIT1, and is configured to provide the signal of the reference signal line REF to the second node N2 and provide the signal of the first initial signal line INIT1 to the first node N1 or the third node N3 under the control of the signal of the at least one reset signal line.

[0132] Figure 3 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 1 , Figure 4 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 2 , Figure 5 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 3 , Figure 6 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 4 , Figure 7 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 5, Figure 8 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 6 .like Figures 3 to 8 As shown, when at least one luminous signal line includes the first luminous signal line EM1, at least one reset signal line includes: at least one of the first reset signal line Reset1, the second reset signal line Reset2 and the third reset signal line Reset3. The first control subcircuit includes: a first transistor T1, a second transistor T2 and a ninth transistor T9.

[0133] Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to one of the first node N1 and the third node N3; the control electrode of the second transistor T2 is electrically connected to the third reset signal line Reset3, the first electrode of the second transistor T2 is electrically connected to the first node N1, the second electrode of the second transistor T2 is electrically connected to the third node N3, the control electrode of the ninth transistor T9 is electrically connected to the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0134] In an exemplary embodiment, the third control subcircuit may include a seventh transistor T7, wherein a control electrode of the seventh transistor T7 is electrically connected to the fifth reset signal line Reset5, a first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0135] like Figures 3 to 8 As shown, when at least one light-emitting signal line includes the first light-emitting signal line EM1, the driving subcircuit includes: a third transistor T3, the writing subcircuit includes: a fourth transistor T4, and the light-emitting control subcircuit includes: a fifth transistor T5 and a sixth transistor T6, wherein the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the scanning signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. Figure 3 , Figure 5 and Figure 7 The following description is made by taking the example that the second electrode of the first transistor T1 is electrically connected to the first node N1. Figure 4 , Figure 6 and Figure 8 The description is made by taking the example that the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0136] In an exemplary embodiment, the second reset signal line Reset2 and the third reset signal line Reset3 are different signal lines, or are the same signal line.

[0137] In an exemplary embodiment, the fifth reset signal line Reset5 is the same signal line as one of the second reset signal line Reset2 and the fourth reset signal line Reset4 .

[0138] Figure 3 and Figure 4 The description is made by taking the example that the second reset signal line Reset2 and the third reset signal line Reset3 are different signal lines, and the fifth reset signal line Reset5 and the second reset signal line Reset2 are the same signal line. Figure 5 and Figure 6 The description is made by taking the second reset signal line Reset2 , the third reset signal line Reset3 , and the fifth reset signal line Reset5 as the same signal line as an example. Figure 7 and Figure 8 The description is made by taking the example that the second reset signal line Reset2 and the third reset signal line Reset3 are the same signal line, and the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are the same signal line.

[0139] In an exemplary embodiment, Figures 3 to 8 The provided pixel driving circuit may further include: a bias subcircuit. The bias subcircuit includes: a tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected to the first reset signal line Reset1, the first electrode of the tenth transistor T10 is electrically connected to the bias signal line BIAS, and the second electrode of the tenth transistor T10 is electrically connected to one of the second node N2 and the third node N3.

[0140] In an exemplary embodiment, Figures 3 to 8The first transistor T1 to the tenth transistor T10 in at least one pixel driving circuit may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the tenth transistor T10 may include a P-type transistor and an N-type transistor.

[0141] In an exemplary embodiment, Figures 3 to 8 The description is made by taking the example that the first transistor T1 to the tenth transistor T10 are all P-type transistors.

[0142] In an exemplary embodiment, Figures 3 to 8 The first transistor T1, the second transistor T2 and the eighth transistor T8 in at least one pixel driving circuit may be N-type transistors, and the third transistor T3 to the seventh transistor T7, the ninth transistor T9 and the tenth transistor T10 may be P-type transistors. Figures 3 to 8 The first transistor T1, the second transistor T2 and the eighth transistor T8 in at least one pixel driving circuit may be N-type transistors, which can reduce the leakage current of the first node N1, thereby improving the reliability of the pixel driving circuit.

[0143] Fig. 9 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 7 , Fig.10 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 8 .like Fig. 9 and Fig.10 As shown, when at least one luminous signal line includes: a first luminous signal line EM1 and a second luminous signal line EM2, at least one reset signal line may include: at least one of a first reset signal line Reset1 and a third reset signal line Reset3. The first control subcircuit is also electrically connected to the first initial signal line INIT1. The first control subcircuit includes a first transistor T1 and a second transistor T2. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to one of the first node N1 and the third node N3; the control electrode of the second transistor T2 is electrically connected to the third reset signal line Reset3, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. Fig. 9 The second electrode of the first transistor and the first node N1 are used as an example for explanation. Fig.10 The second electrode of the first transistor and the third node N3 are taken as an example for description.

[0144] Fig.11 Equivalent circuit of the pixel driving circuit provided by the embodiment of the present disclosure Figure 9 ,like Fig.11 As shown, when the at least one luminous signal line includes: a first luminous signal line EM1 and a second luminous signal line EM2, the at least one reset signal line may include: a third reset signal line Reset3. The first control subcircuit includes a second transistor T2. The control electrode of the second transistor T2 is electrically connected to the third reset signal line Reset3, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3.

[0145] In an exemplary embodiment, the third control subcircuit may include a seventh transistor T7, wherein a control electrode of the seventh transistor T7 is electrically connected to the fifth reset signal line Reset5, a first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0146] like Figure 10 to Figure 11 As shown, when at least one light-emitting signal line includes a first light-emitting signal line and a second light-emitting signal line, the driving subcircuit includes: a third transistor T3, the writing subcircuit includes: a fourth transistor T4, and the light-emitting control subcircuit includes: a fifth transistor T5 and a sixth transistor T6, wherein the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. Figure 3 , Figure 5 and Figure 7 The following description is made by taking the example that the second electrode of the first transistor T1 is electrically connected to the first node N1. Figure 4 , Figure 6 and Figure 8 The description is made by taking the example that the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0147] In an exemplary embodiment, the fifth reset signal line Reset5 is the same signal line as the fourth reset signal line Reset4 , or may be a different signal line from at least one of the first reset signal line Reset1 , the third reset signal line Reset3 , and the fourth reset signal line Reset4 .

[0148] In an exemplary embodiment, Figures 9 to 11 The provided pixel driving circuit may further include: a bias subcircuit. The bias subcircuit includes: a tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected to the first reset signal line Reset1, the first electrode of the tenth transistor T10 is electrically connected to the bias signal line BIAS, and the second electrode of the tenth transistor T10 is electrically connected to one of the second node N2 and the third node N3.

[0149] In an exemplary embodiment, Fig. 9 and Fig.10 The first transistor T1 to the eighth transistor T8 and the tenth transistor T10 in at least one pixel driving circuit may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 and the tenth transistor T10 may include a P-type transistor and an N-type transistor. Fig. 9 and Fig.10 The description is made by taking the first transistor T1 to the eighth transistor T8 and the tenth transistor T10 as P-type transistors as an example.

[0150] In an exemplary embodiment, Fig. 9 and Fig.10 The first transistor T1 , the second transistor T2 and the eighth transistor T8 may be N-type transistors, and the third transistor T3 to the seventh transistor T7 and the tenth transistor T10 may be P-type transistors.

[0151] Fig. 9 and Fig.10 The first transistor T1 , the second transistor T2 , and the eighth transistor T8 are N-type transistors, which can reduce the leakage current of the first node N1 , thereby improving the reliability of the pixel driving circuit.

[0152] In an exemplary embodiment, Fig.11The second transistor T2 to the eighth transistor T8 and the tenth transistor T10 in at least one pixel driving circuit may be a P-type transistor or an N-type transistor. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the second transistor T2 to the eighth transistor T8 and the tenth transistor T10 may include a P-type transistor and an N-type transistor. Fig.11 The description is made by taking the second transistor T2 to the eighth transistor T8 and the tenth transistor T10 as P-type transistors as an example.

[0153] In an exemplary embodiment, Fig.11 The second transistor T2 and the eighth transistor T8 may be N-type transistors, and the third transistor T3 to the seventh transistor T7 and the tenth transistor T10 may be P-type transistors.

[0154] Fig.11 The second transistor T2 and the eighth transistor T8 are N-type transistors, which can reduce the leakage current of the first node N1, thereby improving the reliability of the pixel driving circuit.

[0155] In an exemplary embodiment, if Figures 2 to 11 As shown, the writing subcircuit includes: a fourth transistor T4, and the node control subcircuit includes: a second transistor T2, and the second transistor T2 is electrically connected to the first node N1 and the third node N3 respectively. The reset signal line connected to the control electrode of the second transistor T2 can be the second reset signal line Reset2 or the third reset signal line Reset3. The time period in which the signal of the scanning signal line Gate connected to the control electrode of the fourth transistor is a valid level signal does not overlap with the time period in which the signal of the reset signal line connected to the control electrode of the second transistor is a valid level signal. The time period in which the signal of the scanning signal line Gate connected to the control electrode of the fourth transistor is a valid level signal does not overlap with the time period in which the signal of the reset signal line connected to the control electrode of the second transistor is a valid level signal, so that the time period of threshold compensation and the time period of data writing do not overlap, thereby realizing the separate occurrence of threshold compensation and data writing.

[0156] In an exemplary embodiment, the start time of the period in which the signal of the scan signal line Gate connected to the gate electrode of the fourth transistor is an effective level signal is later than the end time of the period in which the signal of the reset signal line connected to the gate electrode of the second transistor is an effective level signal.

[0157] In an exemplary embodiment, Fig.12 for Figure 3 and Figure 4 The working timing of the pixel driving circuit provided Figure 1 . Combined Figure 3and Fig.12 As shown, Figure 3 The working process of the provided pixel driving circuit may include:

[0158] The first stage P11 is called the initialization stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are low level signals, and the signals of the first light emitting signal line EM1, the scanning signal line Gate, the second reset signal line Reset2, and the fifth reset signal line Reset5 are high level signals. The first transistor T1, the second transistor T2, and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are turned off.

[0159] The first transistor T1 and the second transistor T2 are turned on, and the initial signal of the first initial signal line INIT1 is written into the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), and the pre-stored voltage inside them is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0160] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 = Vinit1, the voltage value of the signal at the third node N3 is V N3 Meet V N3 = Vinit1, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, and Vdd is the voltage value of the signal of the first power line VDD.

[0161] The second stage P12 is called the threshold compensation stage, the signals of the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the first light emitting signal line EM1, the first reset signal line Reset1 and the scanning signal line Gate are high level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0162] The second transistor T2 and the ninth transistor T9 are turned on, the signal of the reference signal line REF is written into the second node N2, and the first node N1 is charged by the turned-on ninth transistor T9, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 Meet V N1 =Vref+Vth, where Vref is the voltage value of the signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0163] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vref, the voltage value of the signal at the third node N3 V N3 Meet V N3 =Vref+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the amount of charge stored in the first capacitor C1 is Vdd-Vref, and the amount of charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0164] The third stage P13 is called the data writing stage, the signals of the scanning signal line Gate and the fourth reset signal line Reset4 are low level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fifth reset signal line Reset5 and the first light emitting signal line EM1 are high level signals. The fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0165] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written into the second node N2, the eighth transistor T8 is turned on, the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0166] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the third node N3 V N3 Meet V N3 =Vref+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the amount of charge stored in the first capacitor C1 is Vdd-Vref, and the amount of charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0167] In the fourth stage P14, referred to as the light-emitting stage, the signal of the first light-emitting signal line EM1 is a low-level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the scanning signal line Gate are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0168] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device L to emit light.

[0169] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the fourth node N4 V N4 Meet V N4=Voled+Vss, Voled is the voltage difference applied to both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0170] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 satisfies V N2 =Vdata, so the driving current of the third transistor T3 is:

[0171] I=K*(Vgs-Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0172] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0173] The above is based on Figure 3 Taking the first transistor T1 to the ninth transistor T9 as an example, when Figure 2 When the pixel driving circuit includes the tenth transistor T10, the tenth transistor T10 is turned on in the first stage and turned off in the second stage to the fourth stage. When the tenth transistor T10 is turned on, the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0174] Figure 4 The pixel driving circuit provided is Figure 3 The pixel driving circuit provided is different only in the position of the first transistor T1. The first transistor T1 is only turned on in the first stage. Therefore, Figure 4 The working process of the pixel driving circuit provided is similar to Figure 3 The working process of the provided pixel driving circuit is the same and will not be described in detail herein.

[0175] In an exemplary embodiment, Fig.13 for Figure 3 and Figure 4 The working timing of the pixel driving circuit provided Figure 2 . Fig.12 and Fig.13 The only difference is the signal of the third reset signal line Reset3. Fig.12The signal of the second reset signal line Reset2 in the first stage is a high level signal and a low level signal in the second stage. The second reset signal line Reset2 is a low level signal in both the first stage and the second stage. Fig.13 The signals of the second reset signal line Reset2 and the third reset signal line Reset3 are exactly the same. And both are high level signals in the first stage and low level signals in the second stage. Therefore, Fig.13 The working timing provided is Fig.12 Compared with the working sequence provided, only the working process in the first stage is different, and the working processes in the remaining stages are exactly the same. The present disclosure only describes the working process in the first stage.

[0176] Combination Figure 3 and Fig.13 As shown, Figure 3 The working process of the provided pixel driving circuit may include:

[0177] The first stage P11 is called the initialization stage, the signals of the first reset signal line Reset1 and the fourth reset signal line Reset4 are low level signals, and the signals of the first light emitting signal line EM1, the scanning signal line Gate, the second reset signal line Reset2, the third reset signal line Reset3 and the fifth reset signal line Reset5 are high level signals. The first transistor T1 and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0178] The first transistor T1 is turned on, and the initial signal of the first initial signal line INIT1 is written into the first node N1, the first node N1 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0179] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 = Vinit1, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, and Vdd is the voltage value of the signal of the first power line VDD.

[0180] The above is based on Figure 3 Taking the first transistor T1 to the ninth transistor T9 as an example, when Figure 3When the pixel driving circuit includes the tenth transistor T10, the tenth transistor T10 is turned on in the first stage and turned off in the second stage to the fourth stage. When the tenth transistor T10 is turned on, the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0181] Combination Figure 4 and Fig.13 As shown, Figure 4 The working process of the provided pixel driving circuit may include:

[0182] The first stage P11 is called the initialization stage, the signals of the first reset signal line Reset1 and the fourth reset signal line Reset4 are low level signals, and the signals of the first light emitting signal line EM1, the scanning signal line Gate, the second reset signal line Reset2, the third reset signal line Reset3 and the fifth reset signal line Reset5 are high level signals. The first transistor T1 and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0183] The first transistor T1 is turned on, and the initial signal of the first initial signal line INIT1 is written into the third node N3, the third node N3 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0184] In this stage, the voltage value V of the signal at the third node N3 is N3 Meet V N3 = Vinit1, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, and Vdd is the voltage value of the signal of the first power line VDD.

[0185] In an exemplary embodiment, when the first transistor T1, the second transistor T2 and the eighth transistor T8 are N-type transistors, the signal of the first reset signal line Reset1 is a high level signal in the first stage, the second reset signal line Reset2 is a high level signal in the second stage, and the fourth reset signal line Reset4 is a high level signal in the first stage, the second stage and the third stage.

[0186] In an exemplary embodiment, Fig.14 for Figure 5 and Figure 6 The working timing diagram of the pixel driving circuit provided. Figure 5 and Fig.14 As shown, Figure 5 The working process of the provided pixel driving circuit may include:

[0187] The first stage P21 is called the initialization stage, the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the first light emitting signal line EM1 and the scanning signal line Gate are high level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0188] The first transistor T1 and the second transistor T2 are turned on, and the initial signal of the first initial signal line INIT1 is written into the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal line REF is written into the second node N2, the second node N2 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0189] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 = Vinit1, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vref, the voltage value of the signal at the third node N3 V N3 Meet V N3 = Vinit1, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, Vref is the voltage value of the signal of the reference signal line REF, and Vdd is the voltage value of the signal of the first power line VDD.

[0190] The second stage P22 is called the threshold compensation stage, the signals of the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the first light emitting signal line EM1, the first reset signal line Reset1 and the scanning signal line Gate are high level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0191] The second transistor T2 and the ninth transistor T9 are turned on, the signal of the reference signal line REF is written into the second node N2, and the first node N1 is charged by the turned-on ninth transistor T9, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 Meet V N1 =Vref+Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0192] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vref, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the amount of charge stored in the first capacitor C1 is Vdd-Vref, and the amount of charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0193] The third stage P23 is called the data writing stage, the signals of the scanning signal line Gate and the fourth reset signal line Reset4 are low level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fifth reset signal line Reset5 and the first light emitting signal line EM1 are high level signals. The fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0194] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written into the second node N2, the eighth transistor T8 is turned on, the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0195] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the third node N3 V N3 Meet V N3 =Vref+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the amount of charge stored in the first capacitor C1 is Vdd-Vref, and the amount of charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0196] The fourth stage P24 is called the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the scanning signal line Gate are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0197] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device L to emit light.

[0198] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the fourth node N4 V N4 Meet V N4 =Voled+Vss, Voled is the voltage difference applied to both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0199] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 satisfies V N2 =Vdata, so the driving current of the third transistor T3 is:

[0200] I=K*(Vgs-Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0201] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0202] The above is based on Figure 5 Taking the first transistor T1 to the ninth transistor T9 as an example, when Figure 5 When the pixel driving circuit includes the tenth transistor T10, the tenth transistor T10 is turned on in the first stage and turned off in the second stage to the fourth stage. When the tenth transistor T10 is turned on, the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0203] Figure 6 The pixel driving circuit provided is Figure 5The pixel driving circuit provided is different only in the position of the first transistor T1. The first transistor T1 is only turned on in the first stage. Therefore, Figure 6 The working process of the pixel driving circuit provided is similar to Figure 5 The working process of the provided pixel driving circuit is the same and will not be described in detail herein.

[0204] In an exemplary embodiment, when the first transistor T1, the second transistor T2 and the eighth transistor T8 are N-type transistors, the signal of the first reset signal line Reset1 is a high-level signal in the first stage, the second reset signal line Reset2 is a high-level signal in the first stage and the second stage, and the third reset signal line Reset3 is a high-level signal in the first stage, the second stage and the third stage.

[0205] In an exemplary embodiment, Fig.15 for Figure 7 and Figure 8 The working timing diagram of the pixel driving circuit provided. Figure 7 and Fig.15 As shown, Figure 7 The working process of the provided pixel driving circuit may include:

[0206] The first stage P31 is called the initialization stage, the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset4, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the first light emitting signal line EM1 and the scanning signal line Gate are high level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0207] The first transistor T1 and the second transistor T2 are turned on, and the initial signal of the first initial signal line INIT1 is written into the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal line REF is written into the second node N2, the second node N2 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0208] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 = Vinit1, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vref, the voltage value of the signal at the third node N3 V N3 Meet V N3 = Vinit1, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, Vref is the voltage value of the signal of the reference signal line REF, and Vdd is the voltage value of the signal of the first power line VDD.

[0209] The second stage P32 is called the threshold compensation stage, the signals of the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the first light emitting signal line EM1, the first reset signal line Reset1 and the scanning signal line Gate are high level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0210] The second transistor T2 and the ninth transistor T9 are turned on, the signal of the reference signal line REF is written into the second node N2, and the first node N1 is charged by the turned-on ninth transistor T9, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 Meet V N1 =Vref+Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0211] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2Meet V N2 =Vref, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the amount of charge stored in the first capacitor C1 is Vdd-Vref, and the amount of charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0212] The third stage P33 is called the data writing stage, the signals of the scanning signal line Gate, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3 and the first light emitting signal line EM1 are high level signals. The fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0213] The fourth transistor T4 is turned on, and the data voltage of the data signal line Data is written into the second node N2. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, and the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, and the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0214] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the third node N3 V N3 Meet V N3 =Vref+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the amount of charge stored in the first capacitor C1 is Vdd-Vref, and the amount of charge stored in the second capacitor C2 is Vdd-Vref-Vth.

[0215] In the fourth stage P34, referred to as the light-emitting stage, the signal of the first light-emitting signal line EM1 is a low-level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the scanning signal line Gate are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0216] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device L to emit light.

[0217] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the fourth node N4 V N4 Meet V N4 =Voled+Vss, Voled is the voltage difference applied to both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0218] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 satisfies V N2 =Vdata, so the driving current of the third transistor T3 is:

[0219] I=K*(Vgs-Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0220] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0221] The above is based on Figure 7 Taking the first transistor T1 to the ninth transistor T9 as an example, when Figure 7 When the pixel driving circuit includes the tenth transistor T10, the tenth transistor T10 is turned on in the first stage and turned off in the second stage to the fourth stage. When the tenth transistor T10 is turned on, the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0222] Figure 8 The pixel driving circuit provided is Figure 7 The pixel driving circuit provided is different only in the position of the first transistor T1. The first transistor T1 is only turned on in the first stage. Therefore, Figure 8 The working process of the pixel driving circuit provided is similar to Figure 7 The working process of the provided pixel driving circuit is the same and will not be described in detail herein.

[0223] In an exemplary embodiment, when the first transistor T1, the second transistor T2 and the eighth transistor T8 are N-type transistors, the signal of the first reset signal line Reset1 is a high-level signal in the first stage, the second reset signal line Reset2 is a high-level signal in the first stage and the second stage, and the third reset signal line Reset3 is a high-level signal in the first stage, the second stage and the third stage.

[0224] In an exemplary embodiment, Fig.16 for Fig. 9 and Fig.10 The working timing of the pixel driving circuit provided Figure 1 . Combined Fig. 9 and Fig.16 As shown, Fig. 9 The working process of the provided pixel driving circuit may include:

[0225] The first stage P41 is called the initialization stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, and the first light-emitting signal line EM1 are low-level signals, and the signals of the second light-emitting signal line EM2, the scanning signal line Gate, and the fifth reset signal line Reset5 are high-level signals. The first transistor T1, the second transistor T2, the fifth transistor T5, and the eighth transistor T8 are turned on, and the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0226] The first transistor T1 and the second transistor T2 are turned on, and the initial signal of the first initial signal line INIT1 is written into the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), and the pre-stored voltage inside them is cleared, and the initialization is completed. The fifth transistor T5 is turned on, and the signal of the first power line VDD is written into the second node N2, the second node N2 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0227] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 = Vinit1, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdd, the voltage value of the signal at the third node N3 is V N3 Meet V N3 = Vinit1, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, and Vdd is the voltage value of the signal of the first power line VDD.

[0228] The second stage P42 is called the threshold compensation stage, the signals of the first light emitting signal line EM1, the fifth reset signal line Reset5, the third reset signal line Reset3 and the fourth reset signal line Reset4 are low level signals, and the signals of the second light emitting signal line EM2, the first reset signal line Reset1 and the scanning signal line Gate are high level signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0229] The second transistor T2 and the fifth transistor T5 are turned on, the signal of the first power line VDD is written into the second node N2, and the first node N1 is charged through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 Meet V N1=Vdd+Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0230] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vdd+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdd, the voltage value of the signal at the third node N3 is V N3 Meet V N3 =Vdd+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the amount of charge stored in the first capacitor C1 is 0, and the amount of charge stored in the second capacitor C2 is Vth.

[0231] The third stage P43 is called the data writing stage, the signals of the scanning signal line Gate and the fourth reset signal line Reset4 are low level signals, and the signals of the first reset signal line Reset1, the fifth reset signal line Reset5, the third reset signal line Reset3, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals. The fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0232] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written into the second node N2, the eighth transistor T8 is turned on, the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0233] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vdd+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2=Vdata, the voltage value of the signal at the third node N3 V N3 Meet V N3 =Vdd+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the amount of charge stored in the first capacitor C1 is 0, and the amount of charge stored in the second capacitor C2 is Vth.

[0234] The fourth stage P44 is called the light-emitting stage, the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, and the signals of the first reset signal line Reset1, the fifth reset signal line Reset5, the third reset signal line Reset3, the fourth reset signal line Reset4 and the scanning signal line Gate are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0235] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device L to emit light.

[0236] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the fourth node N4 V N4 Meet V N4 =Voled+Vss, Voled is the voltage difference applied to both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0237] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. N1 Meet V N1 =Vdd+Vth, the voltage value of the signal at the second node N2 satisfies V N2 =Vdata, so the driving current of the third transistor T3 is:

[0238] I=K*(Vgs-Vth) 2 =K*(Vdd+Vth-Vdata-Vth) 2 =K*(Vdd-Vdata) 2

[0239] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0240] The above is based on Fig. 9 Taking the first transistor T1 to the eighth transistor T8 as an example, when Figure 8 When the pixel driving circuit includes the tenth transistor T10, the tenth transistor T10 is turned on in the first stage and turned off in the second stage to the fourth stage. When the tenth transistor T10 is turned on, the signal of the bias signal line BIAS is written into the second node N2 or the third node N3.

[0241] Fig.10 The pixel driving circuit provided is Fig. 9 The pixel driving circuit provided is different only in the position of the first transistor T1. The first transistor T1 is only turned on in the first stage. Therefore, Fig.10 The working process of the pixel driving circuit provided is similar to Fig. 9 The working process of the provided pixel driving circuit is the same and will not be described in detail herein.

[0242] for Fig.11 The provided pixel driving circuit can make the first light-emitting signal line EM1 a low-level signal in the second stage, and the second light-emitting signal line EM2 a low-level signal in the first stage, reset the first node through the second initial signal line, the seventh transistor, the sixth transistor, and the second transistor, and compensate the signal of the first node through the first power line, the fifth transistor, the third transistor, and the second transistor.

[0243] In an exemplary embodiment, Fig.17 for Fig. 9 and Fig.10 The working timing of the pixel driving circuit provided Figure 2 . Combined Fig. 9 and Fig.17 As shown, Fig. 9 The working process of the provided pixel driving circuit may include:

[0244] The first stage P51 is called the initialization stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the first light-emitting signal line EM1 are low-level signals, and the signals of the second light-emitting signal line EM2 and the scanning signal line Gate are high-level signals. The first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0245] The first transistor T1 and the second transistor T2 are turned on, and the initial signal of the first initial signal line INIT1 is written into the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The fifth transistor T5 is turned on, and the signal of the reference signal line REF is written into the second node N2, the second node N2 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0246] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 = Vinit1, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdd, the voltage value of the signal at the third node N3 is V N3 Meet V N3 = Vinit1, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, and Vdd is the voltage value of the signal of the first power line VDD.

[0247] The second stage P52 is called the threshold compensation stage, the signals of the first light emitting signal line EM1, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the second light emitting signal line EM2, the first reset signal line Reset1 and the scanning signal line Gate are high level signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0248] The second transistor T2 and the fifth transistor T5 are turned on, the signal of the first power line VDD is written into the second node N2, and the first node N1 is charged through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value VN1 of the signal at the first node N1 meets V N1 =Vdd+Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0249] In this stage, the voltage value VN1 of the signal at the first node N1 satisfies V N1 =Vdd+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 = Vdd, the voltage value VN4 of the signal at the fourth node N4 satisfies V N4 = Vinit2, the voltage value VN5 of the signal at the fifth node N5 satisfies V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the amount of charge stored in the first capacitor C1 is 0, and the amount of charge stored in the second capacitor C2 is Vth.

[0250] The third stage P53 is called the data writing stage, the signals of the scanning signal line Gate and the fourth reset signal line Reset4 are low level signals, and the signals of the first reset signal line Reset1, the third reset signal line Reset3, the fifth reset signal line Reset5, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals. The fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0251] The fourth transistor T4 is turned on, the data voltage of the data signal line Data is written into the second node N2, the eighth transistor T8 is turned on, the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0252] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vdd+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the third node N3 V N3 Meet V N3 =Vdd+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value VN5 of the signal at the fifth node N5 satisfies V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the amount of charge stored in the first capacitor C1 is 0, and the amount of charge stored in the second capacitor C2 is Vth.

[0253] In the fourth stage P54, referred to as the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the fifth reset signal line Reset5 and the scanning signal line Gate are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0254] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device L to emit light.

[0255] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the fourth node N4 V N4 Meet V N4 =Voled+Vss, Voled is the voltage difference applied to both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0256] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 satisfies V N2 =Vdata, so the driving current of the third transistor T3 is:

[0257] I=K*(Vgs-Vth) 2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0258] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0259] for Fig. 9 and Fig.10 The provided pixel driving circuit can make the first light-emitting signal line EM1 a low-level signal in the second stage, and the second light-emitting signal line EM2 a low-level signal in the first stage, reset the first node through the second initial signal line, the seventh transistor, the sixth transistor, and the second transistor, and compensate the signal of the first node through the first power line, the fifth transistor, the third transistor, and the second transistor.

[0260] In an exemplary embodiment, Fig.18 for Fig. 9 and Fig.10 The working timing of the pixel driving circuit provided Figure 3 . Combined Fig. 9 and Fig.18 As shown, Fig. 9 The working process of the provided pixel driving circuit may include:

[0261] The first stage P61 is called the initialization stage, the signals of the first light emitting signal line EM1, the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the second light emitting signal line EM2 and the scanning signal line Gate are high level signals. The first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0262] The first transistor T1 and the second transistor T2 are turned on, and the initial signal of the first initial signal line INIT1 is written into the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The fifth transistor T5 is turned on, and the signal of the first power line VDD is written into the second node N2, the second node N2 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0263] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 = Vinit1, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdd, the voltage value of the signal at the third node N3 is V N3 Meet V N3 = Vinit1, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit1 is the voltage value of the signal of the first initial signal line INIT1, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, and Vdd is the voltage value of the signal of the first power line VDD.

[0264] The second stage P62 is called the threshold compensation stage, the signals of the first light emitting signal line EM1, the third reset signal line Reset3, the fourth reset signal line Reset4 and the fifth reset signal line Reset5 are low level signals, and the signals of the second light emitting signal line EM2, the first reset signal line Reset1 and the scanning signal line Gate are high level signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0265] The second transistor T2 and the fifth transistor T5 are turned on, the signal of the reference signal line REF is written into the second node N2, and the first node N1 is charged by the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 Meet VN1 =Vdd+Vth, where Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0266] In this stage, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vdd+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdd, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vinit2 is the voltage value of the signal of the second initial signal line INIT2, the amount of charge stored in the first capacitor C1 is 0, and the amount of charge stored in the second capacitor C2 is Vth.

[0267] The third stage P63 is called the data writing stage, the signals of the scanning signal line Gate and the fourth reset signal line Reset4 are low level signals, and the signals of the first reset signal line Reset1, the fifth reset signal line Reset5, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals. The fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0268] The fourth transistor T4 is turned on, and the data voltage of the data signal line Data is written into the second node N2. The eighth transistor T8 is turned on, and the signal of the first power line VDD is written into the fifth node N5, and the fifth node N5 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4, and the first electrode of the light-emitting device is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.

[0269] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2=Vdata, the voltage value of the signal at the third node N3 V N3 Meet V N3 =Vdd+Vth, the voltage value of the signal at the fourth node N4 is V N4 Meet V N4 = Vinit2, the voltage value of the signal at the fifth node N5 is V N5 Meet V N5 =Vdd, Vdata is the data voltage of the data signal line Data, the amount of charge stored in the first capacitor C1 is 0, and the amount of charge stored in the second capacitor C2 is Vth.

[0270] The fourth stage P64 is called the light-emitting stage, the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, and the signals of the first reset signal line Reset1, the fifth reset signal line Reset5, the fourth reset signal line Reset4 and the scanning signal line Gate are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0271] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device L to emit light.

[0272] In this stage, under the action of the first capacitor C1 and the second capacitor C2, the voltage value V of the signal at the first node N1 is N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 is V N2 Meet V N2 =Vdata, the voltage value of the signal at the fourth node N4 V N4 Meet V N4 =Voled+Vss, Voled is the voltage difference applied to both sides of the light emitting device L, and Vss is the voltage value of the signal of the second power line VSS.

[0273] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. N1 Meet V N1 =Vref+Vth, the voltage value of the signal at the second node N2 satisfies V N2 =Vdata, so the driving current of the third transistor T3 is:

[0274] I=K*(Vgs-Vth)2 =K*(Vref+Vth-Vdata-Vth) 2 =K*(Vref-Vdata) 2

[0275] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3.

[0276] In an exemplary embodiment, Figures 3 to 8 The pixel driving circuit provided includes: first transistor to ninth transistor. The path of threshold compensation: reference signal line, ninth transistor, third transistor and second transistor are used to compensate the first node. The path of data writing includes: data signal line and fourth transistor, and the data voltage of the data signal line is written into the pixel driving circuit. Figures 9 to 17 In the pixel driving circuit provided, since the fifth transistor and the sixth transistor are respectively controlled by the first light emitting signal line and the second light emitting signal line, the path of threshold compensation: the first power line, the fifth transistor, the third transistor and the second transistor compensate the first node, and the path of data writing includes: the data signal line and the fourth transistor, and the data voltage of the data signal line is written into the pixel driving circuit. Therefore, Figures 9 to 11 The pixel drive circuit provided is Figures 3 to 8 Compared with the pixel driving circuit provided, the pixel driving circuit occupies a smaller area, which is more conducive to achieving a high PPI of the display device.

[0277] The embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit provided by any of the aforementioned embodiments. The driving method of the pixel driving circuit may include the following steps:

[0278] The driving sub-circuit provides a driving signal to the third node under the control of the signals at the first node and the second node.

[0279] The light-emitting control subcircuit outputs a driving signal under the control of a signal of at least one light-emitting signal line.

[0280] The first control subcircuit connects the first node and the third node under the control of at least one reset signal line.

[0281] The second control subcircuit provides a signal of the first power line to the fifth node based on the fourth reset signal line.

[0282] The storage sub-circuit stores voltage differences of signals between the first node, the second node, and the fifth node.

[0283] An embodiment of the present disclosure further provides a display device, comprising: a pixel driving circuit provided by any one of the aforementioned embodiments.

[0284] In an exemplary embodiment, Fig.19 FIG. 1 is a schematic diagram of the structure of the display device. Fig.19 As shown, it also includes: a substrate and a plurality of first reset signal lines Reset1, a plurality of second reset signal lines Reset2, a plurality of third reset signal lines Reset3, a plurality of fourth reset signal lines Reset4, a plurality of scanning signal lines, a plurality of reference signal lines REF, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of light-emitting signal lines, a plurality of first power lines VDD and a plurality of data signal lines Data, which are arranged on the substrate.

[0285] In an exemplary embodiment, at least one of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the light emitting signal line, the first initial signal line INIT1, the second initial signal line INIT2, and the reference signal line REF extends at least partially along the first direction D1.

[0286] In an exemplary embodiment, at least one of the first power line VDD and the data signal line Data extends at least partially along the second direction D2, and the first direction D1 and the second direction D2 intersect. The angle between the first direction D1 and the second direction D2 may be 70 degrees to 90 degrees, and exemplarily, the angle between the first direction D1 and the second direction D2 is 90 degrees.

[0287] In an exemplary embodiment, the orthographic projection of the first initial signal line INIT1 on the substrate, the orthographic projection of the first reset signal line Reset1 on the substrate, the orthographic projection of the third reset signal line Reset3 on the substrate, the orthographic projection of the scanning signal line on the substrate, the orthographic projection of the light-emitting signal line on the substrate, the orthographic projection of the fourth reset signal line Reset4 on the substrate, the orthographic projection of the second reset signal line Reset2 on the substrate, the orthographic projection of the reference signal line REF on the substrate, and the orthographic projection of the second initial signal line INIT2 on the substrate are arranged sequentially along the second direction D2.

[0288] In an exemplary embodiment, the display device further includes: a plurality of power connection lines VDL located in the third conductive layer, the power connection lines VDL at least partially extending along the first direction D1; and at least one power connection line is electrically connected to the at least one first power line VDD.

[0289] In an exemplary embodiment, an orthographic projection of the power connection line VDL on the substrate is located between an orthographic projection of the first light emitting signal line EM11 on the substrate and an orthographic projection of the fourth reset signal line Reset4 on the substrate.

[0290] In an exemplary embodiment, the display device further includes: a driving circuit layer, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the pixel driving circuit includes: at least one transistor and at least one capacitor, the transistor includes: an active pattern, a control electrode, a first electrode and a second electrode, and the capacitor includes: a first electrode plate and a second electrode plate;

[0291] The semiconductor layer includes a first initial signal line INIT1, a second initial signal line INIT2, and an active pattern of at least one transistor in at least one pixel driving circuit.

[0292] The first conductive layer includes: a first light emitting signal line EM1, a control electrode of at least one transistor located in at least one pixel driving circuit, and a second electrode plate of at least one capacitor.

[0293] The second conductive layer includes: a first plate of at least one capacitor located in at least one pixel driving circuit.

[0294] The third conductive layer may include: a first reset signal line Reset1, a second reset signal line Reset2, a third reset signal line Reset3, a fourth reset signal line Reset4, a scan signal line Gate, a reference signal line REF, a power connection line VDL, and a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit.

[0295] The fourth conductive layer includes: a data signal line Data and a first power line VDD.

[0296] In an exemplary embodiment, the display device further includes a shielding electrode SL located in the second conductive layer, and the shielding electrode SL is electrically connected to the first initial signal line INIT1.

[0297] In an exemplary embodiment, an orthographic projection of the shielding electrode SL on the substrate at least partially overlaps with orthographic projections of the first initial signal line INIT1 , the first reset signal line Reset1 , the third reset signal line Reset3 , and the scan signal line on the substrate.

[0298] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0299] Figures 20 to 30 A schematic diagram of a process for preparing a display substrate is provided for an exemplary embodiment. Figures 20 to 30 The pixel driving circuit is a row of three columns, and the pixel driving circuit is Figure 2 The pixel driving circuit provided is used as an example for explanation. A preparation process of a display substrate provided by an exemplary embodiment may include:

[0300] In an exemplary embodiment, at least one transistor includes an active pattern, a gate electrode, a first electrode, and a second electrode.

[0301] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a first semiconductor film on a substrate, patterning the first insulating film and the first semiconductor film through a patterning process, forming a first insulating layer pattern and a semiconductor layer pattern formed on the first insulating layer pattern, such as Fig. 20 As shown, Fig. 20 for Fig.19 Schematic diagram after patterning the semiconductor layer.

[0302] In an exemplary embodiment, the semiconductor layer pattern may include a first connection line L1 , a second connection line L2 , and an active pattern T11 of a first transistor to an active pattern T91 of a ninth transistor in at least one pixel driving circuit.

[0303] In an exemplary embodiment, the active pattern T11 of the first transistor to the active pattern T81 of the eighth transistor are an integral structure connected to each other, and the active pattern T91 of the ninth transistor is separately provided.

[0304] In an exemplary embodiment, in the first direction D1, the active pattern T21 of the second transistor, the active pattern T61 of the sixth transistor, and the active pattern T71 of the seventh transistor may be located on the same side of the active pattern T31 of the third transistor T3, the active pattern T41 of the fourth transistor and the active pattern T51 of the fifth transistor may be located on the same side of the active pattern T31 of the third transistor T3, and the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor may be located on different sides of the active pattern T31 of the third transistor T3. In the second direction D2, the active pattern T11 of the first transistor, the active pattern T21 of the second transistor, and the active pattern T41 of the fourth transistor in the M-th row of sub-pixels may be located on a side of the active pattern T31 of the third transistor T3 close to the M-1-th row of sub-pixels, and the active pattern T51 of the fifth transistor, the active pattern T61 of the sixth transistor, the active pattern T71 of the seventh transistor, the active pattern T81 of the eighth transistor, and the active pattern T91 of the ninth transistor in the M-th row of sub-pixels may be located on a side of the active pattern T31 of the third transistor T3 close to the M+1-th row of sub-pixels. The active pattern T91 of the ninth transistor is located between the active pattern T71 of the seventh transistor and the active pattern T81 of the eighth transistor.

[0305] In an exemplary embodiment, the active pattern T11 of the first transistor, the active pattern T41 of the fourth transistor, the active pattern T51 of the fifth transistor, the active pattern T61 of the sixth transistor, the active pattern T71 of the seventh transistor, and the active pattern T91 of the ninth transistor may be in an "I" shape, the active pattern T21 of the second transistor may be in an "n" shape, the active pattern 13 of the third transistor T3 may be in an inverted "Ω" shape, and the active pattern T81 of the eighth transistor may be in an "L" shape.

[0306] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the second region T11-2 of the active pattern T11 of the first transistor may serve as the first region T21-1 of the active pattern T21 of the second transistor, the first region T31-1 of the active pattern T31 of the third transistor T3 may serve as the second region T41-2 of the active pattern T41 of the fourth transistor and the second region T51-2 of the active pattern T51 of the fifth transistor, and the second region T31-2 of the active pattern T31 of the third transistor T3 may serve as the second region T21-2 of the active pattern T21 of the second transistor and the first region T61 of the active pattern T61 of the sixth transistor. Area T61-1, the first area T51-1 of the active pattern T51 of the fifth transistor can be used as the first area T81-1 of the active pattern T81 of the eighth transistor, the second area T61-2 of the active pattern T61 of the sixth transistor can be used as the second area T71-2 of the active pattern T71 of the seventh transistor, the first area T41-1 of the active pattern T41 of the fourth transistor, the second area T81-2 of the active pattern T81 of the eighth transistor, the first area T91-1 of the active pattern T91 of the ninth transistor and the second area T91-2 of the active pattern T91 of the ninth transistor can be set separately.

[0307] In an exemplary embodiment, the first connection line L1 is located on a side of the active pattern T11 of the first transistor away from the active pattern T31 of the third transistor T3, and the shape of the first connection line L1 can be a line shape in which the main part extends along the first direction D1, and the first connection line L1 is an integrated structure with the first region T11-1 of the active pattern T11 of the first transistor.

[0308] In an exemplary embodiment, the second connection line L2 is located on a side of the active pattern T71 of the seventh transistor away from the active pattern T31 of the third transistor T3, and the shape of the second connection line L2 can be a line shape in which the main part extends along the first direction D1, and the second connection line L2 is an integrated structure with the first area T71-1 of the active pattern T71 of the seventh transistor.

[0309] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate formed with the aforementioned pattern, patterning the second insulating film and the first conductive film through a patterning process to form a second insulating layer pattern and a first conductive layer pattern located on the second insulating layer, such as Fig.21 and Fig. 22 As shown, Fig.21 for Fig.19 Schematic diagram of the first conductive layer pattern, Fig. 22 for Fig.19Schematic diagram after forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0310] In an exemplary embodiment, the first conductive layer pattern may include: a first light emitting signal line EM1 and control electrodes T12 to T92 of first to ninth transistors in at least one pixel driving circuit, a second plate C12 of a first capacitor, and a second plate C22 of a second capacitor.

[0311] In an exemplary embodiment, the shape of the first light emitting signal line EM1 may be a line shape in which the main part extends along the first direction D1. The area where the first light emitting signal line EM1 overlaps with the active pattern of the fifth transistor serves as the control electrode T52 of the fifth transistor. The area where the first light emitting signal line EM1 overlaps with the active pattern of the sixth transistor serves as the control electrode T62 of the sixth transistor.

[0312] In an exemplary embodiment, the shape of the second plate C12 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The second plate C12 of the first capacitor of the Mth row pixel driving circuit is located on the side of the first light-emitting signal line EM1 connected to the Mth row pixel driving circuit close to the M-1th row pixel driving circuit.

[0313] In an exemplary embodiment, the shape of the second plate C22 of the second capacitor may be rectangular, and the corners of the rectangle may be chamfered. The second plate C22 of the second capacitor of the Mth row of pixel driving circuits is located on a side of the second plate C12 of the first capacitor of the Mth row of pixel driving circuits close to the M-1th row of pixel driving circuits.

[0314] In an exemplary embodiment, the control electrode T72 of the seventh transistor and the control electrode T92 of the ninth transistor are an integrated structure connected to each other. The integrated structure of the control electrode T72 of the seventh transistor and the control electrode T92 of the ninth transistor extends along the first direction D1. The integrated structure of the control electrode T72 of the seventh transistor and the control electrode T92 of the ninth transistor of the M-th row pixel driving circuit is located on a side of the control electrode T82 of the eighth transistor in the M-th row pixel driving circuit close to the M+1-th row pixel driving circuit.

[0315] In an exemplary embodiment, the control electrode T82 of the eighth transistor is separately provided. The control electrode T82 of the eighth transistor extends along the second direction D2. The control electrode T82 of the eighth transistor of the M-th row pixel driving circuit is located on a side of the first light emitting signal line EM1 connected to the M-th row pixel driving circuit close to the M+1-th row pixel driving circuit.

[0316] In an exemplary embodiment, the control electrode T12 of the first transistor is arranged across the active pattern of the first transistor, the control electrode T22 of the second transistor is arranged across the active pattern of the second transistor, the control electrode T32 of the third transistor T3 is arranged across the active pattern of the third transistor T3, the control electrode T42 of the fourth transistor is arranged across the active pattern of the fourth transistor, the control electrode T52 of the fifth transistor is arranged across the active pattern of the fifth transistor, the control electrode T62 of the sixth transistor is arranged across the active pattern of the sixth transistor, the control electrode T72 of the seventh transistor is arranged across the active pattern of the seventh transistor, the control electrode T82 of the eighth transistor is arranged across the active pattern of the eighth transistor, and the control electrode T92 of the ninth transistor is opened on the active pattern of the ninth transistor, that is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0317] In an exemplary embodiment, this process also includes a conductorization process. The conductorization process is to use the semiconductor layer in the control electrode shielding area of ​​multiple transistors (i.e., the area where the semiconductor layer overlaps the control electrode) as the channel area of ​​the transistor after forming the first conductive layer pattern, and the semiconductor layer in the area not shielded by the first conductive layer is processed into a conductorization layer. The first connecting line can be reused as the first initial signal line INIT1 and the first electrode T13 of the first transistor, the second connecting line can be reused as the second initial signal line INIT2 and the first electrode T73 of the seventh transistor, and the second area of ​​the active pattern T31 of the third transistor T3 (also the second area of ​​the active pattern of the second transistor and the first area of ​​the active pattern of the sixth transistor) can be used as the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor T3 and the first electrode T63 of the sixth transistor)

[0318] In an exemplary embodiment, the first light emitting signal line EM1 may be a straight line, or may be a broken line, which is not limited in the present disclosure.

[0319] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third insulating film and the second conductive film through a patterning process to form a third insulating layer pattern and a second conductive layer pattern located on the third insulating layer, Fig.23 and Fig.24 As shown, Fig.23 for Fig.19 Schematic diagram of the second conductive layer pattern, Fig.24 for Fig.19 Schematic diagram after forming a second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0320] In an exemplary embodiment, the second conductive layer pattern includes at least a shielding electrode SL, a first plate C11 of a first capacitor, and a first plate C21 of a second capacitor.

[0321] In an exemplary embodiment, the shielding electrode SL is in an "L" shape, and the orthographic projection of the shielding electrode SL on the substrate at least partially overlaps with the orthographic projection of the first connection line and the active pattern of the second transistor on the substrate. The shielding electrode SL is configured to effectively shield the influence of the data voltage jump on the key nodes in the pixel driving circuit, prevent the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit, and improve the display effect.

[0322] In an exemplary embodiment, the first plate C11 of the first capacitor and the first plate C21 of the second capacitor are an integrated structure. The outline of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor on the substrate overlaps at least partially with the orthographic projection of the second plate of the first capacitor and the second plate of the second capacitor (also the control electrode of the third transistor T3) on the substrate.

[0323] The first opening H1 and the second opening H2 are provided on the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor. The first opening H1 may be in the shape of a rectangle and may be located in the middle of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor. The first opening H1 exposes the third insulating layer covering the second plate of the second capacitor (also the control electrode of the third transistor T3), and the orthographic projection of the second plate of the second capacitor (also the control electrode of the third transistor T3) on the substrate includes the orthographic projection of the first opening H1 on the substrate. The second opening H2 may be in the shape of a rectangle and may be located in the middle of the integrated structure of the first plate C11 of the first capacitor and the first plate C21 of the second capacitor. The second opening H2 exposes the third insulating layer covering the second plate of the first capacitor, and the orthographic projection of the second plate of the first capacitor on the substrate includes the orthographic projection of the second opening H2 on the substrate.

[0324] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the second conductive layer, wherein a plurality of via holes are disposed on the fourth insulating layer pattern, such as Fig.25 shown. Fig.25 for Fig.19 Schematic diagram after forming the fourth insulation layer pattern.

[0325] In an exemplary embodiment, a plurality of vias are provided on the fourth insulation layer pattern, including at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17 and an eighteenth via V18.

[0326] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first initial signal line, and the first via hole V1 is configured to connect a subsequently formed connecting electrode to the first initial signal line through the via hole.

[0327] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) on the substrate, the third insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor), and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) through the via.

[0328] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third transistor T3 (also the second area of ​​the active pattern of the fourth transistor and the second area of ​​the active pattern of the fifth transistor) on the substrate, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the active pattern of the third transistor T3 (also the second area of ​​the active pattern of the fourth transistor and the second area of ​​the active pattern of the fifth transistor), and the third via hole V3 is configured to connect the first electrode of the subsequently formed third transistor T3 (also the second electrode of the fourth transistor, the second electrode of the fifth transistor and the second electrode of the ninth transistor) to the first area of ​​the active pattern of the third transistor T3 (also the second area of ​​the active pattern of the fourth transistor and the second area of ​​the active pattern of the fifth transistor) through the via hole.

[0329] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the fourth via hole V4 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via hole.

[0330] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor) on the substrate, the third insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor), and the fifth via V5 is configured to connect a subsequently formed power connection line to the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor) through the via.

[0331] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) on the substrate, the third insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor), and the sixth via V6 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) through the via.

[0332] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighth transistor on the substrate, the third insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the second area of ​​the active pattern of the eighth transistor, and the seventh via V7 is configured to connect the second electrode of the subsequently formed eighth transistor to the second area of ​​the active pattern of the eighth transistor through the via.

[0333] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the ninth transistor on the substrate, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first area of ​​the active pattern of the ninth transistor, and the eighth via V8 is configured to connect a subsequently formed reference signal line to the first area of ​​the active pattern of the ninth transistor through the via.

[0334] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the ninth transistor on the substrate, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the second area of ​​the active pattern of the ninth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed third transistor T3 (which is also the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second electrode of the ninth transistor) to the second area of ​​the active pattern of the ninth transistor through the via.

[0335] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor on the substrate, the third insulating layer in the tenth via hole V10 is etched away to expose the surface of the control electrode of the first transistor, and the tenth via hole V10 is configured to connect a subsequently formed first reset signal line to the control electrode of the first transistor through the via hole.

[0336] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the third insulating layer in the eleventh via hole V11 is etched away to expose the surface of the control electrode of the second transistor, and the eleventh via hole V11 is configured to connect a subsequently formed third reset signal line to the control electrode of the second transistor through the via hole.

[0337] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the first opening on the substrate, the third insulating layer in the twelfth via hole V12 is etched away to expose the surface of the second electrode plate of the second capacitor (also the control electrode of the third transistor T3), and the twelfth via hole V12 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second electrode plate of the second capacitor (also the control electrode of the third transistor T3) through the via hole.

[0338] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor on the substrate, the third insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the control electrode of the fourth transistor, and the thirteenth via hole V13 is configured to connect a subsequently formed scanning signal line to the control electrode of the fourth transistor through the via hole.

[0339] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor (also the control electrode of the ninth transistor) on the substrate, the third insulating layer in the fourteenth via V14 is etched away to expose the surface of the control electrode of the seventh transistor (also the control electrode of the ninth transistor), and the fourteenth via V14 is configured to connect a subsequently formed second reset signal line to the control electrode of the seventh transistor (also the control electrode of the ninth transistor) through the via.

[0340] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the control electrode of the eighth transistor on the substrate, the third insulating layer in the fifteenth via V15 is etched away to expose the surface of the control electrode of the eighth transistor, and the fifteenth via V15 is configured to connect a subsequently formed fourth reset signal line to the control electrode of the eighth transistor through the via.

[0341] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second opening on the substrate, the third insulating layer in the sixteenth via hole V16 is etched away to expose the surface of the second electrode plate of the first capacitor, and the sixteenth via hole V16 is configured to connect the first electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second electrode of the ninth transistor) to the second electrode plate of the first capacitor through the via hole.

[0342] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first plate of the first capacitor (also the first plate of the second capacitor) on the substrate, exposing the surface of the first plate of the first capacitor (also the first plate of the second capacitor), and the seventeenth via V17 is configured to connect the second electrode of the subsequently formed eighth transistor to the first plate of the first capacitor (also the first plate of the second capacitor) through the via.

[0343] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is within the range of the orthographic projection of the shielding electrode on the substrate, exposing the surface of the shielding electrode. The eighteenth via hole V18 is configured to connect a subsequently formed connecting electrode to the shielding electrode through the via hole.

[0344] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern disposed on the fourth insulating layer, such as Fig.26 and Fig. 27 As shown, Fig.26 for Fig.19 Schematic diagram of the third conductive layer pattern, Fig. 27 for Fig.19 Schematic diagram after forming the third conductive layer pattern. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0345] In an exemplary embodiment, the third conductive layer pattern may at least include: a first reset signal line Reset1, a second reset signal line Reset2, a third reset signal line Reset3, a fourth reset signal line Reset4, a scan signal line Gate, a reference signal line REF, a power connection line VDL, and a connection electrode EL located in at least one pixel driving circuit, a second electrode T14 of the first transistor, a first electrode T23 of the second transistor, a first electrode T33 of the third transistor T3, a first electrode T43 and a second electrode T44 of the fourth transistor, a first electrode T53 and a second electrode T54 of the fifth transistor, a second electrode T64 of the sixth transistor, a second electrode T74 of the seventh transistor, a first electrode T83 and a second electrode T84 of the eighth transistor, and a first electrode T93 and a second electrode T94 of the ninth transistor.

[0346] In an exemplary embodiment, the first reset signal line Reset1 , the third reset signal line Reset3 , the scan signal line Gate, the power connection line VDL, the fourth reset signal line Reset4 , the second reset signal line Reset2 , and the reference signal line REF are sequentially arranged along the second direction D2 .

[0347] In an exemplary embodiment, an orthographic projection of the reference signal line REF on the substrate is located between an orthographic projection of the second reset signal line Reset2 on the substrate and an orthographic projection of the second initial signal line on the substrate.

[0348] In an exemplary embodiment, an orthographic projection of the first reset signal line Reset1 on the substrate is located between an orthographic projection of the third reset signal line Reset3 on the substrate and an orthographic projection of the first initial signal line on the substrate.

[0349] In an exemplary embodiment, an orthographic projection of the light emitting signal line on the substrate is located between an orthographic projection of the scanning signal line on the substrate and an orthographic projection of the power connection line VDL on the substrate.

[0350] In an exemplary embodiment, the shape of the first reset signal line Reset1 may be a line shape in which a main portion extends along the first direction D1 , and the first reset signal line Reset1 is connected to the control electrode of the first transistor through a tenth via hole.

[0351] In an exemplary embodiment, the second reset signal line Reset2 may be in a line shape with a main portion extending along the first direction D1 , and the second reset signal line Reset2 is connected to the control electrode of the seventh transistor (also the control electrode of the ninth transistor) through the fourteenth via hole.

[0352] In an exemplary embodiment, the third reset signal line Reset3 may have a line shape in which a main portion extends along the first direction D1 , and the third reset signal line Reset3 is connected to the control electrode of the second transistor through an eleventh via hole.

[0353] In an exemplary embodiment, the fourth reset signal line Reset4 may have a line shape in which a main portion extends along the first direction D1 , and the fourth reset signal line Reset4 is connected to the control electrode of the eighth transistor through the fifteenth via hole.

[0354] In an exemplary embodiment, the shape of the scan signal line Gate may be a line shape in which a main portion extends along the first direction D1, and the scan signal line Gate is connected to the control electrode of the fourth transistor through the thirteenth via hole.

[0355] In an exemplary embodiment, the power connection line VDL may be in the shape of a line whose main body portion extends along the first direction D1, and the power connection line VDL is connected to the first region of the active pattern of the fifth transistor (also the first region of the active pattern of the eighth transistor) through the fifth via hole. The region where the power connection line VDL overlaps with the first region of the active pattern of the fifth transistor (also the first region of the active pattern of the eighth transistor) serves as the first electrode of the fifth transistor (also the first electrode of the eighth transistor).

[0356] In an exemplary embodiment, the reference signal line REF may be in the shape of a line whose main portion extends along the first direction D1, and the reference signal line REF is connected to the first region of the active pattern of the ninth transistor through the eighth via hole. The region where the reference signal line REF overlaps with the first region of the active pattern of the ninth transistor serves as the first electrode T93 of the ninth transistor.

[0357] In an exemplary embodiment, the connection electrode EL is located on a side of the first reset signal line Reset1 away from the third reset signal line Reset3, the first electrode T43 of the fourth transistor is located between the first reset signal line Reset1 and the third reset signal line Reset3, and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T33 of the third transistor T3, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, the second electrode T64 of the sixth transistor, the second electrode T74 of the seventh transistor, the second electrode T84 of the eighth transistor, and the second electrode T94 of the ninth transistor are located between the scan signal line Gate and the power connection line VDL.

[0358] In an exemplary embodiment, the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are an integrated structure. The shape of the integrated structure of the second electrode T14 of the first transistor and the first electrode T23 of the second transistor is a strip extending along the second direction D2. The second electrode T14 of the first transistor (also the first electrode T23 of the second transistor) is connected to the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) through the second via hole, and is connected to the second electrode plate of the second capacitor (also the control electrode of the third transistor T3) through the twelfth via hole.

[0359] In an exemplary embodiment, the first electrode T43 of the fourth transistor is separately provided and has a strip shape extending along the first direction D1. The first electrode T43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a fourth via hole.

[0360] In an exemplary embodiment, the first electrode T33 of the third transistor T3, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode T94 of the ninth transistor are an integrated structure. The integrated structure of the first electrode T33 of the third transistor T3, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode T94 of the ninth transistor is in the shape of a “┌” character. The first electrode T33 of the third transistor T3 (also the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode T94 of the ninth transistor) is connected to the first area of ​​the active pattern of the third transistor T3 (also the second area of ​​the active pattern of the fourth transistor and the second area of ​​the active pattern of the fifth transistor) through the third via hole, connected to the second area of ​​the active pattern of the ninth transistor through the ninth via hole, and connected to the second plate of the first capacitor through the sixteenth via hole.

[0361] In an exemplary embodiment, the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor are an integral structure. The shape of the integral structure of the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor extends along the second direction D2. The second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) is connected to the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) through the sixth via.

[0362] In an exemplary embodiment, the second electrode T84 of the eighth transistor is separately provided. The second electrode T84 of the eighth transistor may be in the shape of a strip extending along the second direction D2. The second electrode T84 of the eighth transistor is connected to the second region of the active pattern of the eighth transistor through the seventh via hole, and is connected to the first electrode plate of the first capacitor (also the first electrode plate of the second capacitor) through the seventeenth via hole.

[0363] In an exemplary embodiment, the connection electrode EL is provided separately. The connection electrode EL may be in the shape of a strip extending along the first direction D1. The connection electrode EL is electrically connected to the first initial signal line through the first via hole, and is electrically connected to the shielding electrode through the eighteenth via hole.

[0364] In an exemplary embodiment, an orthographic projection of the shielding electrode on the substrate at least partially overlaps with orthographic projections of the first reset signal line Reset1 , the third reset signal line Reset3 , and the scan signal line Gate on the substrate.

[0365] In an exemplary embodiment, the scanning signal line Gate, the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the fourth reset signal line Reset4, the reference signal line REF and the power connection line VDL can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0366] (6) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein the first planar layer is provided with a plurality of via holes, such as Fig.28 As shown, Fig.28 for Fig.19 Schematic diagram after forming the first planarization layer pattern.

[0367] In an exemplary embodiment, the plurality of via holes on the first planarization layer pattern includes at least nineteenth to twenty-first via holes V19 to V21 .

[0368] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fifth insulating layer in the nineteenth via V19 is etched away to expose the surface of the first electrode of the fourth transistor, and the nineteenth via V19 is configured to connect the subsequently formed data signal line through the via to the first electrode of the fourth transistor.

[0369] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the fifth insulating layer in the twentieth via V20 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the twentieth via V20 is configured to connect the subsequently formed anode connecting electrode through the via to the second electrode of the sixth transistor (also the second electrode of the seventh transistor).

[0370] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the power connection line on the substrate, the fifth insulating layer in the twenty-first via V21 is etched away to expose the surface of the power connection line, and the twenty-first via V21 is configured to connect the subsequently formed first power line to the power connection line.

[0371] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern disposed on the fourth insulating layer, such as Fig.29 and Fig.30 As shown, Fig.29 for Fig.19 Schematic diagram of the fourth conductive layer pattern, Fig.30 for Fig.19 Schematic diagram after forming a fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0372] In an exemplary embodiment, the fourth conductive layer pattern includes at least a data signal line Data, a first power line VDD, and an anode connection electrode AL located at at least one pixel driving circuit.

[0373] In an exemplary embodiment, the shape of the first power line VDD may be a line shape in which a main body portion extends along the second direction D2. The first power line VDD is connected to the power connection line through the twenty-first via hole.

[0374] In an exemplary embodiment, the shape of the data signal line Data may be a line shape in which a main portion extends along the second direction D2. The data signal line Data is connected to the first electrode of the fourth transistor through the nineteenth via hole.

[0375] In an exemplary embodiment, a line width of the first power line VDD is greater than a line width of the data signal line Data.

[0376] In an exemplary embodiment, the anode connection electrode AL may be in the shape of a bar with a main portion extending along the second direction D2. The anode connection electrode AL is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the twentieth via hole.

[0377] (8) Forming a second flat layer pattern. In an exemplary embodiment, forming the second flat layer pattern may include: coating a second flat film on the substrate on which the aforementioned pattern is formed, patterning the second flat film using a patterning process to form a second flat layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the second flat layer. The positive projection of the anode via hole on the second flat layer pattern on the substrate is within the range of the positive projection of the anode connection electrode on the substrate, the second flat layer in the anode via hole is removed, exposing the surface of the anode connection electrode, and the anode via hole is configured to connect the subsequently formed anode to the anode connection electrode through the via hole.

[0378] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer can be a pixel drive circuit, and the pixel drive circuit is connected to the first reset signal line, the second reset signal line, the third reset signal line, the fourth reset signal line, the light emitting signal line, the first initial signal line, the second initial signal line, the reference signal line, the data signal line and the first power supply line. In a plane perpendicular to the display substrate, the drive circuit layer can be arranged on the substrate.

[0379] The driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer and a second flat layer sequentially arranged on the substrate. The semiconductor layer may include at least an active pattern of at least one transistor, a first initial signal line and a second initial signal line, the first conductive layer may include at least gate electrodes of the first transistor to the ninth transistor, a second plate of the first capacitor, a second plate of the third capacitor and a light-emitting signal line, the second conductive layer may include at least a shielding electrode, a first plate of the first capacitor and a first plate of the second capacitor, the shielding electrode is electrically connected to the first initial signal line, the third conductive layer may include at least: first and second electrodes of a plurality of transistors, a first reset signal line, a second reset signal line, a third reset signal line, a fourth reset signal line, a power connection line, a scanning signal line, a reference signal line, and the power connection line is electrically connected to the first power supply. The fourth conductive layer may include at least: a data signal line, a first power line and an anode connection electrode.

[0380] In an exemplary embodiment, the semiconductor layer may be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0381] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0382] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer, the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer may be referred to as a passivation (PVX) layer.

[0383] In an exemplary embodiment, the first planarization layer and the second planarization layer may employ an organic material such as resin or the like.

[0384] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0385] Forming a light-emitting structure layer. In an exemplary embodiment, forming the light-emitting structure layer includes: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, patterning the anode conductive film by a patterning process to form an anode conductive layer pattern, depositing a pixel definition film on a substrate on which the aforementioned pattern is formed, patterning the pixel definition film by a patterning process to form a pixel definition layer pattern exposing the anode layer pattern, coating an organic light-emitting material on a substrate on which the pixel definition layer pattern is formed, patterning the organic light-emitting material by a patterning process to form an organic structure layer pattern, and depositing a cathode conductive film on a substrate on which an organic material layer pattern is formed, patterning the cathode conductive film by a patterning process to form a cathode conductive layer.

[0386] In an exemplary embodiment, the anode conductive layer pattern may include at least: anodes of a plurality of light emitting devices.

[0387] In an exemplary embodiment, the organic structure layer pattern may include at least: an organic light emitting layer of the light emitting device.

[0388] In an exemplary embodiment, the cathode conductive layer pattern may include at least cathodes of a plurality of light emitting devices.

[0389] In an exemplary embodiment, the anode conductive layer may use a transparent conductive material such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0390] In an exemplary embodiment, the cathode conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.

[0391] In an exemplary embodiment, the display device can be: electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, or any other product or component with display function.

[0392] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0393] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0394] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A pixel driving circuit, characterized in that: include: A driving subcircuit, a light emitting control subcircuit, a storage subcircuit, a first control subcircuit and a second control subcircuit; A driving subcircuit, electrically connected to the first node, the second node and the third node respectively, and configured to provide a driving signal to the third node under the control of signals of the first node and the second node; a light-emitting control subcircuit, electrically connected to at least one light-emitting signal line, and configured to output a driving signal under the control of a signal of at least one light-emitting signal line; A first control subcircuit is electrically connected to at least one reset signal line, the first node and the third node respectively, and is configured to connect the first node and the third node under the control of a signal of the at least one reset signal line; a second control subcircuit, electrically connected to the fourth reset signal line, the first power line and the fifth node, respectively, and configured to provide the signal of the first power line to the fifth node under the control of the signal of the fourth reset signal line; The storage sub-circuit is electrically connected to the first node, the second node and the fifth node, respectively, and is configured to store a voltage difference of a signal between the first node, the second node and the fifth node.

2. The pixel driving circuit according to claim 1, characterized in that: The storage subcircuit comprises: a first capacitor and a second capacitor; The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the second node; The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the first node.

3. The pixel driving circuit according to claim 1, characterized in that: The second control subcircuit comprises: an eighth transistor; A control electrode of the eighth transistor is electrically connected to the fourth reset signal line, a first electrode of the eighth transistor is electrically connected to the first power line, and a second electrode of the eighth transistor is electrically connected to the fifth node.

4. The pixel driving circuit according to claim 3, characterized in that: The first control subcircuit is also electrically connected to the reference signal line, the second node and the first initial signal line, and is configured to provide the signal of the reference signal line to the second node and provide the signal of the first initial signal line to the first node or the third node under the control of the signal of at least one reset signal line.

5. The pixel driving circuit according to claim 4, characterized in that: The at least one reset signal line includes: at least one of a first reset signal line, a second reset signal line and a third reset signal line; The first control subcircuit includes: a first transistor, a second transistor and a ninth transistor; The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to one of the first node and the third node; The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node; The control electrode of the ninth transistor is electrically connected to the second reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

6. The pixel driving circuit according to claim 5, characterized in that: The second reset signal line and the third reset signal line are different signal lines, or are the same signal line.

7. The pixel driving circuit according to claim 6, characterized in that: Also includes: a third control subcircuit; The third control subcircuit is electrically connected to the fifth reset signal line, the second initial signal line and the fourth node respectively, and is configured to provide the signal of the second initial signal line to the fourth node under the control of the signal of the fifth reset signal line; The third control subcircuit comprises: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the fifth reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node; The fifth reset signal line is the same signal line as one of the second reset signal line and the fourth reset signal line.

8. The pixel driving circuit according to claim 4, characterized in that: Also includes: Write subcircuit; The writing subcircuit is electrically connected to the scanning signal line, the data signal line and the second node respectively, and is configured to provide the signal of the data signal line to the second node under the control of the signal of the scanning signal line; The light emitting control subcircuit is also electrically connected to the first power line, the second node, the third node and the fifth node; At least one light emitting signal line includes: a first light emitting signal line, the driving sub-circuit includes: a third transistor, the writing sub-circuit includes: a fourth transistor, and the light emitting control sub-circuit includes: a fifth transistor and a sixth transistor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the scan signal line, and the first electrode of the fourth transistor is electrically connected to the data signal line. The second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the first light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the first light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

9. The pixel driving circuit according to claim 3, characterized in that: The at least one reset signal line includes: at least one of a first reset signal line and a third reset signal line; The first control subcircuit includes: a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to one of the first node and the third node; The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

10. The pixel driving circuit according to claim 3, characterized in that: The at least one reset signal line comprises: a third reset signal line; The first control subcircuit includes: a second transistor; The control electrode of the second transistor is electrically connected to the third reset signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

11. The pixel driving circuit according to claim 9 or 10, characterized in that: Also includes: a third control subcircuit; The third control subcircuit is electrically connected to the fifth reset signal line, the second initial signal line and the fourth node respectively, and is configured to provide the signal of the second initial signal line to the fourth node under the control of the signal of the fifth reset signal line; The fifth reset signal line is the same signal line as the fourth reset signal line, or is a different signal line from at least one of the first reset signal line, the third reset signal line and the fourth reset signal line.

12. The pixel driving circuit according to claim 11, characterized in that: Also includes: Write subcircuit; The writing subcircuit is electrically connected to the scanning signal line, the data signal line and the second node respectively, and is configured to provide the signal of the data signal line to the second node under the control of the signal of the scanning signal line; The light emitting control subcircuit is also electrically connected to the first power line, the second node, the third node and the fifth node; At least one light emitting signal line includes: a first light emitting signal line and a second light emitting signal line, the driving subcircuit includes: a third transistor, the writing subcircuit includes: a fourth transistor, and the light emitting control subcircuit includes: a fifth transistor and a sixth transistor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; A control electrode of the fourth transistor is electrically connected to the scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the first light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the second light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

13. The pixel driving circuit according to claim 1, characterized in that: Also includes: A writing subcircuit, the writing subcircuit is electrically connected to the scanning signal line and comprises: a fourth transistor, the first control subcircuit comprises: a second transistor, the second transistor is electrically connected to the first node and the third node respectively; A time period during which the signal of the scanning signal line connected to the control electrode of the fourth transistor is an effective level signal does not overlap with a time period during which the signal of the reset signal line connected to the control electrode of the second transistor is an effective level signal.

14. The pixel driving circuit according to claim 13, characterized in that: The start time of a time period in which the signal of the scanning signal line connected to the control electrode of the fourth transistor is a valid level signal is later than the end time of a time period in which the signal of the reset signal line connected to the control electrode of the second transistor is a valid level signal.

15. The pixel driving circuit according to claim 1, characterized in that: Also includes: Bias subcircuit; The bias subcircuit is electrically connected to at least one of the second node and the third node, the first reset signal line and the bias signal line, respectively, and is configured to provide a signal of the bias signal line to one of the second node and the third node under the control of a signal of the first reset signal line; The bias subcircuit includes: a tenth transistor; A control electrode of the tenth transistor is electrically connected to the first reset signal line, a first electrode of the tenth transistor is electrically connected to the bias signal line, and a second electrode of the tenth transistor is electrically connected to one of the second node and the third node.

16. A display device, characterized in that: include: A pixel driving circuit as claimed in any one of claims 1 to 15.

17. The display device according to claim 16, characterized in that: The device further comprises: a substrate and a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines, a plurality of scan signal lines, a plurality of reference signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of light-emitting signal lines, a plurality of first power lines, a plurality of data signal lines and a plurality of power connection lines arranged on the substrate, wherein at least one power connection line is electrically connected to at least one first power line; At least one of the first reset signal line, the second reset signal line, the third reset signal line, the fourth reset signal line, the light emitting signal line, the first initial signal line, the second initial signal line, the reference signal line and the power connection line extends at least partially along the first direction, and at least one of the first power line and the data signal line extends at least partially along the second direction, and the first direction and the second direction intersect; The orthographic projection of the first initial signal line on the substrate, the orthographic projection of the first reset signal line on the substrate, the orthographic projection of the third reset signal line on the substrate, the orthographic projection of the scanning signal line on the substrate, the orthographic projection of the luminous signal line on the substrate, the orthographic projection of the fourth reset signal line on the substrate, the orthographic projection of the second reset signal line on the substrate, the orthographic projection of the reference signal line on the substrate and the orthographic projection of the second initial signal line on the substrate are arranged in sequence along the second direction, and the orthographic projection of the power connection line on the substrate is located between the orthographic projection of the luminous signal line on the substrate and the orthographic projection of the fourth reset signal line on the substrate.

18. The display device according to claim 17, characterized in that: Also includes: A driving circuit layer, the driving circuit layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the pixel driving circuit comprising: at least one transistor and at least one capacitor, the transistor comprising: an active pattern, a control electrode, a first electrode and a second electrode, the capacitor comprising: a first electrode plate and a second electrode plate; The semiconductor layer includes: a first initial signal line, a second initial signal line, and an active pattern of at least one transistor located in at least one pixel driving circuit; The first conductive layer includes: a light emitting signal line, a control electrode of at least one transistor located in at least one pixel driving circuit, and a second electrode plate of at least one capacitor; The second conductive layer includes: a first plate of at least one capacitor located in at least one pixel driving circuit; The third conductive layer includes: a first reset signal line, a second reset signal line, a third reset signal line, a fourth reset signal line, a scan signal line, a reference signal line, a power connection line, and a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit; The fourth conductive layer includes: a data signal line and a first power line.

19. The display device according to claim 18, characterized in that Also includes: a shielding electrode located in the second conductive layer, the shielding electrode being electrically connected to the first initial signal line; The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projections of the first initial signal line, the first reset signal line, the third reset signal line and the scan signal line on the substrate.

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