A gate negative voltage half-bridge driving circuit

Abstract

The utility model provides a gate negative voltage half-bridge driving circuit, which includes: a gate driver U1, a power half-bridge circuit, a high-side negative voltage shutdown circuit, a low-side negative voltage shutdown circuit and a bootstrap circuit; the high-side negative voltage shutdown circuit is respectively connected to the VS pin of the gate driver U1, the source of the high-side MOS tube Q1, and the bootstrap circuit. When the high-side MOS tube Q1 is turned off, the HO pin of the gate driver U1 is connected to the VS pin, and the high-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the high-side MOS tube Q1; the low-side negative voltage shutdown circuit is respectively connected to the source of the low-side MOS tube Q2, the VCC pin and the COM pin of the gate driver U1. When the low-side MOS tube Q2 is turned off, the LO pin of the gate driver U1 is connected to the COM pin, and the low-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the low-side MOS tube Q2.

Description

Technical Field

[0001] The utility model relates to the technical field of servo drive control hardware, in particular to a gate negative voltage half-bridge drive circuit. Background Art

[0002] At present, the half-bridge drive circuit of the existing power switch tube is designed by matching the parameters of the peripheral circuit based on the parameters of the driver chip itself. High power levels and fast switching devices will cause large voltage transients di / dt and current transients di / dt at each switching moment. The voltage transient di / dt of the switch interacts with the parasitic Miller capacitor Cgd, causing current to flow through the gate and may cause mis-conduction. Therefore, while ensuring a high switching speed, it is necessary to prevent mis-conduction caused by large voltage transients di / dt and current transients di / dt due to excessive switching speed. Generally speaking, a resistor is connected to the gate terminal of a MOSFET (Metal-Oxide-SemiconductorField-EffectTransistor) or an RC filter circuit is added to suppress the peak current and reduce the output ringing. However, a larger gate resistor will reduce the switching speed of the MOSFET, resulting in increased power loss, reduced performance, and potential heating problems. On the contrary, a smaller gate resistor will increase the switching speed of the MOSFET, but due to crosstalk, the gate voltage of the power tube device will oscillate, resulting in false turn-on of the tube, thus causing direct fault and damage to the power tube. Utility Model Content

[0003] The present application provides a gate negative voltage half-bridge drive circuit, which uses a charge pump to establish a gate negative voltage to avoid parasitic turn-on of a power switch tube, thereby solving the problem in the prior art of interference with the power tube and misleading turn-on due to rapid voltage transients dv / dt and current transients di / dt, which in turn causes direct conduction of the upper and lower tubes.

[0004] According to an embodiment of the present application, a gate negative voltage half-bridge driving circuit is provided, comprising: a gate driver U1, a power half-bridge circuit, a high-side negative voltage shutdown circuit, a low-side negative voltage shutdown circuit and a bootstrap circuit;

[0005] The power half-bridge circuit is respectively connected to the HO pin and the LO pin of the gate driver U1, and the power half-bridge circuit includes a high-side MOS transistor Q1 and a low-side MOS transistor Q2, the drain of the high-side MOS transistor Q1 is connected to the DC voltage VDC, the source of the high-side MOS transistor Q1 is electrically connected to the drain of the low-side MOS transistor Q2, and the source of the low-side MOS transistor Q2 is grounded;

[0006] The bootstrap circuit is connected to the VB pin of the gate driver U1, and generates a high-side bias signal through the bootstrap circuit to drive the gate of the high-side MOS tube Q1 based on the switch node;

[0007] The high-side negative voltage shutdown circuit is respectively connected to the VS pin of the gate driver U1, the source of the high-side MOS tube Q1, and the bootstrap circuit. When the high-side MOS tube Q1 is turned off, the HO pin of the gate driver U1 is connected to the VS pin, and the high-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the high-side MOS tube Q1;

[0008] The low-side negative voltage shutdown circuit is respectively connected to the source of the low-side MOS tube Q2, the VCC pin and the COM pin of the gate driver U1. When the low-side MOS tube Q2 is turned off, the LO pin of the gate driver U1 is connected to the COM pin, and the low-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the low-side MOS tube Q2.

[0009] In some embodiments of the present application, the power half-bridge circuit also includes a resistor R3 and a resistor R5, one end of the resistor R3 is electrically connected to the HO pin of the gate driver U1, and the other end of the resistor R3 is electrically connected to the gate of the high-side MOS tube Q1, one end of the resistor R5 is electrically connected to the LO pin of the gate driver U1, and the other end of the resistor R5 is electrically connected to the gate of the low-side MOS tube Q2.

[0010] In some embodiments of the present application, the power half-bridge circuit also includes a Zener diode D2, a resistor R2, a Zener diode D3 and a resistor R4, the negative electrode of the Zener diode D2 is electrically connected to one end of the resistor R3 and the HO pin of the gate driver U1, the positive electrode of the Zener diode D2 is electrically connected to one end of the resistor R2, the other end of the resistor R2 is electrically connected to the other end of the resistor R3 and the gate of the high-side MOS tube Q1, the negative electrode of the Zener diode D3 is electrically connected to one end of the resistor R5 and the LO pin of the gate driver U1, the positive electrode of the Zener diode D3 is electrically connected to one end of the resistor R4, and the other end of the resistor R4 is electrically connected to the other end of the resistor R5 and the gate of the low-side MOS tube Q2.

[0011] In some embodiments of the present application, the high-side negative voltage shutdown circuit includes a charge pump U2, a resistor R7, a capacitor C2, a capacitor C3, a voltage regulator D4 and a resistor R6, the IN pin of the charge pump U2 is electrically connected to one end of the resistor R6, the OUT pin of the charge pump U2 is electrically connected to the VS pin of the gate driver U1 and one end of the capacitor C3, the EN pin of the charge pump U2 is electrically connected to one end of the resistor R7, the GND pin of the charge pump U2 is electrically connected to the other end of the resistor R7, the other end of the capacitor C3, and the source of the high-side MOS tube Q1, the two ends of the capacitor C2 are electrically connected to the CFLY-pin and CFLY+pin of the charge pump U2, the negative electrode of the voltage regulator D4 is electrically connected to the IN pin of the charge pump U2 and one end of the resistor R6, and the positive electrode of the voltage regulator D4 is electrically connected to the GND pin of the charge pump U2.

[0012] In some embodiments of the present application, the high-side negative voltage shutdown circuit further includes a capacitor C6, and two ends of the capacitor C6 are electrically connected to the negative electrode and the positive electrode of the voltage regulator tube D4 respectively.

[0013] In some embodiments of the present application, the bootstrap circuit includes a resistor R1, a diode D1 and a capacitor C1, one end of the resistor R1 is electrically connected to the VB pin of the gate driver U1 and one end of the capacitor C1, respectively, the other end of the capacitor C1 is electrically connected to the GND pin of the charge pump U2 and the source of the high-side MOS tube Q1, the other end of the resistor R1 is electrically connected to the cathode of the diode D1, and the other end of the resistor R6 is electrically connected to the other end of the resistor R1 and the cathode of the diode D1, respectively, and the anode of the diode D1 is connected to the power supply voltage VCC.

[0014] In some embodiments of the present application, the low-side negative voltage shutdown circuit includes a charge pump U3, a resistor R9, a capacitor C4, a capacitor C5, a voltage regulator D5 and a resistor R8, the IN pin of the charge pump U3 is electrically connected to one end of the resistor R8, the other end of the resistor R8 is electrically connected to the VCC pin of the gate driver U1, the OUT pin of the charge pump U3 is electrically connected to the COM pin of the gate driver U1 and one end of the capacitor C5, and the EN pin of the charge pump U3 is electrically connected to the gate driver U1. One end of the resistor R9 is electrically connected, the GND pin of the charge pump U3 is respectively electrically connected to the other end of the resistor R9, the other end of the capacitor C5, and the source of the low-side MOS tube Q2, the two ends of the capacitor C4 are respectively electrically connected to the CFLY-pin and the CFLY+pin of the charge pump U3, the negative electrode of the voltage regulator D5 is respectively electrically connected to the IN pin of the charge pump U3 and one end of the resistor R8, and the positive electrode of the voltage regulator D5 is electrically connected to the GND pin of the charge pump U3.

[0015] In some embodiments of the present application, the low-side negative voltage shutdown circuit further includes a capacitor C7, and two ends of the capacitor C7 are electrically connected to the negative electrode and the positive electrode of the voltage regulator tube D5 respectively.

[0016] In some embodiments of the present application, the VDD pin, HI pin, LI pin and VSS pin of the gate driver U1 are respectively connected to PWM signals.

[0017] In some embodiments of the present application, the high-side MOS transistor Q1 and the low-side MOS transistor Q2 are both NMOS transistors.

[0018] The beneficial effects of the embodiments of the present application are as follows:

[0019] The gate negative voltage half-bridge drive circuit uses a bootstrap circuit to reduce the circuit topology power supply devices, reduces peripheral power supplies such as power modules, simplifies the circuit topology, and at the same time, provides gate negative voltage for high and low side power tubes through a negative voltage charge pump, increases negative voltage shutdown, reduces costs, and improves anti-interference ability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of the circuit principle of the gate negative voltage half-bridge drive circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present utility model, not all of the embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present utility model.

[0023] It should be noted that the terms "including" and "having" and any variations thereof in the embodiments of the present application and the accompanying drawings are intended to cover non-exclusive inclusions. For example, a series of structures are included, which is not limited to the listed structures, but may optionally include structures not listed, or may optionally include other components inherent to these structures.

[0024] The embodiment of the present application discloses a gate negative voltage half-bridge driving circuit, which uses a charge pump to establish a gate negative voltage to avoid parasitic turn-on of a power switch tube, thereby solving the problem in the prior art that the power tube is mis-turned on due to interference caused by rapid voltage transient di / dt and current transient di / dt, thereby causing the upper and lower tubes to be turned on directly. The following are detailed descriptions.

[0025] Figure 1 A gate negative voltage half-bridge driving circuit provided according to an embodiment of the present application is shown. Figure 1 As shown, the gate negative voltage half-bridge driving circuit includes: a gate driver U1, a power half-bridge circuit, a high-side negative voltage shutdown circuit, a low-side negative voltage shutdown circuit and a bootstrap circuit.

[0026] In the present application, the gate driver U1, the power half-bridge circuit and the bootstrap circuit constitute a basic half-bridge drive circuit, and the power half-bridge circuit includes an upper half-bridge and a lower half-bridge. In some specific embodiments, the half-bridge drive circuit controls the on and off of the power switch tube through PWM (Pulse Width Modulation) technology. In detail, the gate driver U1 includes a VDD pin, a HI pin, a LI pin, a VSS pin, a VB pin, a HO pin, a VS pin, a VCC pin, a LO pin, and a COM pin, wherein the VDD pin is the working power pin inside the device, the VSS pin is the circuit common ground power pin, the HI pin represents the high-side gate drive input, the LI pin represents the low-side gate drive input, the VDD pin, the HI pin, the LI pin, and the VSS pin of the gate driver U1 are connected to PWM signals respectively, the VB pin is the high-side floating power input pin, the HO pin represents the high-side gate drive output, the VS pin is the high-side floating power return, the VB pin, the HO pin, and the VS pin of the gate driver U1 control the MOS conduction of the upper half bridge, the VCC pin is the low-side floating and reference power input pin, the LO pin represents the low-side gate drive output, the COM pin represents the low-side floating power return, and the VCC pin, the LO pin, and the COM pin of the gate driver U1 control the MOS conduction of the lower half bridge.

[0027] The upper half bridge of the power half bridge circuit includes a high-side MOS tube Q1, and the upper half bridge is connected to the HO pin of the gate driver U1. The lower half bridge of the power half bridge circuit includes a low-side MOS tube Q2, and the lower half bridge is connected to the LO pin of the gate driver U1. The drain of the high-side MOS tube Q1 is connected to the DC voltage VDC, the source of the high-side MOS tube Q1 is electrically connected to the drain of the low-side MOS tube Q2, and the source of the low-side MOS tube Q2 is grounded. To be more specific, the upper half bridge of the power half-bridge circuit includes a resistor R3, a voltage regulator D2, and a resistor R2. One end of the resistor R3 is electrically connected to the HO pin of the gate driver U1, and the other end of the resistor R3 is electrically connected to the gate of the high-side MOS tube Q1. The negative electrode of the voltage regulator D2 is electrically connected to one end of the resistor R3 and the HO pin of the gate driver U1, respectively. The positive electrode of the voltage regulator D2 is electrically connected to one end of the resistor R2, and the other end of the resistor R2 is electrically connected to the other end of the resistor R3 and the gate of the high-side MOS tube Q1, respectively. The resistor R3 and the resistor R2 determine the turn-on and turn-off speeds of the high-side MOS tube Q1. The lower half bridge of the power half bridge circuit includes a resistor R5, a voltage regulator tube D3 and a resistor R4, one end of the resistor R5 is electrically connected to the LO pin of the gate driver U1, the other end of the resistor R5 is electrically connected to the gate of the low-side MOS tube Q2, the negative electrode of the voltage regulator tube D3 is electrically connected to one end of the resistor R5 and the LO pin of the gate driver U1, the positive electrode of the voltage regulator tube D3 is electrically connected to one end of the resistor R4, the other end of the resistor R4 is electrically connected to the other end of the resistor R5 and the gate of the low-side MOS tube Q2, and the resistor R5 and the resistor R4 determine the turn-on and turn-off speed of the low-side MOS tube Q2. In the specific implementation process, the high-side MOS tube Q1 and the low-side MOS tube Q2 are both NMOS tubes.

[0028] When the HI pin of the gate driver U1 is at a high level and the LI pin of the gate driver U1 is at a low level, the high-side MOS tube Q1 is turned on; when the HI pin of the gate driver U1 is at a low level and the LI pin of the gate driver U1 is at a high level, the low-side MOS tube Q2 is turned on.

[0029] The gate negative voltage half-bridge driving circuit uses a bootstrap circuit to reduce the circuit topology power supply components. The bootstrap circuit is connected to the VB pin of the gate driver U1. The bootstrap circuit generates a high-side bias signal to drive the gate of the high-side MOS tube Q1 based on the switch node. More specifically, the bootstrap circuit includes a resistor R1, a diode D1 and a capacitor C1. One end of the resistor R1 is electrically connected to the VB pin of the gate driver U1 and one end of the capacitor C1 respectively. The other end of the capacitor C1 is electrically connected to the source of the high-side MOS tube Q1. The other end of the resistor R1 is electrically connected to the cathode of the diode D1. The anode of the diode D1 is connected to the power supply voltage VCC.

[0030] When the low-side MOS tube Q2 is turned on and the high-side MOS tube Q1 is turned off, the VS pin and the switch node of the gate driver U1 are pulled to the ground, and the power supply voltage VCC charges the capacitor C1 of the bootstrap circuit via the diode D1 and the resistor R1 of the bootstrap circuit; when the high-side MOS tube Q1 is turned on and the low-side MOS tube Q2 is turned off, the VS pin and the switch node of the gate driver U1 are pulled to the DC voltage VDC (i.e., the high-voltage bus end), and the capacitor C1 of the bootstrap circuit discharges the stored voltage to the high-side MOS tube Q1 through the HO pin of the gate driver U1.

[0031] A larger gate resistor will reduce the switching speed of the MOS tube, thereby increasing power loss, while a smaller gate resistor will increase the switching speed of the MOS tube, but will cause voltage spikes and oscillations, resulting in mis-conduction, which will cause device failure and damage. To address this problem, the gate negative voltage half-bridge drive circuit is provided with a high-side negative voltage shutdown circuit and a low-side negative voltage shutdown circuit. The high-side negative voltage shutdown circuit is connected to the VS pin of the gate driver U1, the source of the high-side MOS tube Q1, and the bootstrap circuit respectively. When the high-side MOS tube Q1 is turned off, the HO pin of the gate driver U1 is connected to the VS pin, and the high-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the high-side MOS tube Q1; the low-side negative voltage shutdown circuit is connected to the source of the low-side MOS tube Q2, the VCC pin and the COM pin of the gate driver U1 respectively. When the low-side MOS tube Q2 is turned off, the LO pin of the gate driver U1 is connected to the COM pin, and the low-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the low-side MOS tube Q2. The circuit design of providing gate negative voltage for high and low-side power tubes is adopted, which increases negative voltage shutdown and improves reliability and anti-interference ability.

[0032] In some embodiments, the high-side negative voltage shutdown circuit includes a charge pump U2, a resistor R7, a capacitor C2, a capacitor C3, a voltage regulator D4, and a resistor R6. The high-side negative voltage shutdown circuit establishes a negative voltage for the gate of the high-side MOS tube Q1 through the charge pump U2, absorbs the charge of the parasitic Miller capacitor Cgd, and avoids mis-conduction. Specifically, the charge pump U2 includes an IN pin, an OUT pin, an EN pin, a CFLY-pin, a CFLY+ pin, and a GND pin, the IN pin represents the input end, the OUT pin represents the output end, the EN pin represents the enable input in the circuit, the CFLY-pin represents the negative pole of the external capacitor connection, the CFLY+ pin represents the positive pole of the external capacitor connection, and the GND pin represents the common terminal. The IN pin of the charge pump U2 is electrically connected to one end of the resistor R6, the OUT pin of the charge pump U2 is electrically connected to the VS pin of the gate driver U1 and one end of the capacitor C3, the EN pin of the charge pump U2 is electrically connected to one end of the resistor R7, the GND pin of the charge pump U2 is electrically connected to the other end of the resistor R7, the other end of the capacitor C3, and the source of the high-side MOS tube Q1, the two ends of the capacitor C2 are electrically connected to the CFLY-pin and the CFLY+pin of the charge pump U2, the negative electrode of the Zener diode D4 is electrically connected to the IN pin of the charge pump U2 and one end of the resistor R6, the positive electrode of the Zener diode D4 is electrically connected to the GND pin of the charge pump U2, in addition, the other end of the capacitor C1 is electrically connected to the GND pin of the charge pump U2, and the other end of the resistor R6 is electrically connected to the other end of the resistor R1 and the negative electrode of the diode D1. The charge pump U2 provides a negative gate voltage for the high-side MOS tube Q1. At the same time, the voltage regulator tube D4 provides a stable voltage for the charge pump U2, and the resistance value of the resistor R6 is adjusted to ensure that the voltage regulator tube D4 works in the voltage stabilization area. Further, the high-side negative voltage shutdown circuit also includes a capacitor C6, and the two ends of the capacitor C6 are respectively electrically connected to the negative electrode and the positive electrode of the voltage regulator tube D4. The capacitor C6 is connected in parallel with the voltage regulator tube D4. The capacitor C6 mainly plays the role of filtering and noise reduction, and at the same time protects the voltage regulator tube D4 from interference from high-frequency noise, so as to achieve a better voltage stabilization effect.

[0033] Among them, the power input of the charge pump U2 is provided with a stable voltage by the voltage regulator D4, and the GND pin of the charge pump U2 is connected to the source of the high-side MOS tube Q1. The output voltage of the charge pump U2 is negative and is connected to the VS pin of the gate driver U1, and a capacitor C3 is connected between the output end (i.e., the OUT pin) of the charge pump U2 and its common terminal (i.e., the GND pin). The charge pump U2 first charges the capacitor C2 through the internal control switch, and then the capacitor C3 is charged by the capacitor C2. When the high-side MOS tube Q1 is to be turned off, the HO pin of the gate driver U1 is connected to the VS pin, and the charge of the parasitic Miller capacitor Cgd of the high-side MOS tube Q1 is absorbed by the capacitor C3, thereby avoiding the excessive voltage generated at the gate to cause the MOS tube to be mis-turned on.

[0034] In other embodiments, the low-side negative voltage shutdown circuit includes a charge pump U3, a resistor R9, a capacitor C4, a capacitor C5, a voltage regulator D5 and a resistor R8. The low-side negative voltage shutdown circuit establishes a negative voltage for the gate of the low-side MOS tube Q2 through the charge pump U3, absorbs the charge of the parasitic Miller capacitor Cgd, and avoids misleading conduction. Specifically, the charge pump U3 includes an IN pin, an OUT pin, an EN pin, a CFLY-pin, a CFLY+ pin and a GND pin, the IN pin represents the input end, the OUT pin represents the output end, the EN pin represents the enable input in the circuit, the CFLY-pin represents the negative pole connected to the external capacitor, the CFLY+ pin represents the positive pole connected to the external capacitor, and the GND pin represents the common terminal. The IN pin of the charge pump U3 is electrically connected to one end of the resistor R8, the other end of the resistor R8 is electrically connected to the VCC pin of the gate driver U1, the OUT pin of the charge pump U3 is electrically connected to the COM pin of the gate driver U1 and one end of the capacitor C5, the EN pin of the charge pump U3 is electrically connected to one end of the resistor R9, the GND pin of the charge pump U3 is electrically connected to the other end of the resistor R9, the other end of the capacitor C5, and the source of the low-side MOS tube Q2, the two ends of the capacitor C4 are electrically connected to the CFLY-pin and the CFLY+pin of the charge pump U3, the negative electrode of the voltage regulator D5 is electrically connected to the IN pin of the charge pump U3 and one end of the resistor R8, and the positive electrode of the voltage regulator D5 is electrically connected to the GND pin of the charge pump U3. The charge pump U3 provides a negative gate voltage for the low-side MOS tube Q2, and at the same time, the voltage regulator D5 provides a stable voltage for the charge pump U3, and the resistance value of the resistor R8 is adjusted to ensure that the voltage regulator D5 works in the voltage stabilization area. Furthermore, the low-side negative voltage shutdown circuit also includes a capacitor C7, and the two ends of the capacitor C7 are electrically connected to the negative electrode and the positive electrode of the voltage regulator D5 respectively. The capacitor C7 is connected in parallel with the voltage regulator D5. The capacitor C7 mainly plays the role of filtering and noise reduction, and at the same time protects the voltage regulator D5 from interference from high-frequency noise, so as to achieve a better voltage stabilization effect.

[0035] Among them, the power input of the charge pump U3 is provided with a stable voltage by the voltage regulator D5, and the GND pin of the charge pump U3 is connected to the source of the low-side MOS tube Q2. The output voltage of the charge pump U3 is negative and is connected to the COM pin of the gate driver U1. A capacitor C5 is connected between the output end (i.e., the OUT pin) of the charge pump U3 and its common terminal (i.e., the GND pin). The charge pump U3 first charges the capacitor C4 through the internal control switch, and then the capacitor C5 is charged by the capacitor C4. When the low-side MOS tube Q2 is to be turned off, the LO pin of the gate driver U1 is connected to the COM pin, and the charge of the parasitic Miller capacitor Cgd of the low-side MOS tube Q2 is absorbed by the capacitor C5, thereby avoiding the excessive voltage generated at the gate to cause the MOS tube to be mis-turned on.

[0036] In summary, the present application discloses a gate negative voltage half-bridge drive circuit, which utilizes a bootstrap circuit to reduce the circuit topology power supply devices, reduces peripheral power supplies such as power modules, simplifies the circuit topology, and at the same time, provides gate negative voltage for high and low side power tubes through a negative voltage charge pump, increases negative voltage shutdown, reduces costs, and improves anti-interference capabilities and reliability.

[0037] Those skilled in the art will understand that the drawings are only schematic diagrams of an embodiment, and the components in the drawings are not necessarily necessary for implementing the present invention. It should also be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0038] It should be noted that the above-described embodiments are only specific implementation methods of the present utility model, which are used to illustrate the technical solution of the present utility model, rather than to limit it. The protection scope of the present utility model is not limited thereto. Although the present utility model is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solution recorded in the above-mentioned embodiments within the technical scope disclosed by the present utility model, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiment of the present utility model, and should be included in the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be based on the protection scope described in the claims.

Claims

1. A gate negative voltage half-bridge drive circuit, characterized in that: include: Gate driver U1, power half-bridge circuit, high-side negative voltage shutdown circuit, low-side negative voltage shutdown circuit and bootstrap circuit; The power half-bridge circuit is respectively connected to the HO pin and the LO pin of the gate driver U1, and the power half-bridge circuit includes a high-side MOS transistor Q1 and a low-side MOS transistor Q2, the drain of the high-side MOS transistor Q1 is connected to the DC voltage VDC, the source of the high-side MOS transistor Q1 is electrically connected to the drain of the low-side MOS transistor Q2, and the source of the low-side MOS transistor Q2 is grounded; The bootstrap circuit is connected to the VB pin of the gate driver U1, and generates a high-side bias signal through the bootstrap circuit to drive the gate of the high-side MOS tube Q1 based on the switch node; The high-side negative voltage shutdown circuit is respectively connected to the VS pin of the gate driver U1, the source of the high-side MOS tube Q1, and the bootstrap circuit. When the high-side MOS tube Q1 is turned off, the HO pin of the gate driver U1 is connected to the VS pin, and the high-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the high-side MOS tube Q1; The low-side negative voltage shutdown circuit is respectively connected to the source of the low-side MOS tube Q2, the VCC pin and the COM pin of the gate driver U1. When the low-side MOS tube Q2 is turned off, the LO pin of the gate driver U1 is connected to the COM pin, and the low-side negative voltage shutdown circuit absorbs the charge of the parasitic Miller capacitor Cgd of the low-side MOS tube Q2.

2. The gate negative voltage half-bridge driving circuit according to claim 1, characterized in that: The power half-bridge circuit also includes a resistor R3 and a resistor R5, one end of the resistor R3 is electrically connected to the HO pin of the gate driver U1, and the other end of the resistor R3 is electrically connected to the gate of the high-side MOS tube Q1, one end of the resistor R5 is electrically connected to the LO pin of the gate driver U1, and the other end of the resistor R5 is electrically connected to the gate of the low-side MOS tube Q2.

3. The gate negative voltage half-bridge driving circuit according to claim 2, characterized in that: The power half-bridge circuit also includes a voltage regulator tube D2, a resistor R2, a voltage regulator tube D3 and a resistor R4. The negative electrode of the voltage regulator tube D2 is electrically connected to one end of the resistor R3 and the HO pin of the gate driver U1, respectively. The positive electrode of the voltage regulator tube D2 is electrically connected to one end of the resistor R2, and the other end of the resistor R2 is electrically connected to the other end of the resistor R3 and the gate of the high-side MOS tube Q1, respectively. The negative electrode of the voltage regulator tube D3 is electrically connected to one end of the resistor R5 and the LO pin of the gate driver U1, respectively. The positive electrode of the voltage regulator tube D3 is electrically connected to one end of the resistor R4, and the other end of the resistor R4 is electrically connected to the other end of the resistor R5 and the gate of the low-side MOS tube Q2.

4. The gate negative voltage half-bridge driving circuit according to claim 1, characterized in that: The high-side negative voltage shutdown circuit includes a charge pump U2, a resistor R7, a capacitor C2, a capacitor C3, a voltage regulator D4 and a resistor R6. The IN pin of the charge pump U2 is electrically connected to one end of the resistor R6, the OUT pin of the charge pump U2 is electrically connected to the VS pin of the gate driver U1 and one end of the capacitor C3 respectively, the EN pin of the charge pump U2 is electrically connected to one end of the resistor R7, the GND pin of the charge pump U2 is electrically connected to the other end of the resistor R7, the other end of the capacitor C3 and the source of the high-side MOS tube Q1 respectively, the two ends of the capacitor C2 are electrically connected to the CFLY-pin and the CFLY+pin of the charge pump U2 respectively, the negative electrode of the voltage regulator D4 is electrically connected to the IN pin of the charge pump U2 and one end of the resistor R6 respectively, and the positive electrode of the voltage regulator D4 is electrically connected to the GND pin of the charge pump U2.

5. The gate negative voltage half-bridge driving circuit according to claim 4, characterized in that: The high-side negative voltage shutdown circuit further includes a capacitor C6, and two ends of the capacitor C6 are electrically connected to the negative electrode and the positive electrode of the voltage regulator tube D4 respectively.

6. The gate negative voltage half-bridge driving circuit according to claim 5, characterized in that: The bootstrap circuit includes a resistor R1, a diode D1 and a capacitor C1, one end of the resistor R1 is electrically connected to the VB pin of the gate driver U1 and one end of the capacitor C1 respectively, the other end of the capacitor C1 is electrically connected to the GND pin of the charge pump U2 and the source of the high-side MOS tube Q1 respectively, the other end of the resistor R1 is electrically connected to the cathode of the diode D1, and the other end of the resistor R6 is electrically connected to the other end of the resistor R1 and the cathode of the diode D1 respectively, and the anode of the diode D1 is connected to the power supply voltage VCC.

7. The gate negative voltage half-bridge driving circuit according to claim 1, characterized in that: The low-side negative voltage shutdown circuit includes a charge pump U3, a resistor R9, a capacitor C4, a capacitor C5, a voltage regulator D5 and a resistor R8. The IN pin of the charge pump U3 is electrically connected to one end of the resistor R8, and the other end of the resistor R8 is electrically connected to the VCC pin of the gate driver U1. The OUT pin of the charge pump U3 is electrically connected to the COM pin of the gate driver U1 and one end of the capacitor C5, respectively. The EN pin of the charge pump U3 is electrically connected to one end of the resistor R9, and the GND pin of the charge pump U3 is electrically connected to the other end of the resistor R9, the other end of the capacitor C5, and the source of the low-side MOS tube Q2, respectively. The two ends of the capacitor C4 are electrically connected to the CFLY-pin and the CFLY+pin of the charge pump U3, respectively. The negative electrode of the voltage regulator D5 is electrically connected to the IN pin of the charge pump U3 and one end of the resistor R8, respectively, and the positive electrode of the voltage regulator D5 is electrically connected to the GND pin of the charge pump U3.

8. The gate negative voltage half-bridge driving circuit according to claim 7, characterized in that: The low-side negative voltage shutdown circuit further includes a capacitor C7, and two ends of the capacitor C7 are electrically connected to the negative electrode and the positive electrode of the voltage regulator tube D5 respectively.

9. The gate negative voltage half-bridge driving circuit according to claim 1, characterized in that: The VDD pin, HI pin, LI pin and VSS pin of the gate driver U1 are connected to PWM signals respectively.

10. The gate negative voltage half-bridge driving circuit according to claim 1, characterized in that: The high-side MOS transistor Q1 and the low-side MOS transistor Q2 are both NMOS transistors.

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