Pin enhanced double-transistor packaging structure

Abstract

The utility model provides a pin-enhanced double-transistor packaging structure. The pin-enhanced double-transistor packaging structure comprises a double-base-island lead frame; the plurality of frame units are arranged on the surface of the double-base-island lead frame at equal intervals. The utility model provides a pin enhanced double-transistor packaging structure, which is formed by a newly designed double-base island lead frame structure which is formed by a plurality of frame unit arrays, each frame unit comprises two base islands and six pins, the base islands are respectively connected with the pins, the area of a single PIN2 pin and the area of a single PIN5 pin are increased, the areas of the two base islands are decreased accordingly, and due to the fact that the areas of the pins are increased, the area of the two base islands is increased. According to the double-transistor packaging structure, the glue locking capacity of the frame is greatly improved, the glue crack phenomenon during rib cutting can be effectively improved, and the barb-shaped glue locking structures are additionally arranged on the surfaces of the pins, so that the double-transistor packaging structure is further enhanced and stabilized, and the reliability of the double-transistor packaging structure is improved. And the pin loosening problem generated when the component is subjected to stress in each link of packaging production or application is prevented.

Description

Technical Field

[0001] The utility model relates to the field of dual transistor packaging, in particular to a pin-enhanced dual transistor packaging structure. Background Art

[0002] The packaging structure of dual-transistor dual-base island has two base islands in one plastic package. The two chips are placed in the two base islands respectively. Since the two related chips are installed in the two base islands inside one plastic package, the performance stability is greatly enhanced and the cost is greatly reduced.

[0003] The two base islands of the conventional SOT-363 18R double base island lead frame are the same size, both of which are 026*031+026*031 (0.667mm*0.775mm+0.667mm*0.775mm), and the PIN2 and PIN5 pins are smaller. Figure 1 As shown, the contact area with the resin is small and the glue locking ability is poor. When there is a certain deviation in the stamping size of the frame, there is stress tearing phenomenon in the inner pins, the glue will have the risk of cracking and the pins will have the risk of loosening.

[0004] Therefore, it is necessary to provide a pin-enhanced dual transistor packaging structure to solve the above technical problems. Utility Model Content

[0005] The utility model provides a pin-enhanced dual-transistor packaging structure, which solves the problems that the pins are small, the contact area with the resin is small, the glue locking ability is poor, when there is a certain deviation in the frame stamping size, the inner pins have stress tearing phenomenon, the glue has the risk of cracking, and the pins have the risk of loosening.

[0006] In order to solve the above technical problems, the utility model provides a pin-enhanced dual transistor packaging structure, comprising: a dual base island lead frame;

[0007] A frame unit, a plurality of the frame units are equidistantly arranged on the surface of the double base island lead frame, the frame unit comprises two base islands, a PIN1 pin, a PIN2 pin, a PIN3 pin, a PIN4 pin, a PIN5 pin and a PIN6 pin, and the two base islands are respectively connected to the PIN3 pin and the PIN6 pin;

[0008] A transistor, wherein the transistor is soldered to the surface of the base island;

[0009] A barbed glue locking structure, wherein the barbed glue locking structure is arranged on one side of the surface of the PIN2 pin and the PIN5 pin;

[0010] The two welding wires are respectively welded to the surface of the transistor, and the other ends of the two welding wires are respectively welded to the surface of the pins.

[0011] Preferably, the two bonding wires on the surface of one of the transistors are respectively connected to the PIN4 pin and the PIN5 pin, and the two bonding wires on the surface of another transistor are respectively connected to the PIN1 pin and the PIN2 pin.

[0012] Preferably, a reinforcing rib is provided in the middle of the surface of the double-base island lead frame.

[0013] Preferably, a mounting groove is opened in the middle of the base island surface, welding grooves are connected on both sides of the inner cavity of the mounting groove, mounting devices are fixedly installed on both sides of the base island surface, and limiting devices are slidably installed on both sides of the inside of the mounting device.

[0014] Preferably, the mounting device comprises a mounting plate, and a sliding groove is provided on one side of the mounting plate.

[0015] Preferably, the limiting device comprises a limiting plate, sliding blocks are fixedly mounted on both sides of the outer surface of the limiting plate, and an anti-slip pad is arranged on one side of the limiting plate.

[0016] Preferably, the sliding block is matched with the sliding groove, and the anti-slip pad is made of rubber.

[0017] Compared with the related art, the pin-enhanced dual transistor packaging structure provided by the utility model has the following beneficial effects:

[0018] The utility model provides a pin-enhanced dual-transistor packaging structure, which is formed by a plurality of frame unit arrays through a newly designed dual-base island lead frame structure. The frame unit includes two base islands and six pins, the base islands are respectively connected to the pins, and the single area of ​​PIN2 and PIN5 pins increases, and the areas of the two base islands decrease accordingly. Due to the increase in the pin area, the glue locking ability of the frame is greatly improved, and the glue cracking phenomenon during rib cutting can be effectively improved. A barbed glue locking structure is added on the pin surface, which further enhances and stabilizes the dual-transistor packaging structure, and prevents the pins from loosening due to stress caused by components in various links of packaging production or application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic structural diagram of a first embodiment of a pin-enhanced dual transistor packaging structure provided by the utility model;

[0020] Figure 2 for Figure 1 An enlarged schematic diagram of point A is shown;

[0021] Figure 3 for Figure 2 The enlarged schematic diagram of point B is shown;

[0022] Figure 4 This is a comparison of the shapes of the PIN2 and PIN5 pins before improvement;

[0023] Figure 5 This is a comparison diagram of the improved PIN2 and PIN5 pin shapes;

[0024] Figure 6 A schematic structural diagram of a second embodiment of a pin-enhanced dual transistor packaging structure provided by the utility model;

[0025] Figure 7 for Figure 6 The enlarged schematic diagram of point C is shown;

[0026] Figure 8 for Figure 7 The schematic diagram of the installation device structure shown;

[0027] Fig. 9 for Figure 7 The schematic diagram of the limit device structure is shown.

[0028] Numbers in the figure: 1. double base island lead frame, 2. reinforcement rib, 3. frame unit, 4. PIN4 pin, 5. PIN5 pin, 6. PIN6 pin, 7. PIN1 pin, 8. PIN2 pin, 9. PIN3 pin, 10. base island, 11. transistor, 12. welding wire, 13. mounting groove, 14. welding groove, 15. welding foot, 16. mounting device, 161. mounting plate, 162. slide groove, 17. limit device, 171. limit plate, 172. slider, 173. anti-slip pad, 18. barbed glue locking structure. DETAILED DESCRIPTION

[0029] The utility model is further described below in conjunction with the accompanying drawings and implementation modes.

[0030] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 ,in, Figure 1 A schematic structural diagram of a first embodiment of a pin-enhanced dual transistor packaging structure provided by the utility model; Figure 2 for Figure 1 An enlarged schematic diagram of point A is shown; Figure 3 for Figure 2 The enlarged schematic diagram of point B is shown; Figure 4 This is a comparison of the shapes of the PIN2 and PIN5 pins before improvement; Figure 5 The improved PIN2 pin and PIN5 pin shape comparison diagram is shown in FIG. A pin-enhanced dual transistor packaging structure includes: a dual-base island lead frame 1;

[0031] A frame unit 3, wherein a plurality of the frame units 3 are equidistantly arranged on the surface of the double base island lead frame 1, the frame unit 3 comprises two base islands 10, a PIN1 pin 7, a PIN2 pin 8, a PIN3 pin 9, a PIN4 pin 4, a PIN5 pin 5 and a PIN6 pin 6, and the two base islands 10 are respectively connected to the PIN3 pin 9 and the PIN6 pin 6;

[0032] A transistor 11, wherein the transistor 11 is welded to the surface of the base island 10;

[0033] A barbed glue locking structure 18, wherein the barbed glue locking structure 18 is disposed on one side of the surface of the PIN2 pin 8 and the PIN5 pin 5;

[0034] The two welding wires 12 are welded to the surface of the transistor 11 respectively, and the other ends of the two welding wires 12 are welded to the surface of the pins respectively.

[0035] The two welding wires 12 on the surface of one of the transistors 11 are respectively connected to the PIN4 pin 4 and the PIN5 pin 5, and the two welding wires 12 on the surface of another transistor 11 are respectively connected to the PIN1 pin 7 and the PIN2 pin 8.

[0036] A reinforcing rib 2 is provided in the middle of the surface of the double-base island lead frame 1 .

[0037] The volume of base island 10 is 023*023+023*023 (0.585mm*0.585mm+0.585mm*0.585mm), and the single area of ​​PIN2 and PIN4 pins reaches 0.1533mm2, which is about 1.9 times that before the improvement.

[0038] The working principle of a pin-enhanced dual transistor packaging structure provided by the utility model is as follows:

[0039] During operation, first, the double-island lead frame 1 structure is composed of a plurality of frame units 3 arrays. The frame unit 3 includes two islands 10 and six pins. The islands 10 are connected to the pins respectively. The single area of ​​PIN2 and PIN5 pins increases to 0.1533mm2, and the areas of the two islands 10 decrease accordingly. The sizes are both 023*023+023*023 (0.585mm*0.585mm+0.585mm*0.585mm).

[0040] Compared with the related art, the pin-enhanced dual transistor packaging structure provided by the utility model has the following beneficial effects:

[0041] The utility model provides a pin-enhanced dual-transistor packaging structure. The structure is formed by an array of multiple frame units 3 through a newly designed dual-base island lead frame structure. The frame unit 3 includes two base islands 10 and six pins. The base islands 10 are respectively connected to the pins. The area of ​​the single pin 5, PIN2 and PIN5, increases, and the areas of the two base islands 10 decrease accordingly. Since the pin area increases, the glue locking ability of the frame is greatly improved, and the glue cracking phenomenon during rib cutting can be effectively improved. A barbed glue locking structure is added to the pin surface, which further enhances and stabilizes the dual-transistor packaging structure, and prevents the pins from becoming loose due to stress caused by components in various links of packaging production or application.

[0042] Second embodiment

[0043] Please refer to Figure 6 , Figure 7 , Figure 8 and Fig. 9 Based on the pin-enhanced dual transistor package structure provided by the first embodiment of the present application, the second embodiment of the present application proposes another pin-enhanced dual transistor package structure. The second embodiment is only a preferred embodiment of the first embodiment, and the implementation of the second embodiment will not affect the independent implementation of the first embodiment.

[0044] Specifically, the difference of a pin-enhanced dual transistor packaging structure provided in the second embodiment of the present application is that, in a pin-enhanced dual transistor packaging structure, a mounting groove 13 is opened in the middle of the surface of the base island 10, and welding grooves 14 are connected on both sides of the inner cavity of the mounting groove 13, and mounting devices 16 are fixedly installed on both sides of the surface of the base island 10, and limiting devices 17 are slidably installed on both sides of the inside of the mounting device 16.

[0045] The mounting device 16 includes a mounting plate 161 , and a sliding groove 162 is formed on one side of the mounting plate 161 .

[0046] The limiting device 17 includes a limiting plate 171 , and sliders 172 are fixedly mounted on both sides of the outer surface of the limiting plate 171 . An anti-slip pad 173 is provided on one side of the limiting plate 171 .

[0047] The sliding block 172 is matched with the sliding groove 162 , and the anti-slip pad 173 is made of rubber.

[0048] The slider 172 is adapted to the slide groove 162, and the friction between the slider 172 and the slide groove 162 is relatively strong, and a relatively strong thrust is required to push the slider 172 to slide inside the slide groove 162. The anti-slip pad 173 is made of rubber material, and has a buffering and wear-resistant effect. The anti-slip pad 173 is pressed on the surface of the transistor 11, which not only restricts the transistor 11, but also buffers the vibration effect on the transistor 11.

[0049] The working principle of a pin-enhanced dual transistor packaging structure provided by the utility model is as follows:

[0050] During operation, the transistor 11 and the soldering foot 15 are first installed in the installation groove 13 and the soldering groove 14 respectively, and then the spot welding technology is used for welding.

[0051] After welding is completed, the user pushes the limit plate 171 so that the left and right limit plates 171 slide inside the slide groove 162 through the slider 172, so that the limit plate 171 moves to the surface of the transistor 11, so that the anti-skid pad 173 fits the surface of the transistor 11, achieving shock absorption and anti-skid effects.

[0052] Compared with the related art, the pin-enhanced dual transistor packaging structure provided by the utility model has the following beneficial effects:

[0053] The utility model provides a pin-enhanced dual-transistor packaging structure, in which a transistor 11 and a soldering foot 15 are soldered inside through an installation groove 13 and a soldering groove 14, and a limit plate 171 is moved so that the limit plate 171 is pressed on the top surface of the soldering foot 15 to limit the transistor 11, thereby improving the soldering effect of the transistor 11, and an anti-skid pad 173 has a shock-absorbing effect, thereby reducing the influence of vibration on the transistor 11, avoiding the soldering foot 15 from falling off due to external vibration, and improving the stability of the installation of the transistor 11.

[0054] The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A pin-enhanced dual transistor packaging structure, characterized in that: include: Double base island lead frame; A frame unit, a plurality of the frame units are equidistantly arranged on the surface of the double base island lead frame, the frame unit comprises two base islands, a PIN1 pin, a PIN2 pin, a PIN3 pin, a PIN4 pin, a PIN5 pin and a PIN6 pin, and the two base islands are respectively connected to the PIN3 pin and the PIN6 pin; A transistor, wherein the transistor is soldered to the surface of the base island; A barbed glue locking structure, wherein the barbed glue locking structure is arranged on one side of the surface of the PIN2 pin and the PIN5 pin; The two welding wires are respectively welded to the surface of the transistor, and the other ends of the two welding wires are respectively welded to the surface of the pins.

2. The pin-enhanced dual transistor package structure according to claim 1, characterized in that: The two welding wires on the surface of one of the transistors are respectively connected to the PIN4 pin and the PIN5 pin, and the two welding wires on the surface of another transistor are respectively connected to the PIN1 pin and the PIN2 pin.

3. The pin-enhanced dual transistor package structure according to claim 1, characterized in that: A reinforcing rib is arranged in the middle of the surface of the double base island lead frame.

4. The pin-enhanced dual transistor package structure according to claim 1, characterized in that: A mounting groove is provided in the middle of the base island surface, and welding grooves are connected to both sides of the inner cavity of the mounting groove. Mounting devices are fixedly installed on both sides of the base island surface, and limiting devices are slidably installed on both sides of the inside of the mounting device.

5. The pin-enhanced dual transistor package structure according to claim 4, characterized in that: The mounting device comprises a mounting plate, and a sliding groove is provided on one side of the mounting plate.

6. The pin-enhanced dual transistor package structure according to claim 5, characterized in that: The limiting device comprises a limiting plate, sliding blocks are fixedly mounted on both sides of the outer surface of the limiting plate, and an anti-slip pad is arranged on one side of the limiting plate.

7. The pin-enhanced dual transistor package structure according to claim 6, characterized in that: The sliding block is matched with the sliding groove, and the anti-slip pad is made of rubber material.

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