A rotary transformer excitation signal generating circuit and electronic equipment

Abstract

The present application discloses a resolver excitation signal generating circuit and electronic equipment, which relate to the field of resolver, and include a square wave generating circuit, a first branch and a second branch, wherein the first branch and the second branch both include a bandpass filtering circuit and a signal conditioning circuit, wherein the square wave generating circuit generates two square wave signals with the same frequency and a phase difference of π, wherein the two square wave signals are filtered by the bandpass filtering circuit and the amplitude amplified by the signal conditioning circuit in the first branch and the second branch respectively, and finally a group of differential sinusoidal excitation signals with the same frequency and a phase difference of π are obtained as the input of the resolver, wherein the resolver excitation signal generating circuit is externally arranged in a microcontroller, and does not need to occupy the analog-to-digital conversion module of the microcontroller, and can directly output the sinusoidal excitation signal, and does not need to use the microcontroller to calculate the trigonometric function value corresponding to the sinusoidal signal in real time, thereby saving the resources of the microcontroller, and the generated sinusoidal excitation signal can be directly used for the resolver without the need for additional configuration circuits.

Description

Technical Field

[0001] The present application relates to the technical field of rotary transformers, and in particular to a rotary transformer excitation signal generating circuit and an electronic device including the rotary transformer excitation signal generating circuit. Background Art

[0002] The resolver is an electromagnetic sensor commonly used for measuring motor speed. Due to its high reliability, it is widely used in motor control scenarios in the automotive, aerospace and other fields. The resolver requires a sinusoidal excitation signal as input, and the input sinusoidal excitation signal is also the carrier signal of the output signal. The sinusoidal and cosine signals output by the resolver containing the excitation signal are collected and de-enveloped by the digital-to-analog converter to obtain accurate sine and cosine signals, which are then solved to obtain the speed of the target being measured.

[0003] Currently, there are two widely used technical solutions for generating a sinusoidal excitation signal for a rotary transformer (i.e., a resolver excitation signal). One is to use a built-in analog-to-digital converter (DAC) module of a microcontroller (MCU) to generate a sinusoidal signal, which is input into the rotary transformer after passing through a signal conditioning circuit. However, this will occupy one DAC module in the microcontroller for the output of the sinusoidal signal. The other is an external analog-to-digital converter chip (DAC chip). Although the external DAC chip will not occupy the DAC module in the microcontroller, the microcontroller needs to be used to control the external DAC chip to output the sinusoidal signal through inter-chip communication. In addition, the above two technical solutions require the microcontroller to calculate the trigonometric function value corresponding to the output sinusoidal signal in real time, which occupies the resources of the microcontroller. Utility Model Content

[0004] In order to solve the above technical problems, an embodiment of the present application provides a resolver excitation signal generating circuit, which is externally placed in a microcontroller and does not need to occupy the analog-to-digital conversion module of the microcontroller. It can directly output a sinusoidal excitation signal and does not need to use the microcontroller to calculate the trigonometric function value corresponding to the sinusoidal signal in real time, thereby saving the resources of the microcontroller.

[0005] To achieve the above objectives, the present application provides the following technical solutions:

[0006] A resolver excitation signal generating circuit comprises a square wave generating circuit, a first branch and a second branch;

[0007] The square wave generating circuit is used to generate a first square wave signal and output it to the first branch, and to generate a second square wave signal and output it to the second branch, wherein the first square wave signal and the second square wave signal have the same frequency and a phase difference of π;

[0008] The first branch includes a first bandpass filter circuit and a first signal conditioning circuit electrically connected in sequence, the first bandpass filter circuit is used to filter out signals of other frequencies other than the target frequency in the first square wave signal, and output a first sinusoidal signal of the target frequency; the first signal conditioning circuit is used to amplify the amplitude of the first sinusoidal signal and output a first sinusoidal excitation signal;

[0009] The second branch includes a second bandpass filter circuit and a second signal conditioning circuit electrically connected in sequence, the second bandpass filter circuit is used to filter out signals of other frequencies other than the target frequency in the second square wave signal, and output a second sinusoidal signal of the target frequency; the second signal conditioning circuit is used to amplify the amplitude of the second sinusoidal signal and output a second sinusoidal excitation signal.

[0010] Optionally, the square wave generating circuit includes a 555 timer, a first resistor, a second resistor, a first capacitor and an inverter;

[0011] The power pin of the 555 timer is connected to a first DC power supply voltage, and the power pin of the 555 timer is also connected to ground via the first resistor and the first capacitor in sequence;

[0012] The threshold pin and the trigger pin of the 555 timer are both electrically connected to an end of the first capacitor away from the ground;

[0013] The reset pin of the 555 timer is electrically connected to the power pin of the 555 timer;

[0014] The output pin of the 555 timer is electrically connected to the trigger pin of the 555 timer through the second resistor;

[0015] The output pin of the 555 timer is also electrically connected to the input end of the first branch, and the output pin of the 555 timer is also electrically connected to the input end of the second branch through the inverter.

[0016] Optionally, the first band-pass filter circuit includes a first low-pass filter circuit and a first high-pass filter circuit electrically connected in sequence;

[0017] The first low-pass filter circuit is used to filter out signals with a frequency higher than the target frequency in the first square wave signal, and output the signal to the first high-pass filter circuit;

[0018] The first high-pass filter circuit is used to filter out signals with frequencies higher than the target frequency in the signal output by the first low-pass filter circuit, and output the first sinusoidal signal of the target frequency.

[0019] Optionally, the first low-pass filter circuit includes a first operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a second capacitor and a third capacitor;

[0020] The input end of the first branch is electrically connected to the positive input end of the first operational amplifier through the third resistor and the fourth resistor in sequence, and the positive input end of the first operational amplifier is also grounded through the second capacitor; the negative input end of the first operational amplifier is electrically connected to the output end of the first operational amplifier through the fifth resistor and is also grounded through the sixth resistor; the output end of the first operational amplifier is electrically connected to the fourth resistor through the third capacitor and is electrically connected to one end of the third resistor;

[0021] The first high-pass filter circuit includes a second operational amplifier, a fourth capacitor, a fifth capacitor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor;

[0022] The output end of the first operational amplifier is electrically connected to the positive input end of the second operational amplifier through the fourth capacitor and the fifth capacitor in sequence, and the positive input end of the second operational amplifier is also grounded through the seventh resistor; the negative input end of the second operational amplifier is electrically connected to the output end of the second operational amplifier through the eighth resistor, and is also grounded through the ninth resistor; the output end of the second operational amplifier is electrically connected to the fifth capacitor through the tenth resistor and one end of the fourth capacitor is electrically connected;

[0023] The output end of the second operational amplifier is the output end of the first band-pass filter circuit.

[0024] Optionally, the first signal conditioning circuit includes a third operational amplifier, a sixth capacitor and an eleventh resistor;

[0025] Among them, the output end of the first band-pass filter circuit is electrically connected to the negative input end of the third operational amplifier through the sixth capacitor; the positive input end of the third operational amplifier is connected to the first collimated voltage; the output end of the third operational amplifier is electrically connected to the negative input end of the third operational amplifier through the eleventh resistor.

[0026] Optionally, the first signal conditioning circuit further includes a seventh capacitor, one end of the seventh capacitor being electrically connected to the negative input terminal of the third operational amplifier, and the other end of the seventh capacitor being electrically connected to the output terminal of the third operational amplifier.

[0027] Optionally, the first signal conditioning circuit further includes a push-pull circuit, and the push-pull circuit is used to amplify the driving capability of the input signal;

[0028] The input end of the push-pull circuit is electrically connected to the output end of the third operational amplifier, the output end of the push-pull circuit is electrically connected to one end of the eleventh resistor electrically connected to the output end of the third operational amplifier, and the common end of the push-pull circuit and the eleventh resistor is the output end of the first signal conditioning circuit;

[0029] Alternatively, the input end of the push-pull circuit is electrically connected to the output end of the third operational amplifier, and the input end of the push-pull circuit is also electrically connected to one end of the eleventh resistor electrically connected to the output end of the third operational amplifier, and the output end of the push-pull circuit is the output end of the first signal conditioning circuit.

[0030] Optionally, the push-pull circuit includes a first triode and a second triode, wherein the first end of the first triode is connected to a second DC power supply voltage, the second end of the first triode is electrically connected to the first end of the second triode, and the second end of the second triode is grounded;

[0031] The push-pull circuit further includes a first sub-branch located between the input end of the push-pull circuit and the control end of the first transistor, the first sub-branch includes a first diode, a twelfth resistor and a thirteenth resistor, wherein the first end of the twelfth resistor is electrically connected to the input end of the push-pull circuit, the second end of the twelfth resistor is electrically connected to the N pole of the first diode, and the P pole of the first diode is electrically connected to the control end of the first transistor through the thirteenth resistor;

[0032] The P pole of the first diode is also electrically connected to the first end of the first transistor through a fourteenth resistor, and the control end of the first transistor is electrically connected to the second end of the first transistor through a fifteenth resistor;

[0033] The push-pull circuit further includes a second sub-branch located between the input end of the push-pull circuit and the control end of the second triode, the second sub-branch includes a second diode, a sixteenth resistor and a seventeenth resistor, wherein a first end of the sixteenth resistor is electrically connected to the input end of the push-pull circuit, a second end of the sixteenth resistor is electrically connected to a P-pole of the second diode, and an N-pole of the second diode is electrically connected to the control end of the second triode through the seventeenth resistor;

[0034] The N-pole of the second diode is also electrically connected to the second end of the second transistor through an eighteenth resistor, and the control end of the second transistor is electrically connected to the first end of the second transistor through a nineteenth resistor.

[0035] Optionally, the second branch has the same structure as the first branch.

[0036] An electronic device comprises the resolver excitation signal generating circuit described in any one of the above items.

[0037] Compared with the prior art, the above technical solution has the following advantages:

[0038] The resolver excitation signal generating circuit provided in the embodiment of the present application includes a square wave generating circuit, a first branch and a second branch, wherein the square wave generating circuit is used to generate a first square wave signal and output it to the first branch, and to generate a second square wave signal and output it to the second branch, the first square wave signal and the second square wave signal have the same frequency and a phase difference of π; the first branch includes a first bandpass filter circuit and a first signal conditioning circuit which are electrically connected in sequence, the first bandpass filter circuit is used to filter out signals of other frequencies other than the target frequency in the first square wave signal, and output a first sinusoidal signal of the target frequency; the first signal conditioning circuit is used to adjust the amplitude of the first sinusoidal signal The value is amplified, and the first sinusoidal excitation signal of the target frequency is output; similarly, the second branch includes a second bandpass filter circuit and a second signal conditioning circuit electrically connected in sequence, the second bandpass filter circuit is used to filter out the signals of other frequencies other than the target frequency in the second square wave signal, and output the second sinusoidal signal of the target frequency; the second signal conditioning circuit is used to amplify the amplitude of the second sinusoidal signal, and output the second sinusoidal excitation signal of the target frequency; thus, the first sinusoidal excitation signal and the second sinusoidal excitation signal constitute a set of differential sinusoidal excitation signals with the same frequency and a phase difference of π, which can be used as the sinusoidal excitation signal input of the rotary transformer. It can be seen that the rotary transformer excitation signal generating circuit provided in the embodiment of the present application can be externally placed in a microcontroller, without occupying the analog-to-digital conversion module of the microcontroller, and can directly output the sinusoidal excitation signal, without using the microcontroller to calculate the trigonometric function value corresponding to the sinusoidal signal in real time, saving the resources of the microcontroller, and the generated sinusoidal excitation signal can be directly used for the rotary transformer without the need for additional configuration circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A structural block diagram of a resolver excitation signal generating circuit provided in an embodiment of the present application;

[0041] Figure 2 A schematic diagram of a specific circuit structure of a resolver excitation signal generating circuit provided in an embodiment of the present application;

[0042] Figure 3A schematic diagram of the circuit structure of a 555 timer U1;

[0043] Figure 4 for Figure 3 The structure diagram of the square wave generating circuit 10 formed by the configuration circuit of the 555 timer U1 through the first resistor R1, the second resistor R2 and the first capacitor C1;

[0044] Figure 5 Schematic diagram of waveforms of a first square wave signal TP1 and a second square wave signal TP2 output by the square wave generating circuit 10;

[0045] Figure 6 Schematic diagram of waveforms of the first sinusoidal signal TP3 in the first branch 20 and the second sinusoidal signal TP4 in the second branch 30;

[0046] Figure 7 Schematic diagram of waveforms of the first sinusoidal excitation signal EXC1 output by the first branch 20 and the second sinusoidal excitation signal EXC2 output by the second branch 30 . DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0049] Figure 1 FIG. 4 shows a structural block diagram of a resolver excitation signal generating circuit provided in an embodiment of the present application. Figure 1 As shown, the resolver excitation signal generating circuit provided in the embodiment of the present application includes a square wave generating circuit 10, a first branch 20 and a second branch 30; wherein the square wave generating circuit 10 is used to generate a first square wave signal TP1 and output it to the first branch 20, and to generate a second square wave signal TP2 and output it to the second branch 30, and the first square wave signal TP1 and the second square wave signal TP2 have the same frequency and a phase difference of π;

[0050] The first branch 20 includes a first band-pass filter circuit 21 and a first signal conditioning circuit 22 which are electrically connected in sequence, wherein the first band-pass filter circuit 21 is used to filter out signals of other frequencies except the target frequency in the first square wave signal TP1, and allow the signals of the target frequency in the first square wave signal TP1 to pass through, and output a first sinusoidal signal TP3 of the target frequency; the first signal conditioning circuit 22 is used to amplify the amplitude of the first sinusoidal signal TP3, and output a first sinusoidal excitation signal EXC1;

[0051] Similarly, the second branch 30 includes a second bandpass filter circuit 31 and a second signal conditioning circuit 32 which are electrically connected in sequence. The second bandpass filter circuit 31 is used to filter out signals of frequencies other than the target frequency in the second square wave signal TP2, allow signals of the target frequency in the second square wave signal TP2, and output a second sinusoidal signal TP4 within the target frequency range; the second signal conditioning circuit 32 is used to amplify the amplitude of the second sinusoidal signal TP4 and output a second sinusoidal excitation signal EXC2.

[0052] It can be understood that the first square wave signal TP1 and the second square wave signal TP2 generated by the square wave generating circuit 10 have the same frequency and a phase difference of π. Furthermore, the first square wave signal TP1 is filtered by the first bandpass filter circuit 21 and the amplitude amplified by the first signal conditioning circuit 22 in the first branch 20 to become the first sinusoidal excitation signal EXC1 of the target frequency, and the second square wave signal TP2 is filtered by the second bandpass filter circuit 31 and the amplitude amplified by the second signal conditioning circuit 32 in the second branch 30 to become the second sinusoidal excitation signal EXC2 of the target frequency. Thus, the first sinusoidal excitation signal EXC1 and the second sinusoidal excitation signal EXC2 constitute a set of differential sinusoidal excitation signals with the same frequency and a phase difference of π, which can be used as the sinusoidal excitation signal input of the rotating transformer.

[0053] It can be seen that the resolver excitation signal generating circuit provided in the embodiment of the present application first uses a square wave generating circuit to generate two square wave signals with the same frequency and a phase difference of π, and then filters and amplifies the amplitude of the two square wave signals respectively to obtain a set of differential sinusoidal excitation signals with the same frequency and a phase difference of π. Therefore, the resolver excitation signal generating circuit provided in the embodiment of the present application can be externally placed in a microcontroller without occupying the analog-to-digital conversion module of the microcontroller, and can directly output a sinusoidal excitation signal without using the microcontroller to calculate the trigonometric function value corresponding to the sinusoidal signal in real time, thereby saving the resources of the microcontroller, especially for small-resource, low-cost microcontrollers. In addition, the generated sinusoidal excitation signal can be directly used for the resolver without the need for additional configuration circuits.

[0054] Optional, Figure 2 A specific circuit structure diagram of a resolver excitation signal generating circuit provided in an embodiment of the present application is further shown, such as Figure 2 As shown, the square wave generating circuit 10 includes a 555 timer U1, a first resistor R1, a second resistor R2, a first capacitor C1 and an inverter U2;

[0055] The power pin Vin of the 555 timer U1 is connected to the first DC power supply voltage Vcc1, and the power pin Vin of the 555 timer U1 is also connected to the ground through the first resistor R1 and the first capacitor C1 in sequence;

[0056] The threshold pin th and the trigger pin tr of the 555 timer U1 are both electrically connected to the end of the first capacitor C1 away from the ground;

[0057] The reset pin rst of the 555 timer U1 is electrically connected to the power pin Vin of the 555 timer U1;

[0058] The output pin out of the 555 timer U1 is electrically connected to the trigger pin tr of the 555 timer U1 through the second resistor R2;

[0059] The output pin out of the 555 timer U1 is also electrically connected to the input end of the first branch 20 , and the output pin out of the 555 timer is also electrically connected to the input end of the second branch 30 through the inverter U2 .

[0060] For ease of understanding, Figure 3 A schematic diagram of the circuit structure of a 555 timer U1 is further shown. Figure 2 and Figure 3 As shown, the 555 timer U1 has 8 pins, namely, power pin Vin, trigger pin tr, threshold pin th, reset pin rst, output pin out, ground pin gnd, discharge pin dis and control pin ctl; the 555 timer U1 is mainly composed of two comparators T1 and T2, voltage divider circuit VDC, trigger RS-FF, discharge transistor DT and buffer ODC. The specific circuit connection relationship is as follows: Figure 3 As shown, no further details are given.

[0061] The voltage divider circuit VDC is composed of three 5kΩ resistors R01, R02 and R03 connected in series, so these three resistors can divide the first DC power supply voltage Vcc1 input by the power supply pin Vin into three equal parts. When the control pin ctl is not connected to an external fixed voltage, the voltage VH of the end of the resistor R02 away from the ground is equal to (2 / 3) Vcc1, and the voltage VL of the end of the resistor R01 away from the ground is equal to (1 / 3) Vcc1.

[0062] For comparator T1, the voltage Vtr input at the trigger pin tr serves as the voltage input to the negative input terminal of comparator T1, and the voltage VL at the end of resistor R01 away from the ground serves as the voltage input to the positive input of comparator T1. Comparator T1 compares the voltage Vtr input at the trigger pin tr with the voltage VL at the end of resistor R01 away from the ground. When the voltage Vtr input at the trigger pin tr is less than the voltage VL at the end of resistor R01 away from the ground, i.e., Vtr < VL, the output terminal A of comparator T1 outputs logic "1". When the voltage Vtr input at the trigger pin tr is greater than the voltage VL at the end of resistor R01 away from the ground, i.e., Vtr > VL, the output terminal A of comparator T1 outputs logic "0".

[0063] For comparator T2, the voltage Vth input at the threshold pin th serves as the voltage input to the positive input terminal of comparator T2, and the voltage VH at the end of resistor R02 away from the ground serves as the voltage input to the negative input of comparator T2. Comparator T2 compares the voltage Vth input at the threshold pin th with the voltage VH at the end of resistor R02 away from the ground. When the voltage Vth input at the threshold pin th is greater than the voltage VH at the end of resistor R02 away from the ground, the output terminal B of comparator T2 gets logic "1". When the voltage Vth input at the threshold pin th is less than the voltage VH at the end of resistor R02 away from the ground, the output terminal B of comparator T2 gets logic "0".

[0064] The flip-flop RS-FF has two input terminals S and R. The output terminal A of comparator T1 is connected to the input terminal S of flip-flop FP, and the output terminal B of comparator T2 is connected to the input terminal R of flip-flop FP.

[0065] The flip-flop RS-FF is followed by a discharge transistor DT. If the discharge transistor DT is turned on, it is equivalent to connecting the discharge pin dis to the ground pin gnd.

[0066] After the flip-flop RS-FF, there is also a buffer ODC, whose function is to improve the load-carrying capacity of the circuit and output a larger current.

[0067] Table 1 below lists the input, internal, and output conditions of the 555 timer U1.

[0068] Table 1 Input, Internal, and Output Conditions of the 555 Timer U1

[0069]

[0070] Figure 4 Further shown is a schematic diagram of the structure of the square wave generating circuit 10 formed by the 555 timer U1 through the configuration circuit of the first resistor R1, the second resistor R2, and the first capacitor C1, in combination with Figure 2 and Figure 4It can be seen that in the square wave generating circuit 10, the trigger pin tr and the threshold pin th of the 555 timer U1 are at the same potential, that is, Vth = Vtr, and both Vth and Vtr are the voltages at the end of the first capacitor C1 away from the ground.

[0071] During specific operation, the control pin ctl of the 555 timer U1 is not externally connected to a fixed voltage. Therefore, the voltage VH at the end of the resistor R02 away from the ground is VH = (2 / 3)Vcc1, and the voltage VL at the end of the resistor R01 away from the ground is VL = (1 / 3)Vcc1. When Vth (Vtr) < VL < VH, that is, when Vth (Vtr) < (1 / 3)Vcc1, referring to Table 1, it can be known that the output pin out of the 555 timer U1 outputs logic "1", which is a high level. The output pin out of the 555 timer U1 charges the first capacitor C1 through the second resistor R2, and the voltages Vth and Vtr at the end of the first capacitor C1 away from the ground gradually increase. When the voltages Vth and Vtr at the end of the first capacitor C1 away from the ground increase to satisfy VL < Vth (Vtr) < VH, that is, (1 / 3)Vcc1 < Vth (Vtr) < (2 / 3)Vcc1, referring to Table 1, it can be known that the output logic of the output pin out of the 555 timer U1 remains unchanged and is still "1", and the output pin out of the 555 timer U1 continues to charge the first capacitor C1 through the second resistor R2. When the voltages Vth and Vtr at the end of the first capacitor C1 away from the ground increase to (2 / 3)Vcc1, referring to Table 1, it can be known that the output logic of the output pin out of the 555 timer U1 changes to "0", becoming a low level. The output pin out of the 555 timer U1 stops charging the first capacitor C1, and the first capacitor C1 then discharges externally. When the voltages Vth and Vtr at the end of the first capacitor C1 away from the ground decrease to (1 / 3)Vcc1, referring to Table 1, it can be known that the discharge of the first capacitor C1 stops, and the output pin out of the 555 timer U1 then charges the first capacitor C1 again.

[0072] In this way, the first capacitor C1 is periodically charged and discharged between (1 / 3)Vcc1 and (2 / 3)Vcc1, causing the output pin out of the 555 timer U1 to switch between a high level and a low level, generating a square wave signal. Thus, the square wave generating circuit 10 outputs a first square wave signal TP1 with a fixed frequency to the input end of the first branch 20. The first square wave signal TP1 then passes through the inverter U2 and becomes a second square wave signal TP2 and is output to the input end of the second branch 30. The function of the inverter U2 is to delay the phase of the first square wave signal TP1 by π to become a second square wave signal TP2 with the same frequency but a phase difference of π. Figure 5 The waveform diagrams of the first square wave signal TP1 and the second square wave signal TP2 output by the square wave generating circuit 10 are shown. It can be seen that the first square wave signal TP1 and the second square wave signal TP2 have the same frequency and a phase difference of π.

[0073] Optionally, the first DC power supply voltage Vcc1 may be +5V.

[0074] It can be understood that the 555 timer U1 is configured as a square wave output mode through the first capacitor C1, the first resistor R1 and the second resistor R2. The charge and discharge cycle of the first capacitor C1 determines the frequency of the output first square wave signal TP1 and the second square wave signal TP2. The typical excitation frequency of the rotary transformer is 10kHz, and the period T of the first square wave signal TP1 output by the 555 timer U1 should be set to 1×10 -4 s, in Figure 4 In the square wave generating circuit 10 shown, the period T of the first square wave signal TP1 output by the 555 timer U1 satisfies T=1.386×R2×C1. Optionally, R2=3.3kΩ, C1=22nF, and R1 can be set to 1MΩ.

[0075] Alternatively, the square wave generating circuit 10 may include a time base generating chip having similar functions to the 555 timer, and adjust the configuration circuit accordingly, so as to generate a first square wave signal TP1 having a fixed frequency, and then form a second square wave signal TP2 having the same frequency and a phase difference of π through an inverter U2.

[0076] like Figure 2 As shown, the first square wave signal TP1 is input into the first branch 20 through the input end of the first branch 20 , and the second square wave signal TP2 is input into the second branch 30 through the input end of the second branch 30 .

[0077] In the first branch 20, optionally, as Figure 2 As shown, the first band-pass filter circuit 21 includes a first low-pass filter circuit 211 and a first high-pass filter circuit 212 which are electrically connected in sequence; wherein the first low-pass filter circuit 211 is used to filter out signals with frequencies higher than the target frequency in the first square wave signal TP1, allow signals with the target frequency and signals lower than the target frequency in the first square wave signal TP1 to pass through, and output signals with the target frequency and signals lower than the target frequency in the first square wave signal TP1 to the first high-pass filter circuit 212; the first high-pass filter circuit 212 is used to filter out signals with frequencies lower than the target frequency in the signal output by the first low-pass filter circuit 211, and output a first sinusoidal signal TP3 with the target frequency.

[0078] Optional, such as Figure 2 As shown, the first low-pass filter circuit 211 includes a first operational amplifier H1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second capacitor C2 and a third capacitor C3;

[0079] Among them, the input end of the first branch 20 is electrically connected to the positive input end of the first operational amplifier H1 through the third resistor R3 and the fourth resistor R4 in sequence, and the positive input end of the first operational amplifier H1 is also grounded through the second capacitor C2; the negative input end of the first operational amplifier H1 is electrically connected to the output end of the first operational amplifier H1 through the fifth resistor R5, and is also grounded through the sixth resistor R6; the output end of the first operational amplifier H1 is electrically connected to the fourth resistor R4 through the third capacitor C3 and one end of the third resistor R3.

[0080] In this way, the first low-pass filter circuit 211 is a first-order active low-pass filter circuit, which filters out signals with frequencies higher than the target frequency in the first square wave signal TP1, allows signals with the target frequency and lower than the target frequency in the first square wave signal TP1 to pass, and outputs signals with the target frequency and lower than the target frequency in the first square wave signal TP1 to the first high-pass filter circuit 212.

[0081] Figure 2 The cut-off frequency f of the first low-pass filter circuit 211 in c It can be expressed as:

[0082]

[0083] Figure 2 The gain G0 of the first low-pass filter circuit 211 in can be expressed as:

[0084]

[0085] Figure 2 The quality factor Q of the first low-pass filter circuit 211 in can be expressed as:

[0086]

[0087] The quality factor of a typical low-pass filter circuit for resolver applications is Q = 0.707, and the cut-off frequency f c =10kHz, for the convenience of design, R3=R4, C2=C3 can be set. According to formula (1), R3=R4=36kΩ, C2=C3=880pF can be set. Furthermore, combining formula (2) and formula (3), R5=30kΩ, R6=51kΩ can be set.

[0088] Optional, such as Figure 2 As shown, the first high-pass filter circuit 212 includes a second operational amplifier H2, a fourth capacitor C4, a fifth capacitor C5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10;

[0089] The output end of the first operational amplifier H1 is electrically connected to the positive input end of the second operational amplifier H2 through the fourth capacitor C4 and the fifth capacitor C5 in sequence, and the positive input end of the second operational amplifier H2 is also grounded through the seventh resistor R7; the negative input end of the second operational amplifier H2 is electrically connected to the output end of the second operational amplifier H2 through the eighth resistor R8, and is also grounded through the ninth resistor R9; the output end of the second operational amplifier H2 is electrically connected to the fifth capacitor C5 through the tenth resistor R10, and is electrically connected to one end of the fourth capacitor C4;

[0090] The output end of the second operational amplifier H2 is the output end of the first band-pass filter circuit 21 .

[0091] Thus, the first high-pass filter circuit 212 is a first-order active high-pass filter circuit, which filters out the signal with a frequency lower than the target frequency in the signal output by the first low-pass filter circuit 211 and outputs the first sinusoidal signal TP3 of the target frequency. Figure 6 A waveform diagram of the first sinusoidal signal TP3 is shown.

[0092] Similar to the aforementioned parameter designs for the first low-pass filter circuit 211, the fourth capacitor C4, the fifth capacitor C5, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 in the first high-pass filter circuit 212 can be designed and will not be repeated here.

[0093] Alternatively, the first bandpass filter circuit 21 may also be other circuit structures, as long as it can filter out signals of other frequencies except the target frequency in the first square wave signal TP1 and output the first sinusoidal signal TP3 of the target frequency.

[0094] It should be noted that the present application does not limit the target frequency. The target frequency can be a fixed frequency or a frequency range, depending on the specific requirements.

[0095] Furthermore, the first signal conditioning circuit 22 amplifies the amplitude of the first sinusoidal signal TP3 of the target frequency, and outputs a first sinusoidal excitation signal EXC1 with an amplitude that meets the requirement.

[0096] Optional, such as Figure 2 As shown, the first signal conditioning circuit 22 includes a third operational amplifier H3, a sixth capacitor C6 and an eleventh resistor R11; wherein the output end of the first bandpass filter circuit 21 is electrically connected to the negative input end of the third operational amplifier H3 through the sixth capacitor C6; the positive input end of the third operational amplifier H3 is connected to the first collimated voltage Vdd1; the output end of the third operational amplifier H3 is electrically connected to the negative input end of the third operational amplifier H3 through the eleventh resistor R11. Optionally, the first collimated voltage Vdd1 can be +6V.

[0097] It can be understood that the third operational amplifier H3, the sixth capacitor C6 and the eleventh resistor R11 and their connection relationship constitute a proportional amplifier circuit, which amplifies the amplitude of the first sinusoidal signal TP3 of the target frequency output by the first bandpass filter circuit 21 to output the first sinusoidal excitation signal EXC1 with an amplitude that meets the requirements.

[0098] Another option, such as Figure 2 As shown, the first signal conditioning circuit 22 includes, in addition to the third operational amplifier H3, the sixth capacitor C6 and the eleventh resistor R11, a push-pull circuit 221. The push-pull circuit 221 is used to amplify the driving capability of the input signal, thereby ultimately improving the load capacity of the output first sinusoidal excitation signal EXC1, so that the amplitude and driving capability of the output first sinusoidal excitation signal EXC1 meet the requirements.

[0099] In this embodiment, optionally, Figure 2 As shown, the input end of the push-pull circuit 221 is electrically connected to the output end of the third operational amplifier H3, and the output end of the push-pull circuit 221 is electrically connected to one end of the eleventh resistor R11 electrically connected to the output end of the third operational amplifier H3, that is, the push-pull circuit 221 is located between the output end of the third operational amplifier H3 and the eleventh resistor R11, and the common end of the push-pull circuit 221 and the eleventh resistor R11 is the output end of the first signal conditioning circuit 22. In this case, the first signal conditioning circuit 22 is a push-pull proportional amplifier circuit, and the output end of the third operational amplifier H3 is fed back to the negative input end of the third operational amplifier H3 through the push-pull circuit 221 and the eleventh resistor R11 in sequence, so that the signal output by the third operational amplifier H3 is amplified by the push-pull circuit 221 for driving capability, and then fed back to the negative input end of the third operational amplifier H3 through the feedback loop, thereby performing push-pull proportional amplification on the amplitude and driving capability of the first sinusoidal signal TP3, and outputting the first sinusoidal excitation signal EXC1.

[0100] Alternatively, the input end of the push-pull circuit 221 is electrically connected to the output end of the third operational amplifier H3, and the input end of the push-pull circuit 221 is also electrically connected to one end of the eleventh resistor R11 electrically connected to the output end of the third operational amplifier H3, and the output end of the push-pull circuit 221 is the output end of the first signal conditioning circuit 22, that is, the output end of the third operational amplifier H3 is directly electrically connected to the eleventh resistor R11, and the common end of the third operational amplifier H3 and the eleventh resistor R11 is electrically connected to the input end of the push-pull circuit 221, and the output end of the push-pull circuit 221 is the output end of the first signal conditioning circuit 22. In this case, the proportional amplifier circuit formed by the third operational amplifier H3, the sixth capacitor C6 and the eleventh resistor R11 and their connection relationship amplifies the amplitude of the first sinusoidal signal TP3, and then the push-pull circuit 221 amplifies the driving capability of the first sinusoidal signal TP3 after the amplitude is amplified, and outputs the first sinusoidal excitation signal EXC1.

[0101] Both of the above methods can utilize the push-pull circuit 221 to improve the driving capability of the output first sinusoidal excitation signal EXC1 , that is, to improve the load carrying capacity of the output first sinusoidal excitation signal EXC1 .

[0102] Optional, such as Figure 2 As shown, the push-pull circuit 221 includes a first transistor Q1 and a second transistor Q2, wherein the first end of the first transistor Q1 is connected to the second DC power supply voltage Vcc2, the second end of the first transistor Q1 is electrically connected to the first end of the second transistor Q2, and the second end of the second transistor Q2 is grounded, that is, the first transistor Q1 and the second transistor Q2 are connected in series; optionally, the second DC power supply voltage Vcc2 may be +15V;

[0103] The push-pull circuit 221 also includes a first sub-branch 2211 located between the input end of the push-pull circuit 221 and the control end of the first transistor Q1, and the first sub-branch 2211 includes a first diode D1, a twelfth resistor R12, and a thirteenth resistor R13, wherein a first end of the twelfth resistor R12 is electrically connected to the input end of the push-pull circuit 211, a second end of the twelfth resistor R12 is electrically connected to the N pole of the first diode D1, and a P pole of the first diode D1 is electrically connected to the control end of the first transistor Q1 through the thirteenth resistor R13;

[0104] The P pole of the first diode D1 is also electrically connected to the first end of the first transistor Q1 through the fourteenth resistor R14, and the control end of the first transistor Q1 is electrically connected to the second end of the first transistor Q1 through the fifteenth resistor R15;

[0105] The push-pull circuit 221 also includes a second sub-branch 2212 located between the input end of the push-pull circuit 221 and the control end of the second triode Q2, and the second sub-branch 2212 includes a second diode D2, a sixteenth resistor R16, and a seventeenth resistor R17, wherein a first end of the sixteenth resistor R16 is electrically connected to the input end of the push-pull circuit 221, a second end of the sixteenth resistor R16 is electrically connected to a P-pole of the second diode D2, and an N-pole of the second diode D2 is electrically connected to the control end of the second triode Q2 through the seventeenth resistor R17;

[0106] The N-pole of the second diode D2 is also electrically connected to the second end of the second diode D2 via the eighteenth resistor R18, and the control end of the second transistor D2 is electrically connected to the first end of the second diode D2 via the nineteenth resistor R19.

[0107] like Figure 6 As shown, the first sinusoidal signal TP3 has a positive voltage signal of half a cycle and a negative voltage signal of half a cycle in one cycle. During or after the amplitude amplification of the first sinusoidal signal TP3 by the proportional amplification circuit composed of the third operational amplifier H3, the sixth capacitor C6 and the eleventh resistor R11 and their connection relationship, the first transistor Q1, the first sub-branch 2211, the fourteenth resistor R14 and the fifteenth resistor R15 constitute a driving output circuit to amplify the driving capability of the input positive half-cycle signal. Specifically, when the input positive half-cycle signal reaches the N-pole of the first diode D1 through the twelfth resistor R12, since the P-pole of the first diode D1 is electrically connected to the first end of the first transistor Q1 through the fourteenth resistor R14, that is, the N-pole of the first diode D1 is connected to the second DC power supply voltage Vcc2 through the fourteenth resistor R14, the N-pole and the P-pole of the first diode D1 are equal in potential, thereby making the first transistor The control end of the tube Q1 is at a high level, thereby turning on the first transistor Q1 and amplifying the driving capability of the input positive half-cycle signal; similarly, the second transistor Q2, the second sub-branch 2212, the eighteenth resistor R18 and the nineteenth resistor R19 constitute a pull output circuit to amplify the driving capability of the input negative half-cycle signal. Specifically, when the input negative half-cycle signal reaches the P pole of the second diode D2 through the sixteenth resistor R16, since the N pole of the second diode D2 is electrically connected to the second end of the second transistor Q2 through the eighteenth resistor R18, that is, the N pole of the second diode D2 is grounded through the eighteenth resistor R18, the P pole and the N pole of the second diode D2 are at the same potential, so that the control end of the second transistor Q2 is at a low level, thereby turning on the second transistor Q2 and amplifying the driving capability of the input negative half-cycle signal, and finally outputting the first sinusoidal excitation signal EXC1 whose amplitude and driving capability meet the requirements. The first transistor Q1 is an NPN transistor, and the second transistor Q2 is a PNP transistor.

[0108] In the present application, whether the first signal conditioning circuit 22 includes the push-pull circuit 221 or not, and whether when the first signal conditioning circuit 22 includes the push-pull circuit 221, the push-pull circuit 221 is located between the output terminal of the third operational amplifier H3 and the eleventh resistor R11, or the push-pull circuit 221 is located after the output terminal of the third operational amplifier H3 and the common terminal of the eleventh resistor R11, as Figure 2 As shown, the first signal conditioning circuit 22 may further include a seventh capacitor C7, one end of the seventh capacitor C7 being electrically connected to the negative input terminal of the third operational amplifier H3, and the other end being electrically connected to the output terminal of the third operational amplifier H3, so as to utilize the seventh capacitor C7 to increase the phase margin of the system, ensure the stability of the system loop, and avoid self-oscillation and the like.

[0109] It should be noted that if Figure 2 As shown, when the first signal conditioning circuit 22 includes a push-pull circuit 2211, and the push-pull circuit 2211 is located between the output end of the third operational amplifier H3 and the eleventh resistor R11, the output end of the third operational amplifier H3 is fed back to the negative input end of the third operational amplifier H3 through the push-pull circuit 221 and the eleventh resistor R11 in sequence. Due to the existence of this feedback loop, the cross-distortion problem of the series circuit composed of the first transistor Q1 and the second transistor Q2 can be effectively suppressed.

[0110] Figure 7 The first sinusoidal signal TP3 passes through Figure 2 Schematic diagram of the waveform of the first sinusoidal excitation signal EXC1 after push-pull ratio amplification by the first signal conditioning circuit 22.

[0111] It can be understood that the processing process of the second square wave signal TP2 by the second branch 30 is similar to the processing process of the first square wave signal TP1 by the first branch 20. Specifically, the second bandpass filter circuit 31 is used to filter out the signals of other frequencies other than the target frequency in the second square wave signal TP2, and the second sinusoidal signal TP4 of the target frequency is output, and then the second signal conditioning circuit 32 is used to amplify the amplitude of the second sinusoidal signal TP4, and the second sinusoidal excitation signal EXC2 is output. Based on any of the above embodiments, optionally, the second branch 30 and the first branch 20 have the same structure, that is, the second bandpass filter circuit 31 in the second branch 30 and the first bandpass filter circuit 21 in the first branch 20 have the same structure, and the second signal conditioning circuit 32 in the second branch 30 and the first signal conditioning circuit 22 in the first branch 20 have the same structure.

[0112] Specifically, Figure 2As shown, in the second branch 30, the second band-pass filter circuit 31 includes a second low-pass filter circuit 311 and a second high-pass filter circuit 312 which are electrically connected in sequence; wherein the second low-pass filter circuit 311 is used to filter out signals with frequencies higher than the target frequency in the second square wave signal TP2, allow signals with the target frequency and signals lower than the target frequency in the second square wave signal TP2 to pass, and output signals with the target frequency and signals lower than the target frequency in the second square wave signal TP2 to the second high-pass filter circuit 312; the second high-pass filter circuit 312 is used to filter out signals with frequencies lower than the target frequency in the signal output by the second low-pass filter circuit 311, and output a second sinusoidal signal TP4 with the target frequency, Figure 6 FIG. 4 also shows a waveform diagram of the second sinusoidal signal TP4.

[0113] like Figure 2 As shown, the second low-pass filter circuit 311 includes a fourth operational amplifier H4, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, an eighth capacitor C8 and a ninth capacitor C9;

[0114] Among them, the input end of the second branch 20 is electrically connected to the positive input end of the fourth operational amplifier H4 through the twentieth resistor R20 and the twenty-first resistor R21 in sequence, and the positive input end of the fourth operational amplifier H4 is also grounded through the eighth capacitor C8; the negative input end of the fourth operational amplifier H4 is electrically connected to the output end of the fourth operational amplifier H4 through the twenty-second resistor R22, and is also grounded through the twenty-third resistor R23; the output end of the fourth operational amplifier H4 is electrically connected to the twenty-first resistor R21 through the ninth capacitor C9 and one end of the twentieth resistor R20.

[0115] In this way, the second low-pass filter circuit 311 is a first-order active low-pass filter circuit, which filters out signals with frequencies higher than the target frequency in the second square wave signal TP2, allows signals with the target frequency and lower than the target frequency in the second square wave signal TP2 to pass, and outputs signals with the target frequency and lower than the target frequency in the second square wave signal TP2 to the second high-pass filter circuit 312.

[0116] like Figure 2 As shown, the second high-pass filter circuit 312 includes a fifth operational amplifier H5, a tenth capacitor C10, an eleventh capacitor C11, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26 and a twenty-seventh resistor R27;

[0117] The output end of the fourth operational amplifier H4 is electrically connected to the positive input end of the fifth operational amplifier H5 through the tenth capacitor C10 and the eleventh capacitor C11 in sequence, and the positive input end of the fifth operational amplifier H5 is also grounded through the twenty-fourth resistor R24; the negative input end of the fifth operational amplifier H5 is electrically connected to the output end of the fifth operational amplifier H5 through the twenty-fifth resistor R25, and is also grounded through the twenty-sixth resistor R26; the output end of the fifth operational amplifier H5 is electrically connected to the eleventh capacitor C11 and one end of the tenth capacitor C10 through the twenty-seventh resistor R27;

[0118] The output end of the fifth operational amplifier H5 is the output end of the second band-pass filter circuit 31 .

[0119] Thus, the second high-pass filter circuit 312 is a first-order active high-pass filter circuit, which filters out the signal with a frequency lower than the target frequency in the signal output by the second low-pass filter circuit 311 and outputs the second sinusoidal signal TP4 of the target frequency.

[0120] Similar to the aforementioned parameter designs for the first low-pass filter circuit 211, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the twenty-third resistor R23, the eighth capacitor C8 and the ninth capacitor C9 in the second low-pass filter circuit 311 can be designed, and the tenth capacitor C10, the eleventh capacitor C11, the twenty-fourth resistor R24, the twenty-fifth resistor R25, the twenty-sixth resistor R26 and the twenty-seventh resistor R27 in the second high-pass filter circuit 312 can be designed, which will not be repeated here.

[0121] like Figure 2 As shown, the second signal conditioning circuit 32 includes a fifth operational amplifier H5, a twelfth capacitor C12 and a twenty-eighth resistor R28; wherein, the output end of the second band-pass filter circuit 31 is electrically connected to the negative input end of the fifth operational amplifier H5 through the twelfth capacitor C12; the positive input end of the fifth operational amplifier H5 is connected to the second collimated voltage Vdd2; optionally, the second collimated voltage Vdd2 can also be +6V, and the output end of the fifth operational amplifier H5 is electrically connected to the negative input end of the fifth operational amplifier H5 through the twenty-eighth resistor R28.

[0122] It can be understood that the fifth operational amplifier H5, the twelfth capacitor C12 and the twenty-eighth resistor R28 and their connection relationship constitute a proportional amplification circuit, which amplifies the amplitude of the second sinusoidal signal TP4 of the target frequency output by the second bandpass filter circuit 31 to output a second sinusoidal excitation signal EXC2 with an amplitude that meets the requirements.

[0123] Another option, such as Figure 2As shown, the second signal conditioning circuit 32 includes, in addition to the fifth operational amplifier H5, the twelfth capacitor C12 and the twenty-eighth resistor R28, a push-pull circuit 321. The push-pull circuit 321 is used to amplify the driving capability of the input signal, improve the load capacity of the output second sinusoidal excitation signal EXC2, so that the amplitude and driving capability of the output second sinusoidal excitation signal EXC2 meet the requirements.

[0124] In this embodiment, optionally, Figure 2 As shown, the input end of the push-pull circuit 321 is electrically connected to the output end of the fifth operational amplifier H5, and the output end of the push-pull circuit 321 is electrically connected to one end of the twenty-eighth resistor R28 electrically connected to the output end of the fifth operational amplifier H5, that is, the push-pull circuit 321 is located between the output end of the fifth operational amplifier H5 and the twenty-eighth resistor R28, and the common end of the push-pull circuit 321 and the twenty-eighth resistor R28 is the output end of the second signal conditioning circuit 32. At this time, the second signal conditioning circuit 32 is a push-pull proportional amplifier circuit.

[0125] Alternatively, the input end of the push-pull circuit 321 is electrically connected to the output end of the fifth operational amplifier H5, and the input end of the push-pull circuit 321 is also electrically connected to one end of the output end of the fifth operational amplifier H5 electrically connected to the twenty-eighth resistor R28, and the output end of the push-pull circuit 321 is the output end of the second signal conditioning circuit 32, that is, the output end of the fifth operational amplifier H5 is directly electrically connected to the twenty-eighth resistor R28, and the common end of the fifth operational amplifier H5 and the twenty-eighth resistor R28 is connected to the input end of the push-pull circuit 321, and the output end of the push-pull circuit 321 is the output end of the second signal conditioning circuit 32.

[0126] Both of the above methods can utilize the push-pull circuit 321 to improve the driving capability of the output second sinusoidal excitation signal EXC2, that is, to improve the load carrying capacity of the output second sinusoidal excitation signal EXC2.

[0127] like Figure 2 As shown, the push-pull circuit 321 includes a third triode Q3 and a fourth triode Q4, wherein a first end of the third triode Q3 is connected to a third DC power supply voltage Vcc3, a second end of the third triode Q3 is electrically connected to a first end of the fourth triode Q4, and a second end of the fourth triode Q4 is grounded, that is, the third triode Q3 and the fourth triode Q4 are connected in series; optionally, the third DC power supply voltage Vcc3 may also be +15V;

[0128] The push-pull circuit 321 also includes a third sub-branch 3211 located between the input end of the push-pull circuit 321 and the control end of the third triode Q3, and the third sub-branch 3211 includes a third diode D3, a twenty-ninth resistor R29, and a thirtieth resistor R30, wherein a first end of the twenty-ninth resistor R29 is electrically connected to the input end of the push-pull circuit 311, a second end of the twenty-ninth resistor R29 is electrically connected to an N-pole of the third diode D3, and a P-pole of the third diode D3 is electrically connected to the control end of the third triode Q3 through the thirtieth resistor R30;

[0129] The P pole of the third diode D3 is also electrically connected to the first end of the third triode Q3 through a thirty-first resistor R31, and the control end of the third triode Q3 is electrically connected to the second end of the third triode Q3 through a thirty-second resistor R32;

[0130] The push-pull circuit 321 also includes a fourth sub-branch 3212 located between the input end of the push-pull circuit 321 and the control end of the fourth triode Q4, and the fourth sub-branch 3212 includes a fourth diode D4, a thirty-third resistor R33, and a thirty-fourth resistor R34, wherein a first end of the thirty-third resistor R33 is electrically connected to the input end of the push-pull circuit 321, a second end of the thirty-third resistor R33 is electrically connected to a P-pole of the fourth diode D4, and an N-pole of the fourth diode D4 is electrically connected to the control end of the fourth triode D4 through the thirty-fourth resistor R34;

[0131] The N-pole of the fourth triode D4 is also electrically connected to the second end of the fourth triode D4 through the thirty-fifth resistor R35, and the control end of the fourth triode D4 is electrically connected to the first end of the fourth triode D4 through the thirty-sixth resistor R36.

[0132] like Figure 6 As shown, the second sinusoidal signal TP4 has a positive voltage signal of half a cycle and a negative voltage signal of half a cycle in one cycle. During or after the amplitude amplification of the second sinusoidal signal TP4 by the proportional amplification circuit composed of the fifth operational amplifier H5, the twelfth capacitor C12 and the twenty-eighth resistor R28 and their connection relationship, the third transistor Q3, the third sub-branch 3211, the thirty-first resistor R31 and the thirty-second resistor R32 constitute a push output circuit to amplify the driving capability of the input positive half-cycle signal; similarly, the fourth transistor Q4, the fourth sub-branch 3212, the thirty-fifth resistor R35 and the thirty-sixth resistor R36 constitute a pull output circuit to amplify the driving capability of the input negative half-cycle signal, and finally output the second sinusoidal excitation signal EXC2 with both amplitude and driving capability meeting the requirements. Among them, the third transistor Q3 is an NPN transistor, and the fourth transistor Q4 is a PNP transistor.

[0133] In the present application, whether the second signal conditioning circuit 32 includes the push-pull circuit 3211 or not, and whether the push-pull circuit 3211 is located between the output terminal of the fifth operational amplifier H5 and the twenty-eighth resistor R28, or the push-pull circuit 3211 is located after the output terminal of the fifth operational amplifier H5 and the common terminal of the twenty-eighth resistor R28, as shown in FIG. Figure 2 As shown, the second signal conditioning circuit 32 may further include a thirteenth capacitor C13, one end of the thirteenth capacitor C13 being electrically connected to the negative input terminal of the fifth operational amplifier H5, and the other end being electrically connected to the output terminal of the fifth operational amplifier H5, so as to utilize the thirteenth capacitor C13 to increase the phase margin of the system, ensure the stability of the system loop, and avoid self-oscillation and the like.

[0134] It should be noted that if Figure 2 As shown, when the second signal conditioning circuit 32 includes a push-pull circuit 3211, and the push-pull circuit 3211 is located between the output end of the fifth operational amplifier H5 and the twenty-eighth resistor R28, the output end of the fifth operational amplifier H5 is fed back to the negative input end of the fifth operational amplifier H5 through the push-pull circuit 321 and the twenty-eighth resistor R28 in sequence. Due to the existence of this feedback loop, the cross-distortion problem of the series circuit composed of the third transistor Q3 and the fourth transistor Q4 can be effectively suppressed.

[0135] Figure 7 It also shows that the second sinusoidal signal TP4 passes through Figure 2 Schematic diagram of the waveform of the second sinusoidal excitation signal EXC2 after push-pull ratio amplification by the second signal conditioning circuit 32.

[0136] Finally, the first sinusoidal excitation signal EXC1 and the second sinusoidal excitation signal EXC2 are input into the rotary transformer through the output interface.

[0137] Alternatively, the second bandpass filter circuit 31 in the second branch 30 may have a different structure from the first bandpass filter circuit 21 in the first branch 20, and the second signal conditioning circuit 32 in the second branch 30 may have a different structure from the first signal conditioning circuit 22 in the first branch 20, as long as it can ultimately output a second sinusoidal excitation signal EXC2 that has the same frequency and a phase difference of π as the first sinusoidal excitation signal EXC1.

[0138] An embodiment of the present application further provides an electronic device, which includes the resolver excitation signal generating circuit provided by any of the above embodiments. Since the resolver excitation signal generating circuit has been described in detail in the above embodiments, it will not be repeated here.

[0139] The various parts in this manual are described in a combination of parallel and progressive ways. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0140] With respect to the above description of the disclosed embodiments, the features described in the embodiments in this specification may be replaced or combined with each other, so that professionals in the field can implement or use the present application. Various modifications to these embodiments will be apparent to professionals in the field, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A resolver excitation signal generating circuit, characterized in that: It includes a square wave generating circuit, a first branch and a second branch; The square wave generating circuit is used to generate a first square wave signal and output it to the first branch, and to generate a second square wave signal and output it to the second branch, wherein the first square wave signal and the second square wave signal have the same frequency and a phase difference of π; The first branch includes a first bandpass filter circuit and a first signal conditioning circuit electrically connected in sequence, the first bandpass filter circuit is used to filter out signals of other frequencies other than the target frequency in the first square wave signal, and output a first sinusoidal signal of the target frequency; the first signal conditioning circuit is used to amplify the amplitude of the first sinusoidal signal and output a first sinusoidal excitation signal; The second branch includes a second bandpass filter circuit and a second signal conditioning circuit electrically connected in sequence, the second bandpass filter circuit is used to filter out signals of other frequencies other than the target frequency in the second square wave signal, and output a second sinusoidal signal of the target frequency; the second signal conditioning circuit is used to amplify the amplitude of the second sinusoidal signal and output a second sinusoidal excitation signal.

2. The resolver excitation signal generating circuit according to claim 1, characterized in that: The square wave generating circuit includes a 555 timer, a first resistor, a second resistor, a first capacitor and an inverter; The power pin of the 555 timer is connected to a first DC power supply voltage, and the power pin of the 555 timer is also connected to ground via the first resistor and the first capacitor in sequence; The threshold pin and the trigger pin of the 555 timer are both electrically connected to an end of the first capacitor away from the ground; The reset pin of the 555 timer is electrically connected to the power pin of the 555 timer; The output pin of the 555 timer is electrically connected to the trigger pin of the 555 timer through the second resistor; The output pin of the 555 timer is also electrically connected to the input end of the first branch, and the output pin of the 555 timer is also electrically connected to the input end of the second branch through the inverter.

3. The resolver excitation signal generating circuit according to claim 1, characterized in that: The first band-pass filter circuit comprises a first low-pass filter circuit and a first high-pass filter circuit electrically connected in sequence; The first low-pass filter circuit is used to filter out signals with a frequency higher than the target frequency in the first square wave signal, and output the signal to the first high-pass filter circuit; The first high-pass filter circuit is used to filter out signals with frequencies higher than the target frequency in the signal output by the first low-pass filter circuit, and output the first sinusoidal signal of the target frequency.

4. The resolver excitation signal generating circuit according to claim 3, characterized in that: The first low-pass filter circuit includes a first operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a second capacitor and a third capacitor; The input end of the first branch is electrically connected to the positive input end of the first operational amplifier through the third resistor and the fourth resistor in sequence, and the positive input end of the first operational amplifier is also grounded through the second capacitor; the negative input end of the first operational amplifier is electrically connected to the output end of the first operational amplifier through the fifth resistor and is also grounded through the sixth resistor; the output end of the first operational amplifier is electrically connected to the fourth resistor through the third capacitor and is electrically connected to one end of the third resistor; The first high-pass filter circuit includes a second operational amplifier, a fourth capacitor, a fifth capacitor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor; The output end of the first operational amplifier is electrically connected to the positive input end of the second operational amplifier through the fourth capacitor and the fifth capacitor in sequence, and the positive input end of the second operational amplifier is also grounded through the seventh resistor; the negative input end of the second operational amplifier is electrically connected to the output end of the second operational amplifier through the eighth resistor, and is also grounded through the ninth resistor; the output end of the second operational amplifier is electrically connected to the fifth capacitor through the tenth resistor and one end of the fourth capacitor is electrically connected; The output end of the second operational amplifier is the output end of the first band-pass filter circuit.

5. The resolver excitation signal generating circuit according to claim 1, characterized in that: The first signal conditioning circuit includes a third operational amplifier, a sixth capacitor and an eleventh resistor; Among them, the output end of the first band-pass filter circuit is electrically connected to the negative input end of the third operational amplifier through the sixth capacitor; the positive input end of the third operational amplifier is connected to the first collimated voltage; the output end of the third operational amplifier is electrically connected to the negative input end of the third operational amplifier through the eleventh resistor.

6. The resolver excitation signal generating circuit according to claim 5, characterized in that: The first signal conditioning circuit further includes a seventh capacitor, one end of the seventh capacitor is electrically connected to the negative input terminal of the third operational amplifier, and the other end of the seventh capacitor is electrically connected to the output terminal of the third operational amplifier.

7. The resolver excitation signal generating circuit according to claim 5, characterized in that: The first signal conditioning circuit further includes a push-pull circuit, and the push-pull circuit is used to amplify the driving capability of the input signal; The input end of the push-pull circuit is electrically connected to the output end of the third operational amplifier, the output end of the push-pull circuit is electrically connected to one end of the eleventh resistor electrically connected to the output end of the third operational amplifier, and the common end of the push-pull circuit and the eleventh resistor is the output end of the first signal conditioning circuit; Alternatively, the input end of the push-pull circuit is electrically connected to the output end of the third operational amplifier, and the input end of the push-pull circuit is also electrically connected to one end of the eleventh resistor electrically connected to the output end of the third operational amplifier, and the output end of the push-pull circuit is the output end of the first signal conditioning circuit.

8. The resolver excitation signal generating circuit according to claim 7, characterized in that: The push-pull circuit comprises a first triode and a second triode, wherein a first end of the first triode is connected to a second DC power supply voltage, a second end of the first triode is electrically connected to a first end of the second triode, and a second end of the second triode is grounded; The push-pull circuit further includes a first sub-branch located between the input end of the push-pull circuit and the control end of the first transistor, the first sub-branch includes a first diode, a twelfth resistor and a thirteenth resistor, wherein the first end of the twelfth resistor is electrically connected to the input end of the push-pull circuit, the second end of the twelfth resistor is electrically connected to the N pole of the first diode, and the P pole of the first diode is electrically connected to the control end of the first transistor through the thirteenth resistor; The P pole of the first diode is also electrically connected to the first end of the first transistor through a fourteenth resistor, and the control end of the first transistor is electrically connected to the second end of the first transistor through a fifteenth resistor; The push-pull circuit further includes a second sub-branch located between the input end of the push-pull circuit and the control end of the second triode, the second sub-branch includes a second diode, a sixteenth resistor and a seventeenth resistor, wherein a first end of the sixteenth resistor is electrically connected to the input end of the push-pull circuit, a second end of the sixteenth resistor is electrically connected to a P-pole of the second diode, and an N-pole of the second diode is electrically connected to the control end of the second triode through the seventeenth resistor; The N-pole of the second diode is also electrically connected to the second end of the second transistor through an eighteenth resistor, and the control end of the second transistor is electrically connected to the first end of the second transistor through a nineteenth resistor.

9. The resolver excitation signal generating circuit according to any one of claims 1 to 8, characterized in that: The second branch has the same structure as the first branch.

10. An electronic device, characterized in that: The invention comprises the resolver excitation signal generating circuit as described in any one of claims 1 to 9.

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