IBC solar cell piece, cell assembly and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar cells, and provides an IBC solar cell piece, a cell assembly and a photovoltaic system, in the IBC solar cell piece, the back face of a silicon wafer comprises an edge region and a middle region, the edge region is arranged around the middle region, a first emitter doping layer and a base region doping layer are arranged on the middle region, and a second emitter doping layer is arranged on the base region doping layer. A second emitter doping layer is arranged on the edge area, the doping type of the second emitter doping layer is the same as that of the first emitter doping layer and is opposite to that of the silicon wafer, and the second emitter doping layer comprises a first doping part, a second doping part, a third doping part and a fourth doping part which are located at the four edges of the back face respectively. Therefore, the back surface is divided into the edge region and the middle region, and the edge region is provided with the second emitter doping layer which is provided with the four doping parts and is opposite to the silicon wafer in polarity, so that the area of the emitter in the IBC solar cell can be increased, and the efficiency of the IBC solar cell is improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to an IBC solar cell sheet, a battery assembly and a photovoltaic system. Background Art

[0002] Among solar cells, a back-contact solar cell is one in which both the p-region and the n-region are arranged on the back side (non-light-receiving side) of the cell. The light-receiving side of the cell is not blocked by any metal electrode, thereby effectively increasing the short-circuit current of the cell.

[0003] In the related art, in an IBC solar cell (i.e., a back-contact solar cell), the doping layer and the electrode are designed on the back side, and need to be designed as a crossed p-region and N-region, wherein the p-region and the N-region are evenly arranged in one direction, the area of ​​the back emitter region accounts for a small proportion, and the conversion efficiency of the battery is low. Utility Model Content

[0004] The present application provides an IBC solar cell sheet, a battery assembly and a photovoltaic system.

[0005] The present application is implemented in this way. The IBC solar cell sheet of the embodiment of the present application includes:

[0006] A silicon wafer, the silicon wafer having a back side and a front side opposite to each other, the back side having a first edge and a second edge opposite to each other along a first direction, and having a third edge and a fourth edge opposite to each other along a second direction, wherein the second direction intersects the first direction; the back side comprising a middle area and an edge area surrounding the middle area;

[0007] a plurality of first emitter doping layers and a plurality of base doping layers, wherein the plurality of first emitter doping layers and the plurality of base doping layers are arranged alternately in sequence along the first direction on the middle region, wherein the first emitter doping layers and the base doping layers extend continuously along the second direction, and the first emitter doping layers and the base doping layers have opposite doping types; and

[0008] a second emitter doping layer, wherein the second emitter doping layer is disposed on the edge region, the doping type of the second emitter doping layer is opposite to the doping type of the silicon wafer, and the second emitter doping layer has the same doping type as the first emitter doping layer;

[0009] Among them, the second emitter doping layer includes a first doping portion, a second doping portion, a third doping portion and a fourth doping portion, the first doping portion is arranged at the first edge and extends continuously along the second direction, the second doping portion is arranged at the second edge and extends continuously along the second direction, the third doping portion is arranged at the third edge and extends continuously along the first direction, the fourth doping portion is arranged at the fourth edge and extends continuously along the first direction, and the first doping portion, the second doping portion, the third doping portion and the fourth doping portion are all insulated and isolated from the base doping layer.

[0010] Furthermore, when the doping type of the silicon wafer is p-type doping, the doping type of the first emitter doping layer is n-type doping, the doping type of the base doping layer is p-type doping, and the doping type of the second emitter doping layer is n-type doping;

[0011] When the doping type of the silicon wafer is n-type doping, the doping type of the first emitter doping layer is p-type doping, the doping type of the base doping layer is n-type doping, and the doping type of the second emitter doping layer is p-type doping.

[0012] Furthermore, two ends of the third doping portion are connected to the first doping portion and the second doping portion respectively; and / or

[0013] Two ends of the fourth doping portion are connected to the first doping portion and the second doping portion respectively.

[0014] Furthermore, the third doped portion is connected to a plurality of the first emitter doped layers; and / or

[0015] The fourth doped portion is connected to a plurality of the first emitter doped layers.

[0016] Furthermore, a first auxiliary gate is provided on the first emitter doping layer, a second auxiliary gate is provided on the base doping layer, and both the first auxiliary gate and the second auxiliary gate extend along the second direction;

[0017] A third sub-grid is disposed on the first doped portion, a fourth sub-grid is disposed on the second doped portion, and the third sub-grid and the fourth sub-grid extend continuously along the second direction;

[0018] A fifth sub-gate is disposed on the third doped portion, a sixth sub-gate is disposed on the fourth doped portion, the fifth sub-gate and the sixth sub-gate extend continuously along the first direction, and the fifth sub-gate and the sixth sub-gate are both insulated and isolated from the second sub-gate.

[0019] Furthermore, the IBC solar cell sheet further includes a plurality of first main grids and a plurality of second main grids, which are alternately arranged in sequence along the second direction and extend along the first direction, the first main grid is electrically connected to the first sub-grid, the third sub-grid and the fourth sub-grid and is insulated and isolated from the second sub-grid, and the second main grid is electrically connected to the second sub-grid and is insulated and isolated from the first sub-grid, the third sub-grid and the fourth sub-grid.

[0020] Furthermore, the second main gate does not extend above the first doped portion and the second doped portion; or

[0021] The second main gate extends to above the first doped portion and the second doped portion and intersects the third sub-gate and the fourth sub-gate. An insulating layer is provided at the position where the third sub-gate and the fourth sub-gate intersect the second main gate, and the second main gate is located above the insulating layer.

[0022] Furthermore, the fifth sub-grid is electrically connected to the third sub-grid and the fourth sub-grid; and / or

[0023] The sixth sub-grid is electrically connected to the third sub-grid and the fourth sub-grid.

[0024] Furthermore, the widths of the third sub-grid and the fourth sub-grid in the first direction are greater than the widths of the first sub-grid and the second sub-grid in the first direction.

[0025] Furthermore, a third main gate is further provided on the third doped portion, the third main gate continuously extends along the first direction and is electrically connected to the fifth sub-gate, and the third main gate is not electrically connected to the second sub-gate; and / or

[0026] The width of at least a portion of the fifth sub-gate in the second direction is greater than the widths of the first sub-gate and the second sub-gate in the first direction.

[0027] Furthermore, a fourth main gate is further provided on the fourth doped portion, the fourth main gate continuously extends along the first direction and is electrically connected to the sixth sub-gate, and the fourth main gate is not electrically connected to the second sub-gate; and / or

[0028] The width of at least a portion of the sixth sub-gate in the second direction is greater than the widths of the first sub-gate and the second sub-gate in the first direction.

[0029] The present application also provides a battery assembly, comprising a plurality of IBC solar cells as described in any one of the above items.

[0030] The present application also provides a photovoltaic system, which includes the above-mentioned battery assembly.

[0031] In the IBC solar cell, battery assembly and photovoltaic system in the embodiment of the present application, the back side includes an edge region and a middle region, the edge region is arranged around the middle region, a first emitter doping layer and a base doping layer are arranged on the middle region, a second emitter doping layer is arranged on the edge region, the second emitter doping layer has the same doping type as the first emitter doping layer and is opposite to the doping type of the silicon wafer, and the second emitter doping layer includes a first doping part, a second doping part, a third doping part and a fourth doping part respectively located at the four edges of the back side. In this way, compared with the traditional solution of using doping layers of different polarities to be alternately and evenly arranged in one direction, the present application divides the back side into an edge region and a middle region, and arranges a second emitter doping layer having four doping parts and opposite to the polarity of the silicon wafer on the edge region, so as to increase the emitter area in the IBC solar cell, thereby improving the efficiency of the IBC solar cell.

[0032] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a module schematic diagram of a photovoltaic system provided in an embodiment of the present application;

[0034] Figure 2 It is a schematic diagram of the planar structure of the silicon wafer of the IBC solar cell provided in the embodiment of the present application;

[0035] Figure 3 It is a schematic diagram of the planar structure of an IBC solar cell provided in an embodiment of the present application;

[0036] Figure 4 is another schematic diagram of the planar structure of the IBC solar cell provided in an embodiment of the present application;

[0037] Figure 5 It is another schematic diagram of the planar structure of the IBC solar cell provided in the embodiment of the present application;

[0038] Figure 6 is another schematic diagram of the planar structure of the IBC solar cell provided in an embodiment of the present application;

[0039] Figure 7 This is another schematic diagram of the planar structure of the IBC solar cell provided in the embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. It should be noted that the embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] In the description of the present application, it should be understood that the terms "up", "down", "left", "right", "horizontal", "vertical", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "several" is two or more, unless otherwise clearly and specifically defined.

[0043] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0044] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0045] See also Figure 1 The photovoltaic system 1000 in the embodiment of the present application may include the battery assembly 200 in the embodiment of the present application. The battery assembly 200 in the embodiment of the present application may include several IBC solar cells 100 in the embodiment of the present application. Several IBC solar cells 100 may be connected in series through welding ribbons to form several battery strings. Each battery string may be connected in series, in parallel, or in series and parallel to form a battery assembly 200.

[0046] Please combine Figure 2 and Figure 3 The IBC solar cell 100 in the embodiment of the present application may include a silicon wafer 10 , a plurality of first emitter doping layers 20 , a plurality of base doping layers 30 and a second emitter doping layer 40 .

[0047] like Figure 2 As shown, the silicon wafer 10 has a back side 11 and a front side (not shown), the back side 11 has a first edge 111 and a second edge 112 in a first direction, and has a third edge 113 and a fourth edge 114 in a second direction, the second direction intersecting the first direction. The back side 11 includes an edge region 115 and a middle region 116, and the edge region 115 is arranged around the middle region 116.

[0048] Specifically, the first direction may be the longitudinal direction of the IBC solar cell 100, and the second direction may be the lateral direction of the IBC solar cell 100, and the two directions are perpendicular to each other. Figure 2 In the example shown, the first edge 111 is the upper edge in the longitudinal direction, the second edge 112 is the lower edge in the longitudinal direction, the third edge 113 is the left edge in the transverse direction, and the fourth edge 114 is the right edge in the transverse direction. The edge region 115 refers to the region located at the four edges of the silicon wafer 10, which is roughly in the shape of a square, and the edge region 115 is arranged around the middle region 116.

[0049] Please combine Figure 2 and Figure 3 , a plurality of first emitter doping layers 20 and a plurality of base doping layers 30 are disposed on the middle region 116. A plurality of first emitter doping layers 20 and a plurality of base doping layers 30 are alternately arranged in sequence along the first direction and extend continuously along the second direction. The first emitter doping layers 20 and the base doping layers 30 have opposite doping types.

[0050] The second emitter doping layer 40 is disposed on the edge region 115 . The doping type of the second emitter doping layer 40 is opposite to the doping type of the silicon wafer 10 , and the second emitter doping layer 40 is the same as the doping type of the first emitter doping layer 20 .

[0051] Among them, the second emitter doping layer 40 includes a first doping portion 41, a second doping portion 42, a third doping portion 43 and a fourth doping portion 44, the first doping portion 41 is arranged at the first edge 111 and extends continuously along the second direction, the second doping portion 42 is arranged at the second edge 112 and extends continuously along the second direction, the third doping portion 43 is arranged at the third edge 113 and extends continuously along the first direction, the fourth doping portion 44 is arranged at the fourth edge 114 and extends continuously along the first direction, and the first emitter doping layer 20, the first doping portion 41, the second doping portion 42, the third doping portion 43 and the fourth doping portion are all insulated and isolated from the base doping layer 30.

[0052] It should be noted that, in the embodiments of the present application, "continuous extension" can be understood as the structure being continuous and uninterrupted in the extension direction, with no interruption area in the middle. That is to say, in this article, the first emitter doping layer 20, the base doping layer 30, the first doping part 41, the second doping part 42, the third doping part 43 and the fourth doping part 44 are all continuous and uninterrupted structures in their respective extension directions. In the following, if there is a description of "continuous extension", please refer to this for understanding.

[0053] In the IBC solar cell 100, the battery assembly 200 and the photovoltaic system 1000 in the embodiment of the present application, the back side 11 includes an edge region 115 and a middle region 116, the edge region 115 is arranged around the middle region 116, a first emitter doping layer 20 and a base doping layer 30 are arranged on the middle region 116, and a second emitter doping layer 40 is arranged on the edge region 115, the second emitter doping layer 40 has the same doping type as the first emitter doping layer 20 and is opposite to the doping type of the silicon wafer 10, and the second emitter doping layer 40 includes a first doping portion 41, a second doping portion 42, a third doping portion 43 and a fourth doping portion 44 respectively located at the four edges of the back side 11. Thus, compared with the conventional solution of using doping layers of different polarities to be alternately and evenly arranged in sequence along one direction, the present application divides the back side 11 into an edge region 115 and a middle region 116, and provides a second emitter doping layer 40 having four doping parts and opposite polarity to the silicon wafer 10 on the edge region 115, thereby increasing the area of ​​the emitter in the IBC solar cell 100, thereby improving the efficiency of the IBC solar cell 100.

[0054] Specifically, in the embodiment of the present application, the first doping portion 41 is arranged at the position of the first edge 111, and the upper edge of the first doping portion 41 may coincide with the first edge 111, or there may be a preset distance between the upper edge of the first doping portion 41 and the first edge 111, which may be determined according to the specific manufacturing process and is not limited here. Similarly, the second doping portion 42 is arranged at the position of the second edge 112, and the lower edge of the second doping portion 42 may coincide with the second edge 112, or there may be a preset distance between the lower edge of the second doping portion 42 and the second edge 112. The third doping portion 43 is arranged at the position of the third edge 113, and the left edge of the third doping portion 43 may coincide with the third edge 113, or there may be a preset distance between the left edge of the third doping portion 43 and the third edge 113. The fourth doping portion 44 is arranged at the position of the fourth edge 114, and the right edge of the fourth doping portion 44 may coincide with the fourth edge 114, or there may be a preset distance between the right edge of the fourth doping portion 44 and the fourth edge 114, which is not limited here. What is shown in the figure is that each doping part has a preset distance from the edge, which is only for the purpose of clearly expressing the existence of the silicon wafer 10 and is only schematic, and it is not necessary to have each doping part have a preset distance from the edge.

[0055] Exemplarily, the first doped portion 41 may extend from the third edge 113 to the fourth edge 114; and / or, the second doped portion 42 may extend from the third edge 113 to the fourth edge 114; and / or, the third doped portion 43 may extend from the first edge 111 to the second edge 112; and / or, the fourth doped portion 44 may extend from the first edge 111 to the second edge 112.

[0056] In the embodiment of the present application, the silicon wafer 10 may be a p-type silicon wafer or an N-type silicon wafer, that is, the doping type of the silicon wafer 10 may be p-type doping or n-type doping.

[0057] When the doping type of the silicon wafer 10 is p-type doping, the doping type of the first emitter doping layer 20 is n-type doping, the doping type of the base doping layer 30 is p-type doping, and the doping type of the second emitter doping layer 40 is n-type doping.

[0058] When the doping type of the silicon wafer 10 is n-type doping, the doping type of the first emitter doping layer 20 is p-type doping, the doping type of the base doping layer 30 is n-type doping, and the doping type of the second emitter doping layer 40 is p-type doping.

[0059] That is to say, no matter what doping type the silicon wafer 10 is, the first emitter doping layer 20 in the middle region 116 and the second emitter doping layer 40 on the edge region 115 are both emitters of the IBC solar cell 100 .

[0060] In this way, by disposing the second emitter doping layer 40 with a doping type opposite to that of the silicon wafer 10 at the positions located at the four edges of the silicon wafer 10 in the edge region 115 , the emitter area can be increased, thereby improving efficiency.

[0061] In addition, it should be noted that in the embodiments of the present application, "insulation isolation" means that there is no conduction between the two. It can be achieved by forming a groove between the two, or by providing other insulating dielectric films between the two to achieve insulation between the two. There is no specific limitation here.

[0062] See also Figure 4 In some embodiments, two ends of the third doping portion 43 may be connected to the first doping portion 41 and the second doping portion 42 respectively.

[0063] In this way, the first doping part 41, the second doping part 42 and the third doping part 43 can be used as a whole, without setting the third doping part 43 and the first doping part 41 and the third doping part 43 and the second doping part 42 in an isolated state, which can reduce the area of ​​the ineffective area of ​​the entire silicon wafer 10 (that is, the area covered by the doping layer) and improve the efficiency of the IBC solar cell 100. At the same time, when the auxiliary grid is subsequently set for current collection and the main grid and / or welding strip are set for current convergence, it is only necessary to turn on the auxiliary grid on the first doping part 41, the second doping part 42 and the third doping part 43 to realize the collection of the current of the third doping part 43, and it is not necessary to set the main grid on the third doping part 43 to realize the current collection of the third doping part 43 located at the third edge 113.

[0064] Of course, in some embodiments, the two ends of the third doping portion 43 may not be connected to the first doping portion 41 and the second doping portion 42 , and no specific limitation is made herein.

[0065] Also, please read Figure 4 In some embodiments, two ends of the fourth doping portion 44 may be connected to the first doping portion 41 and the second doping portion 42 respectively.

[0066] In this way, the first doping part 41, the second doping part 42 and the fourth doping part 44 can be used as a conductive whole, without setting the fourth doping part 44 and the first doping part 41 and the fourth doping part 44 and the second doping part 42 in an isolated state, which can reduce the area of ​​the ineffective area of ​​the entire silicon wafer 10 (that is, the area covered by the doping layer) and improve the efficiency of the IBC solar cell 100. At the same time, when the auxiliary grid is subsequently set for current collection and the main grid and / or welding strip are set for current convergence, it is only necessary to turn on the auxiliary grid on the first doping part 41, the second doping part 42 and the fourth doping part 44 to realize the collection of the current of the fourth doping part 44, and it is not necessary to set the main grid on the fourth doping part 44 to realize the current collection of the fourth doping part 44 located at the third edge 113.

[0067] Of course, in some embodiments, the two ends of the fourth doping portion 44 may not be connected to the first doping portion 41 and the second doping portion 42 , and this is not specifically limited herein.

[0068] See also Figure 3 and Figure 4 In some embodiments, the third doping portion 43 may be connected to a plurality of first emitter doping layers 20 .

[0069] In this way, the third doped portion 43 and the first emitter doped layer 20 can be connected as a whole without isolating the two, and the area of ​​the ineffective region of the entire silicon wafer 10 (i.e., the area covered by the doped layer) can be reduced, thereby improving the efficiency of the IBC solar cell 100.

[0070] Of course, it is understandable that, in some embodiments, the third doping portion 43 is also not connected to the first emitter doping layer 20 , and no specific limitation is made here.

[0071] Similarly, please continue to refer to Figure 3 and Figure 4 In some embodiments, the fourth doping portion 44 may be connected to a plurality of first emitter doping layers 20 .

[0072] In this way, the fourth doped portion 44 and the first emitter doped layer 20 can be connected as a whole without isolating the two, and the area of ​​the ineffective region of the entire silicon wafer 10 (ie, the area covered by the doped layer) can be reduced, thereby improving the efficiency of the IBC solar cell 100.

[0073] Of course, it is understandable that, in some embodiments, the fourth doping portion 44 is also not connected to the first emitter doping layer 20 , and no specific limitation is made here.

[0074] See also Figure 3 and Figure 4In some embodiments, a first sub-gate 21 is disposed on the first emitter doping layer 20 , and a second sub-gate 31 is disposed on the base doping layer 30 . Both the first sub-gate 21 and the second sub-gate 31 extend along the second direction.

[0075] A third sub-gate 411 is provided on the first doped portion 41, a fourth sub-gate 421 is provided on the second doped portion 42, the third sub-gate 411 and the fourth sub-gate 421 extend continuously along the second direction, a fifth sub-gate 431 is provided on the third doped portion 43, a sixth sub-gate 441 is provided on the fourth doped portion 44, the fifth sub-gate 431 and the sixth sub-gate 441 extend continuously along the first direction, and the fifth sub-gate 431 and the sixth sub-gate 441 are both insulated and isolated from the second sub-gate 21.

[0076] In this way, the current can be collected by arranging a secondary grid on each doping layer and each doping part, and then the current can be outputted by the main grid and / or the welding tape.

[0077] Specifically, in such an embodiment, the first sub-gate 21 is used to collect the current of the first emitter doping layer 20, the second sub-gate 31 is used to collect the current of the base doping layer 30, the third sub-gate 411 is used to collect the current of the first doping part 41, the fourth sub-gate 421 is used to collect the current of the second doping part 42, the fifth sub-gate 431 is used to collect the current of the third doping part 43, and the sixth sub-gate 441 is used to collect the current of the fourth doping part 44.

[0078] It is easy to understand that in the IBC solar cell 100, the back side 11 is covered with a passivation film layer, and each sub-grid can form an ohmic contact with the corresponding doping layer or doping part by burning through the passivation film layer or laser grooving to achieve current collection.

[0079] For further information, see Figure 5 In some embodiments, the IBC solar cell 100 may be an IBC solar cell with a main grid. In this case, the IBC solar cell 100 may include a plurality of first main grids 50 and a plurality of second main grids 60, and the plurality of first main grids 50 and the plurality of second main grids 60 are alternately arranged in sequence along the second direction and extend along the first direction.

[0080] The first main gate 50 is electrically connected to the first sub-gate 21, the third sub-gate 411 and the fourth sub-gate 421 and is insulated from the second sub-gate 21. The second main gate 60 is electrically connected to the second sub-gate 31 and is insulated from the first sub-gate 21, the third sub-gate 411 and the fourth sub-gate 421.

[0081] Thus, by providing the first main grid 50 and the second main grid 60 , the first main grid 50 can converge the current collected by the first sub-grid 21 , the third sub-grid 411 and the fourth sub-grid 421 , and the second main grid 60 can converge the current collected by the second sub-grid 31 .

[0082] It can be understood that the insulation isolation between the first main grid 50 and the second auxiliary grid 31 can be achieved by coating an insulating glue at the intersection of the two or the second auxiliary grid 31 is disconnected at the position of the first main grid 50, and the insulation isolation between the second main grid 60 and the first main grid 21 can be achieved by coating an insulating glue at the intersection of the two or the first main grid 21 is disconnected at the position of the second main grid 60 (such as Figure 5 shown).

[0083] Of course, it is understandable that in other embodiments, the IBC solar cell 100 may be a main grid-less IBC solar cell. In this case, a welding pad may be directly provided on the secondary grid to be welded to the welding ribbon, and no specific limitation is made here.

[0084] See also Figure 5 In some embodiments, the second main gate 60 does not extend above the first doped portion 41 and the second doped portion 42 .

[0085] In this way, the second main gate 60 and the third sub-gate 411 and the fourth sub-gate 421 can be prevented from contacting and causing leakage.

[0086] Of course, see Figure 6 In some embodiments, the second main gate 60 may also extend above the first doped portion 41 and the second doped portion 42 and intersect the third sub-gate 411 and the fourth sub-gate 421. In this case, an insulating layer 90 is provided at the position where the third sub-gate 411 and the fourth sub-gate 421 intersect the second main gate 60, and the second main gate 60 is located above the insulating layer 90.

[0087] In this way, even if the second main gate 60 extends to above the first doped portion 41 and the second doped portion 42 , it can be insulated from the third sub-gate 411 and the fourth sub-gate 421 by the insulating layer 90 to prevent leakage.

[0088] See also Figure 4 and Figure 5 In some embodiments, the fifth sub-gate 431 may be electrically connected to the third sub-gate 411 and the fourth sub-gate 421 .

[0089] In this way, by connecting the fifth sub-gate 431 on the third doped portion 43 with the third sub-gate 411 on the first doped portion 41 and the fourth sub-gate 421 on the second doped portion 42, the current collected by the fifth sub-gate 431 can be directly converged to the first main gate 50 through the third sub-gate 411 and the fourth sub-gate 421, without the need to set a main gate and a welding tape on the third doped portion 43 to collect and output the current, and without the need to perform welding at the position of the third edge 113 of the silicon wafer 10, which can avoid stress concentration at the edge position during welding and causing cracks.

[0090] Specifically, in such an embodiment, portions at both ends of the third doping portion 43 may be connected to the first doping portion 41 and the second doping portion 42, respectively. In such a case, when printing the sub-grid, a continuous sub-grid is formed on the first doping portion 41, the third doping portion 43 and the second doping portion 42, and the continuous sub-grid is in contact with the doping portion below, and the third sub-grid 411, the fifth sub-grid 431 and the fourth sub-grid 421 may be connected in sequence.

[0091] Similarly, please continue to refer to Figure 4 and Figure 5 In some embodiments, the sixth sub-gate 441 may also be electrically connected to the third sub-gate 411 and the fourth sub-gate 421 .

[0092] In this way, by connecting the sixth sub-gate 441 on the fourth doped portion 44 with the third sub-gate 411 on the first doped portion 41 and the fourth sub-gate 421 on the second doped portion 42, the current collected by the sixth sub-gate 441 can be directly converged to the first main gate 50 through the third sub-gate 411 and the fourth sub-gate 421, without the need to set a main gate and a welding tape on the fourth doped portion 44 to collect and output the current, and without the need to perform welding at the position of the fourth edge 114 of the silicon wafer 10, which can avoid stress concentration at the edge position during welding and causing cracks.

[0093] Specifically, in such an embodiment, portions at both ends of the fourth doping portion 44 can be connected to the first doping portion 41 and the second doping portion 42, respectively. In this case, when printing the sub-grid, a continuous sub-grid is formed on the first doping portion 41, the fourth doping portion 44 and the second doping portion 42, and the continuous sub-grid is in contact with the doping portion below, and the third sub-grid 411, the sixth sub-grid 441 and the fourth sub-grid 421 can be connected in sequence.

[0094] In some embodiments, Figure 4 and Figure 5 As shown, the first doped portion 41, the third doped portion 43, the second doped portion 42 and the fourth doped portion 44 can be connected end to end to form a U-shaped. The third sub-gate 411, the fifth sub-gate 431, the fourth sub-gate 421 and the sixth sub-gate 441 are also connected in sequence to form a U-shaped.

[0095] Furthermore, in some embodiments, the widths of the third sub-gate 411 and the fourth sub-gate 421 in the first direction are greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0096] In this way, when the main grid and the welding strip are not arranged on the third doped part 43 and / or the fourth doped part 44, the third sub-grid 411 and the fourth sub-grid 421, in addition to being used to collect the current of the first doped part 41 and the second doped part 42, also undertake the transmission function of the current collected by the fifth sub-grid 431 and / or the sixth sub-grid 441, and setting the width of the third sub-grid 411 and the fourth sub-grid 421 wider can reduce the loss in the transmission process, thereby ensuring the reliability of collection and convergence.

[0097] See also Figure 7 In some embodiments, a third main gate 70 may also be disposed on the third doped portion 43 , the third main gate 70 continuously extends along the first direction and is electrically connected to the fifth sub-gate 431 , and the third main gate 70 is not electrically connected to the second sub-gate 31 .

[0098] In such an embodiment, the third main grid 70 can be used to be welded with a welding strip to achieve busbar output, and the third main grid 70 can be covered on the fifth sub-grid 431 to form a whole with the fifth sub-grid 431 .

[0099] In some embodiments, the width of the fifth sub-gate 431 in the second direction may be greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0100] In this way, it is not necessary to set a main grid on the fifth sub-grid 431, but a pad can be directly set on the fifth sub-grid 431 to be welded with the welding strip. If the fifth sub-grid 431 is set wider, the welding area between the welding strip and the fifth sub-grid 431 can be increased, thereby improving the reliability and stability of welding. That is to say, in the embodiment of the present application, the third main grid 70 may not be set on the third doping part 43.

[0101] In some embodiments, the width of a portion of the fifth sub-grid 431 (eg, the position welded to the welding ribbon) in the second direction may be greater than the width of the first sub-grid 21 and the second sub-grid 31 in the first direction.

[0102] That is, in the embodiment of the present application, the width of at least a portion of the fifth sub-gate 431 in the second direction may be greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0103] Please continue reading Figure 7In some embodiments, a fourth main gate 80 may also be disposed on the fourth doped portion 44 , the fourth main gate 80 continuously extends along the first direction and is electrically connected to the sixth sub-gate 441 , and the fourth main gate 80 is not electrically connected to the second sub-gate 31 .

[0104] In such an embodiment, the fourth main grid 80 can be used to be welded with a welding strip to achieve busbar output, and the fourth main grid 80 can be covered on the sixth sub-grid 441 to form a whole with the sixth sub-grid 441 .

[0105] In some embodiments, the width of the sixth sub-gate 441 in the second direction may be greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0106] In this way, it is not necessary to set a main grid on the sixth sub-grid 441, but a pad can be directly set on the sixth sub-grid 441 to be welded with the welding strip. If the sixth sub-grid 441 is set wider, the welding area between the welding strip and the sixth sub-grid 441 can be increased, thereby improving the reliability and stability of welding. That is to say, in the embodiment of the present application, the fourth main grid 80 may not be set on the fourth doping part 44.

[0107] In some embodiments, the width of a portion of the sixth sub-grid 441 (eg, the position welded to the welding strip) in the second direction may be greater than the width of the first sub-grid 21 and the second sub-grid 31 in the first direction.

[0108] That is, in the embodiment of the present application, the width of at least a portion of the sixth sub-gate 441 in the second direction may be greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0109] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0110] In addition, the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An IBC solar cell, characterized in that: include: A silicon wafer, the silicon wafer having a back side and a front side opposite to each other, the back side having a first edge and a second edge opposite to each other along a first direction, and having a third edge and a fourth edge opposite to each other along a second direction, wherein the second direction intersects the first direction; the back side comprising a middle area and an edge area surrounding the middle area; A plurality of first emitter doping layers and a plurality of base doping layers, wherein the plurality of first emitter doping layers and the plurality of base doping layers are arranged alternately in sequence along the first direction on the middle region, wherein the first emitter doping layers and the base doping layers extend continuously along the second direction, and the doping types of the first emitter doping layers and the base doping layers are opposite; and a second emitter doping layer, wherein the second emitter doping layer is disposed on the edge region, the doping type of the second emitter doping layer is opposite to the doping type of the silicon wafer, and the second emitter doping layer has the same doping type as the first emitter doping layer; Among them, the second emitter doping layer includes a first doping portion, a second doping portion, a third doping portion and a fourth doping portion, the first doping portion is arranged at the first edge and extends continuously along the second direction, the second doping portion is arranged at the second edge and extends continuously along the second direction, the third doping portion is arranged at the third edge and extends continuously along the first direction, the fourth doping portion is arranged at the fourth edge and extends continuously along the first direction, and the first doping portion, the second doping portion, the third doping portion and the fourth doping portion are all insulated and isolated from the base doping layer.

2. The IBC solar cell sheet according to claim 1, characterized in that: When the doping type of the silicon wafer is p-type doping, the doping type of the first emitter doping layer is n-type doping, the doping type of the base doping layer is p-type doping, and the doping type of the second emitter doping layer is n-type doping; When the doping type of the silicon wafer is n-type doping, the doping type of the first emitter doping layer is p-type doping, the doping type of the base doping layer is n-type doping, and the doping type of the second emitter doping layer is p-type doping.

3. The IBC solar cell according to claim 1, characterized in that: Two ends of the third doping portion are respectively connected to the first doping portion and the second doping portion; and / or Two ends of the fourth doping portion are connected to the first doping portion and the second doping portion respectively.

4. The IBC solar cell sheet according to claim 1, characterized in that: The third doped portion is connected to a plurality of the first emitter doped layers; and / or The fourth doped portion is connected to a plurality of the first emitter doped layers.

5. The IBC solar cell according to any one of claims 1 to 4, characterized in that: A first auxiliary gate is disposed on the first emitter doping layer, and a second auxiliary gate is disposed on the base doping layer, and both the first auxiliary gate and the second auxiliary gate extend along the second direction; A third sub-grid is disposed on the first doped portion, a fourth sub-grid is disposed on the second doped portion, and the third sub-grid and the fourth sub-grid extend continuously along the second direction; A fifth sub-gate is disposed on the third doped portion, a sixth sub-gate is disposed on the fourth doped portion, the fifth sub-gate and the sixth sub-gate extend continuously along the first direction, and the fifth sub-gate and the sixth sub-gate are both insulated and isolated from the second sub-gate.

6. The IBC solar cell sheet according to claim 5, characterized in that: The IBC solar cell sheet further includes a plurality of first main grids and a plurality of second main grids, which are alternately arranged in sequence along the second direction and extend along the first direction, the first main grid is electrically connected to the first sub-grid, the third sub-grid and the fourth sub-grid and is insulated and isolated from the second sub-grid, and the second main grid is electrically connected to the second sub-grid and is insulated and isolated from the first sub-grid, the third sub-grid and the fourth sub-grid.

7. The IBC solar cell sheet according to claim 6, characterized in that: The second main gate does not extend above the first doped portion and the second doped portion; or The second main gate extends to above the first doped portion and the second doped portion and intersects the third sub-gate and the fourth sub-gate. An insulating layer is provided at the position where the third sub-gate and the fourth sub-gate intersect the second main gate, and the second main gate is located above the insulating layer.

8. The IBC solar cell sheet according to claim 5, characterized in that: The fifth sub-grid is electrically connected to the third sub-grid and the fourth sub-grid; and / or The sixth sub-grid is electrically connected to the third sub-grid and the fourth sub-grid.

9. The IBC solar cell sheet according to claim 8, characterized in that: The widths of the third sub-grid and the fourth sub-grid in the first direction are greater than the widths of the first sub-grid and the second sub-grid in the first direction.

10. The IBC solar cell sheet according to claim 6, characterized in that: A third main grid is further disposed on the third doped portion, the third main grid continuously extends along the first direction and is electrically connected to the fifth sub-grid, and the third main grid is not electrically connected to the second sub-grid; and / or The width of at least a portion of the fifth sub-gate in the second direction is greater than the widths of the first sub-gate and the second sub-gate in the first direction.

11. The IBC solar cell sheet according to claim 6, characterized in that: A fourth main grid is further disposed on the fourth doped portion, the fourth main grid continuously extends along the first direction and is electrically connected to the sixth sub-grid, and the fourth main grid is not electrically connected to the second sub-grid; and / or The width of at least a portion of the sixth sub-gate in the second direction is greater than the widths of the first sub-gate and the second sub-gate in the first direction.

12. A battery assembly, characterized in that: The invention comprises the IBC solar cell sheets as described in any one of claims 1 to 11.

13. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 12.

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