Signal generator

Abstract

The utility model provides a signal generator, and relates to the technical field of emergency communication. The input end of a signal conversion module in the signal generator is connected with the output end of a signal processing module; the signal processing module comprises an FPGA and a direct digital synthesizer, the output end of the FPGA is connected with the input end of the direct digital synthesizer, and the FPGA is used for controlling the direct digital synthesizer to output multiple paths of differential signals; the signal conversion module comprises a plurality of baluns and filter circuits, the number of the baluns is the same as that of the filter circuits, the input end of each balun is connected with the input end of the direct digital synthesizer, the output end of each balun is correspondingly connected with one filter circuit, and the number of the baluns is the same as that of differential signals output by the direct digital synthesizer. The signal generator provided by the embodiment of the utility model can generate a plurality of signals, effectively meets the emergency rescue requirements, facilitates voice communication or file transmission between the emergency broadcast equipment and a plurality of radio stations and broadcasting of a plurality of programs, and achieves the expansion of the coverage range of emergency broadcast information.

Description

Technical Field

[0001] The present application relates to the field of emergency communication technology, and in particular, to a signal generator. Background Art

[0002] Emergency broadcasting refers to when a major natural disaster, emergency event, public health, social security or other public crisis occurs, emergency broadcasting can provide a fast and convenient information transmission channel, so as to deliver disaster news or the possible harm caused by the disaster to the public as soon as possible, so that the people can know what happened and how to evacuate and avoid danger at the first time, so as to minimize the loss of life and property.

[0003] In the prior art, emergency broadcasting equipment often uses a signal generator to generate a single signal for broadcasting. However, in emergency rescue work in large-scale areas, in order to improve rescue efficiency, it is necessary to conduct voice communication or file transfer to different radio stations or broadcast multiple programs simultaneously. That is, the emergency broadcasting equipment needs to send multiple signals. Existing signal generators are difficult to meet rescue needs. Utility Model Content

[0004] The embodiment of the present application provides a signal generator, which can solve the problem that the signal generator can only generate a single signal and is difficult to meet the rescue needs. In order to achieve this purpose, the embodiment of the present application provides the following solutions.

[0005] According to one aspect of an embodiment of the present application, a signal generator is provided. The signal generator is used for emergency broadcasting equipment, and includes a signal processing module and a signal conversion module. The input end of the signal conversion module is connected to the output end of the signal processing module.

[0006] The signal processing module includes an FPGA and a direct digital synthesizer, wherein the output end of the FPGA is connected to the input end of the direct digital synthesizer, and is used to control the direct digital synthesizer to output multiple differential signals;

[0007] The signal conversion module includes multiple baluns and filtering circuits, the number of the baluns is the same as the number of the filtering circuits, the input end of the balun is connected to the input end of the direct digital synthesizer, and the output end of each balun is correspondingly connected to a filtering circuit. The number of the baluns is the same as the number of differential signals output by the direct digital synthesizer, and the frequency of the differential signal received by each balun is the same or different.

[0008] In a possible implementation, the signal generator further includes a signal generating module, the signal generating module includes an audio encoder, and the audio encoder is connected to the FPGA and is used to collect audio data and transmit a digital signal corresponding to the audio data to the FPGA.

[0009] In a possible implementation, the signal generator further includes a storage circuit, and the storage circuit is connected to the FPGA to store working status information of the FPGA.

[0010] In a possible implementation, the signal generator also includes a power supply module, which includes a first power supply circuit, a second power supply circuit, and a third power supply circuit for supplying power to the signal generating module, the signal processing module, and the signal generating module, and the output voltages of the first power supply circuit, the second power supply circuit, and the third power supply circuit decrease sequentially.

[0011] In a possible implementation, the power supply module further includes a protection circuit, an input end of the protection circuit is connected to a power supply, and an output end is respectively connected to input ends of the first power supply circuit, the second power supply circuit, and the third power supply circuit.

[0012] In one possible implementation, the rotating structure includes a rotating shaft and a locking knob cooperating with the rotating shaft, the coil fixing structure is rotationally fixed to the rotating shaft, and one end of the locking knob protrudes from the rotating structure to stop the rotation of the coil fixing structure.

[0013] In a possible implementation, the power supply module further includes a voltage stabilizing circuit, an input end of the voltage stabilizing circuit is connected to an output end of the first power supply circuit, and an output voltage of the voltage stabilizing circuit is the same as an output voltage of the second power supply circuit;

[0014] The voltage stabilizing circuit includes a one-hundred-and-forty-second capacitor, a one-hundred-and-forty-third capacitor, a voltage stabilizer, a one-hundred-and-forty-fourth capacitor, a one-hundred-and-forty-fifth capacitor, and a fourth ferrite bead. The first ends of the one-hundred-and-forty-second capacitor and the one-hundred-and-forty-third capacitor are connected to the output end of the first power supply circuit and the input end of the voltage stabilizer, the second ends of the one-hundred-and-forty-second capacitor and the one-hundred-and-forty-third capacitor are grounded, the output end of the voltage stabilizer is connected to the first ends of the one-hundred-and-forty-fourth capacitor, the one-hundred-and-forty-fifth capacitor, and the fourth ferrite bead, the second ends of the one-hundred-and-forty-fourth capacitor and the one-hundred-and-forty-fifth capacitor are grounded, and the second end of the fourth ferrite bead outputs a voltage signal.

[0015] In one possible implementation, the filtering circuit includes a first low-pass filtering circuit, a second low-pass filtering circuit, a third low-pass filtering capacitor and a fourth low-pass filtering circuit with the same circuit structure, and the baluns connected to the first low-pass filtering circuit, the second low-pass filtering circuit, the third low-pass filtering capacitor and the fourth low-pass filtering circuit are different.

[0016] In a possible implementation, the signal generator also includes a signal detection circuit and a level converter, one end of the signal detection circuit is connected to the output end of the filter circuit, and the other end is connected to the signal detection end of the direct digital synthesizer, the detection end of the signal detection circuit is connected to the output end of the filter circuit, the signal output end of the level converter is connected to the signal detection end of the direct digital synthesizer, and the signal receiving end of the level converter is connected to the output end of the signal detection circuit.

[0017] In a possible implementation, the level converter includes a first level converter, the signal detection circuit includes a one-hundred-fifty-sixth capacitor, a one-hundred-fifty-eighth capacitor, a tenth diode, a fifty-eighth resistor, and a level converter, the signal output end of the first level converter is connected to the direct digital synthesizer, the signal receiving end of the first level converter is connected to the first end of the fifty-eighth resistor, the second end of the fifty-eighth resistor is connected to the cathode of the tenth diode, the anode of the tenth diode is connected to the first end of the one-hundred-fifty-eighth capacitor and the first end of the one-hundred-fifty-sixth capacitor, the second end of the one-hundred-fifty-eighth capacitor is grounded, and the second end of the one-hundred-fifty-sixth capacitor is connected to the output end of the first low-pass filter circuit.

[0018] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0019] The input end of the signal conversion module in the signal generator provided by the present application is connected to the output end of the signal processing module; the signal processing module includes an FPGA and a direct digital synthesizer, and the output end of the FPGA is connected to the input end of the direct digital synthesizer, which is used to control the direct digital synthesizer to output multiple differential signals; the signal conversion module includes multiple baluns and filtering circuits, the number of baluns is the same as the number of filtering circuits, the input end of the balun is connected to the input end of the direct digital synthesizer, and the output end of each balun is correspondingly connected to a filtering circuit, the number of baluns is the same as the number of differential signals output by the direct digital synthesizer, and the frequency of the differential signal received by each balun is the same or different. The signal generator of the embodiment of the present application can generate multiple signals, effectively meet the needs of emergency rescue, facilitate emergency broadcasting equipment to conduct voice communication or file transmission with multiple radio stations and broadcast multiple sets of programs, and realize the expansion of the coverage of emergency broadcasting information. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in describing the embodiments of the present application.

[0021] Figure 1 A structural diagram of a signal generator provided in an embodiment of the present application;

[0022] Figure 2 A partial circuit diagram of a direct digital synthesizer provided in an embodiment of the present application;

[0023] Figure 3 A circuit diagram of a balun provided in an embodiment of the present application;

[0024] Figure 4 A circuit diagram of a first low-pass filter circuit and a portion of a detection circuit connected thereto provided in an embodiment of the present application;

[0025] Figure 5 A circuit diagram of a second low-pass filter circuit and a portion of a detection circuit connected thereto provided in an embodiment of the present application;

[0026] Figure 6 A circuit diagram of a third low-pass filter circuit and a portion of a detection circuit connected thereto provided in an embodiment of the present application;

[0027] Figure 7 A circuit diagram of a fourth low-pass filter circuit and a portion of a detection circuit connected thereto provided in an embodiment of the present application;

[0028] Figure 8 A circuit diagram of a level converter provided in an embodiment of the present application;

[0029] Fig. 9 A partial circuit diagram of an audio encoder provided in an embodiment of the present application;

[0030] Fig.10 A circuit diagram of a first power supply circuit provided in an embodiment of the present application;

[0031] Fig.11 A circuit diagram of a second power supply circuit provided in an embodiment of the present application;

[0032] Fig.12 A circuit diagram of a third power supply circuit provided in an embodiment of the present application;

[0033] Fig.13 A circuit diagram of a protection circuit provided in an embodiment of the present application;

[0034] Fig.14 A circuit diagram of a voltage stabilizing circuit provided in an embodiment of the present application;

[0035] Fig.15 A circuit diagram of a storage circuit provided in an embodiment of the present application.

[0036] Explanation of reference numerals: N6, audio encoder chip; R15, 15th resistor; R12, 12th resistor; R19, 19th resistor; C66, 66th capacitor; C72, 72nd capacitor; R25, 25th resistor; R14, 14th resistor; R17, 17th resistor; C74, 74th capacitor; C75, 75th capacitor; R23, 23rd resistor; C67, 67th capacitor; C77, 77th capacitor; R21, 21st resistor; R14, 14th resistor; D7, first switching regulator; L15, 15th inductor; R49, 49th resistor; R52, 52nd resistor; C153, 153rd capacitor; C154, 154th capacitor; B6, sixth ferrite bead ; V9, the ninth light-emitting diode; R51, the fifty-first resistor; F1, the fuse; V6, the sixth light-emitting diode; C136, the one-hundred-thirty-sixth capacitor; C137, the one-hundred-thirty-seventh capacitor; C138, the one-hundred-thirty-eighth capacitor; C142, the one-hundred-forty-second capacitor; C143, the one-hundred-forty-third capacitor; D5, the voltage regulator; C144, the one-hundred-forty-fourth capacitor; C145, the one-hundred-forty-fifth capacitor; B4, the fourth ferrite bead; R1, the first resistor; C17, the seventeenth capacitor; C28, the twenty-eighth capacitor; D8, the first level converter; D9, the second level converter; C156, the one-hundred-fifty-sixth capacitor; C158, the one-hundred-fifty-eighth capacitor; V10, the tenth diode; R58, the fifty-eighth resistor. DETAILED DESCRIPTION

[0037] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0038] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" indicates that it is implemented as "A", or is implemented as "A", or is implemented as "A and B".

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0040] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0041] The signal generator and magnetic resonance device provided in the present application are intended to solve at least one technical problem existing in the prior art.

[0042] In an embodiment of the present application, a signal generator is provided, such as Figure 1-Figure 15As shown, the signal generator is used for emergency broadcasting equipment, and the emergency broadcasting equipment uses the signal generator to perform emergency communication or, when the emergency broadcasting equipment is an emergency broadcasting station, to modulate and generate internal signals. The signal generator includes a signal processing module and a signal conversion module, and the input end of the signal conversion module is connected to the output end of the signal processing module; the signal processing module includes an FPGA and a direct digital synthesizer, and the output end of the FPGA is connected to the input end of the direct digital synthesizer, and is used to control the direct digital synthesizer to output multiple differential signals; the signal conversion module includes a plurality of baluns and filtering circuits, and the number of baluns is the same as the number of filtering circuits, and the input end of the balun is connected to the input end of the direct digital synthesizer (DDS), and the output end of each balun is connected to a corresponding filtering circuit, and the number of baluns is the same as the number of differential signals output by the direct digital synthesizer, and the frequency of the differential signal received by each balun is the same or different.

[0043] In one embodiment, a portion of the direct digital synthesizer circuit is as follows Figure 2 As shown, Barron Figure 3 As shown, the number of baluns is 4, and the direct digital synthesizer outputs one to four differential signals. Each channel can be controlled separately, and any one of the four channels can be controlled to output a single-frequency signal, any two channels can output a dual-frequency signal, any three channels can output a triple-frequency signal, and the four channels can output a quad-frequency signal at the same time, and the frequency of each signal can be the same or different. The operating frequency range of the output signal is 1.6MHz-60MHz. The output signal power is -49.3dBm to -7dBm. The output signal type of the signal generator is divided into analog signals and digital signals. When the output signal is an analog signal, the analog signal can be a high-frequency single-carrier signal, which is a standard sine wave signal that has not been modulated, and the signal generator can perform amplitude modulation and frequency modulation on the analog signal. Among them, in amplitude modulation, the amplitude of the baseband signal is linearly modulated onto a high-frequency carrier, and the amplitude modulation includes any one of amplitude modulation, single-sideband amplitude modulation, and double-sideband amplitude modulation. Frequency modulation is to modulate the frequency of the carrier according to the frequency change of the baseband signal. The signal generator of the present application modulates the frequency of the carrier by the frequency change of white noise to form white noise narrowband frequency modulation. When outputting a digital signal, the signal generator generates a digital signal by coding modulation. The coding modulation transmits data by encoding digital information into modulation symbols, and generates a frequency shift keying signal and a phase shift keying signal by coding modulation.

[0044] In one embodiment, the DDS may adopt AD9959 of ADI Company, which generates multiple signals after receiving the instruction transmitted by FPGA, and the signal includes at least one of single carrier, analog modulation signal and digital modulation signal.

[0045] Optionally, the signal generator further includes a signal generating module, the signal generating module includes an audio encoder, the audio encoder is connected to the FPGA, and is used for collecting audio data and transmitting a digital signal corresponding to the audio data to the FPGA.

[0046] Optionally, the audio encoder may further include a signal acquisition circuit and an audio encoder chip N6, such as Fig. 9 As shown, the output end of the signal acquisition circuit is connected to the audio encoder chip N6, and the audio encoder chip N6 obtains the audio signal through the signal acquisition circuit. Wherein, the signal acquisition circuit includes a fifteenth resistor R15, a twelfth resistor R12, a nineteenth resistor R19, a sixty-sixth capacitor C66, a seventy-second capacitor C72, a twenty-fifth resistor R25, a fourteenth resistor R14R14, a seventeenth resistor R17, a seventy-fourth capacitor C74, a seventy-fifth capacitor C75, a twenty-third resistor R23, a sixty-seventh capacitor C67, a seventy-seventh capacitor C77, a twenty-first resistor R21, and a fourteenth resistor R14R14. The first end of the fifteenth resistor R15 is connected to the first input end of the signal acquisition circuit and the first end of the twelfth resistor R12, and the second end of the fifteenth resistor R15 is connected to the second input end of the signal acquisition circuit and the first end of the nineteenth resistor R19. The second end of the twelfth resistor R12 is connected to the first end of the sixty-sixth capacitor C66, and the second end of the nineteenth resistor R19 is connected to the first end of the seventy-second capacitor C72. The second end of the seventy-second capacitor C72 is grounded, the second end of the sixty-sixth capacitor C66 is connected to the first end of the twenty-fifth resistor R25, the second end of the twenty-fifth capacitor is connected to the first end of the seventy-seventh capacitor C77, the second end of the seventy-fifth capacitor C75, and the second end of the twenty-third resistor R23, the first end of the seventy-fifth capacitor C75 is connected to the second end of the twenty-first resistor R21, the first end of the twenty-third resistor R23, the first end of the seventy-fourth capacitor C74, and the first end of the seventeenth resistor R17, and the first end of the twenty-first resistor R21 is grounded. The second end of the seventeenth resistor R17 is connected to the second end of the seventy-fourth capacitor C74, the first end of the sixty-seventh capacitor C67, the second end of the fourteenth resistor R14R14, and the first end of the sixty-seventh capacitor C67, the first end of the fourteenth resistor R14R14 is connected to the second end of the sixty-sixth capacitor C66, and the second end of the sixty-seventh capacitor C67 and the second end of the seventy-seventh capacitor are both connected to the audio encoder chip N6.

[0047] In one embodiment, the model of the audio encoder chip N6 may be TLV320AIC23B, through which A / D acquisition of audio data is performed, and the audio encoder sends the digital audio signal to the FPGA for processing through the I2S communication interface and the ADC interface.

[0048] Optionally, the FPGA includes an internal power supply circuit, a JTAG download circuit, a communication circuit, and a communication control circuit, wherein the internal power supply circuit provides three DC voltages of 3.3VDC, 1.8DC, and 1.0VDC to the devices in the FPGA, and the JTAG download circuit provides a hardware interface for program downloading of the FPGA. The communication circuit provides an interface for communication between the FPGA and the FPGA and external devices (such as the FPGA). Among them, the communication circuit includes a variety of interfaces, which may include an SPI interface for communication with FLASH, an I2S and ADC interface for communication with an audio encoder, an RS232 interface for serial communication, and an SDIO interface for communication with DDS. The FPGA is connected to the DDS, and transmits instructions to the DDS to control the DDS to output analog signals, digital signals, and perform signal filtering, sampling, compensation, frequency conversion, timing coordination, logic processing, and other processing operations. And the FPGA can also perform A / D acquisition on the audio data input by the audio encoder to achieve amplitude modulation.

[0049] Optionally, the FPGA includes an external SPI interface module and a UART communication module, wherein the external SPI interface module includes a first SPI interface, a second SPI interface, and a third SPI interface, wherein the audio ADC control and sampling are realized through the first SPI interface, the DDS chip configuration is performed using the second SPI interface, and the DAC control is performed through the third SPI interface. The UART communication module is used to complete the communication with the host computer and realize the transmission of communication commands. In addition, the FPGA also includes a DDS configuration module, which is connected to the second SPI interface and is used to complete the configuration of DDS register parameters in different modes.

[0050] In one embodiment, the FPGA model is XC7A50T-2CSG324 of the Xilinx7 series, which realizes the highest performance device through stacked silicon interconnect technology. The internal power supply circuit, JTAG download circuit, communication circuit and communication control circuit are integrated in the FPGA.

[0051] Optionally, the signal generator further includes a storage circuit, and the storage circuit is connected to the FPGA to store the working state information of the FPGA.

[0052] In one embodiment, Fig.15 As shown, the storage circuit includes a storage chip, the model of the storage chip may be S25FL256SAGNF100, and its operating voltage is 3.3V.

[0053] Optionally, the signal generator also includes a power supply module, which includes a first power supply circuit, a second power supply circuit and a third power supply circuit for supplying power to the signal generating module, the signal processing module and the signal generating module, and the output voltages of the first power supply circuit, the second power supply circuit and the third power supply circuit decrease sequentially.

[0054] In one embodiment, Figure 10-12 As shown, the first power supply circuit, the second power supply circuit and the third power supply circuit output three voltages of +3.3VDC, +1.8VDC and +1.0VDC in sequence, and the first power supply circuit, the second power supply circuit and the third power supply circuit are all provided with a switching regulator, and the model of the switching regulator can be TLV62130RGTT. Among them, the first power supply circuit is provided with a first switching regulator D7, and the model of the first switching regulator D7 can be TLV62130RGTT. The input end of the first power supply circuit inputs a 5V DC voltage, which is transmitted to the first switching regulator D7. The first power supply circuit also includes a fifteenth inductor L15, a forty-ninth resistor R49, a fifty-second resistor R52, a one-hundred-and-fifty-third capacitor C153, a one-hundred-and-fifty-fourth capacitor C154, a sixth ferrite bead B6, a ninth light-emitting diode V9, and a fifty-first resistor R51. The first end of the fifteenth inductor L15 is connected to the SW pin of the first switching regulator D7, the second end of the fifteenth inductor L15 is connected to the VOS pin and the PG pin of the switching regulator, the first end of the forty-ninth resistor R49, the first end of the one-hundred-and-fifty-third capacitor C153, the first end of the one-hundred-and-fifty-fourth capacitor C154, and the first end of the sixth ferrite bead B6, the second end of the forty-ninth resistor R49 is connected to the first end of the fifty-second resistor R52, and the FB pin of the first switching regulator D7. The second end of the one-hundred-and-fifty-third capacitor C153 and the second end of the one-hundred-and-fifty-fourth capacitor C154 are grounded. The second end of the sixth ferrite bead B6 is connected to the anode of the ninth light emitting diode V9. The cathode of the ninth light emitting diode V9 is connected to the first end of the fifty-first resistor R51, and the second end of the fifty-first resistor R51 is grounded.

[0055] Optionally, the power supply module also includes a protection circuit, the input end of the protection circuit is connected to the power supply, and the output end is respectively connected to the input ends of the first power supply circuit, the second power supply circuit and the third power supply circuit, and the first power supply circuit, the second power supply circuit and the third power supply circuit convert the voltage transmitted by the protection circuit into a DC voltage of corresponding magnitude and output it to the corresponding circuit or device.

[0056] Alternatively, if Fig.13As shown, the protection circuit includes a fuse F1, a sixth light emitting diode V6, a 136th capacitor C136, a 137th capacitor C137 and a 138th capacitor C138, a first end of the fuse F1 is connected to the positive electrode of the output end of the power supply, a second end is connected to the anode of the sixth light emitting diode V6, the 136th capacitor C136, the 137th capacitor C137 and the first end of the 138th capacitor C138, a cathode of the sixth light emitting diode V6 is grounded, and a second end of the 136th capacitor C136, the 137th capacitor C137 and the 138th capacitor C138 is grounded. The sixth light emitting diode V6 indicates the on and off of the protection circuit.

[0057] Optionally, in order to maintain the stability of the input voltage, the power supply module also includes a voltage stabilization circuit, such as Fig.14 As shown, the input end of the voltage stabilizing circuit is connected to the output end of the first power supply circuit, and the output voltage of the voltage stabilizing circuit is the same as the output voltage of the second power supply circuit; the voltage stabilizing circuit includes a one-hundred-and-forty-second capacitor C142, a one-hundred-and-forty-third capacitor C143, a voltage stabilizer D5, a one-hundred-and-forty-fourth capacitor C144, a one-hundred-and-forty-fifth capacitor C145, and a fourth ferrite bead B4, the first ends of the one-hundred-and-forty-second capacitor C142 and the one-hundred-and-forty-third capacitor C143 are connected to the output end of the first power supply circuit and the input end of the voltage stabilizer D5, the second ends of the one-hundred-and-forty-second capacitor C142 and the one-hundred-and-forty-third capacitor C143 are grounded, the output end of the voltage stabilizer D5 is connected to the first ends of the one-hundred-and-forty-fourth capacitor C144, the one-hundred-and-forty-fifth capacitor C145, and the fourth ferrite bead B4, the second ends of the one-hundred-and-forty-fourth capacitor C144 and the one-hundred-and-forty-fifth capacitor C145 are grounded, and the second end of the fourth ferrite bead B4 outputs a voltage signal.

[0058] Optionally, the filtering circuit includes a first low-pass filtering circuit, a second low-pass filtering circuit, a third low-pass filtering capacitor and a fourth low-pass filtering circuit with the same circuit structure, and the first low-pass filtering circuit, the second low-pass filtering circuit, the third low-pass filtering capacitor and the fourth low-pass filtering circuit are connected to different baluns.

[0059] In one embodiment, the balun model may be ADTT1-1, such as Figure 4 As shown, the first low-pass filter circuit includes a first resistor R1, a seventeenth capacitor C17, and a twenty-eighth capacitor C28. The first end of the first resistor R1 is connected to the balun, the second end of the seventeenth capacitor C17 is grounded, the first end of the seventieth capacitor is connected to the first end of the twenty-eighth capacitor C28 and the output end of the signal generator, and the second end of the twenty-eighth capacitor C28 is grounded.

[0060] Optionally, the signal generator also includes a signal detection circuit and a level converter, one end of the signal detection circuit is connected to the output end of the filter circuit, and the other end is connected to the signal detection end of the direct digital synthesizer, the detection end of the signal detection circuit is connected to the output end of the filter circuit, the signal output end of the level converter is connected to the signal detection end of the direct digital synthesizer, and the signal receiving end of the level converter is connected to the output end of the signal detection circuit.

[0061] Alternatively, if Figure 4-Figure 8 As shown, the level converter includes a first level converter D8, the signal detection circuit includes a one-hundred-and-fifty-sixth capacitor C156, a one-hundred-and-fifty-eighth capacitor, a tenth diode V10, and a fifty-eighth resistor R58, the signal output end of the first level converter D8 is connected to the direct digital synthesizer, the signal receiving end is connected to the first end of the fifty-eighth resistor R58, the second end of the fifty-eighth resistor R58 is connected to the cathode of the tenth diode V10, the anode of the tenth diode V10 is connected to the first end of the one-hundred-and-fifty-eighth capacitor and the first end of the one-hundred-and-fifty-sixth capacitor C156, the second end of the one-hundred-and-fifty-eighth capacitor is grounded, and the second end of the one-hundred-and-fifty-sixth capacitor C156 is connected to the output end of the first low-pass filter circuit.

[0062] In one embodiment, the signal detection circuit includes a first level converter D8 and a second level converter D9. The first level converter D8 is connected to the first low-pass filter circuit and the second low-pass filter circuit through the signal detection circuit. The second level converter D9 is connected to the third low-pass filter circuit and the fourth low-pass filter circuit through the signal detection circuit.

[0063] The input end of the signal conversion module in the signal generator of the present application is connected to the output end of the signal processing module; the signal processing module includes an FPGA and a direct digital synthesizer, the output end of the FPGA is connected to the input end of the direct digital synthesizer, and is used to control the direct digital synthesizer to output multiple differential signals; the signal conversion module includes multiple baluns and filtering circuits, the number of baluns is the same as the number of filtering circuits, the input end of the balun is connected to the input end of the direct digital synthesizer, the output end of each balun is correspondingly connected to a filtering circuit, the number of baluns is the same as the number of differential signals output by the direct digital synthesizer, and the frequency of the differential signal received by each balun is the same or different. The signal generator of the embodiment of the present application can generate multiple signals, effectively meet the needs of emergency rescue, facilitate emergency broadcasting equipment to conduct voice communication or file transmission with multiple radio stations and broadcast multiple sets of programs, and realize the expansion of the coverage of emergency broadcasting information.

[0064] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in the drawings.

[0065] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0066] The above is only an optional implementation method for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A signal generator, characterized in that: Used in emergency broadcasting equipment, comprising a signal processing module and a signal conversion module, wherein the input end of the signal conversion module is connected to the output end of the signal processing module; The signal processing module includes an FPGA and a direct digital synthesizer, wherein the output end of the FPGA is connected to the input end of the direct digital synthesizer, and is used to control the direct digital synthesizer to output multiple differential signals; The signal conversion module includes multiple baluns and filtering circuits, the number of the baluns is the same as the number of the filtering circuits, the input end of the balun is connected to the input end of the direct digital synthesizer, and the output end of each balun is correspondingly connected to a filtering circuit. The number of the baluns is the same as the number of differential signals output by the direct digital synthesizer, and the frequency of the differential signal received by each balun is the same or different.

2. The signal generator according to claim 1, characterized in that: The signal generator further includes a signal generating module, which includes an audio encoder. The audio encoder is connected to the FPGA and is used to collect audio data and transmit a digital signal corresponding to the audio data to the FPGA.

3. The signal generator according to claim 1, characterized in that: The signal generator further includes a storage circuit, which is connected to the FPGA to store the working status information of the FPGA.

4. The signal generator according to claim 2, characterized in that: The signal generator also includes a power supply module, which includes a first power supply circuit, a second power supply circuit and a third power supply circuit for supplying power to the signal generating module, the signal processing module and the signal generating module, and the output voltages of the first power supply circuit, the second power supply circuit and the third power supply circuit decrease sequentially.

5. The signal generator according to claim 4, characterized in that: The power supply module also includes a protection circuit, the input end of the protection circuit is connected to the power supply, and the output end is respectively connected to the input ends of the first power supply circuit, the second power supply circuit and the third power supply circuit.

6. The signal generator according to claim 5, characterized in that: The protection circuit includes a fuse, a sixth light-emitting diode, a one-hundred-thirty-sixth capacitor, a one-hundred-thirty-seventh capacitor and a one-hundred-thirty-eighth capacitor. The first end of the fuse is connected to the positive electrode of the output end of the power supply, and the second end is connected to the anode of the sixth light-emitting diode, the one-hundred-thirty-sixth capacitor, the one-hundred-thirty-seventh capacitor and the first end of the one-hundred-thirty-eighth capacitor. The cathode of the sixth light-emitting diode is grounded, and the second ends of the one-hundred-thirty-sixth capacitor, the one-hundred-thirty-seventh capacitor and the one-hundred-thirty-eighth capacitor are grounded.

7. The signal generator according to claim 4, characterized in that: The power supply module further includes a voltage stabilizing circuit, an input end of the voltage stabilizing circuit is connected to an output end of the first power supply circuit, and an output voltage of the voltage stabilizing circuit is the same as an output voltage of the second power supply circuit; The voltage stabilizing circuit includes a one-hundred-and-forty-second capacitor, a one-hundred-and-forty-third capacitor, a voltage stabilizer, a one-hundred-and-forty-fourth capacitor, a one-hundred-and-forty-fifth capacitor, and a fourth ferrite bead. The first ends of the one-hundred-and-forty-second capacitor and the one-hundred-and-forty-third capacitor are connected to the output end of the first power supply circuit and the input end of the voltage stabilizer, the second ends of the one-hundred-and-forty-second capacitor and the one-hundred-and-forty-third capacitor are grounded, the output end of the voltage stabilizer is connected to the first ends of the one-hundred-and-forty-fourth capacitor, the one-hundred-and-forty-fifth capacitor, and the fourth ferrite bead, the second ends of the one-hundred-and-forty-fourth capacitor and the one-hundred-and-forty-fifth capacitor are grounded, and the second end of the fourth ferrite bead outputs a voltage signal.

8. The signal generator according to claim 1, characterized in that: The filter circuit includes a first low-pass filter circuit, a second low-pass filter circuit, a third low-pass filter capacitor and a fourth low-pass filter circuit with the same circuit structure, and the baluns connected to the first low-pass filter circuit, the second low-pass filter circuit, the third low-pass filter capacitor and the fourth low-pass filter circuit are different.

9. The signal generator according to claim 8, characterized in that: The signal generator also includes a signal detection circuit and a level converter. One end of the signal detection circuit is connected to the output end of the filter circuit, and the other end is connected to the signal detection end of the direct digital synthesizer. The detection end of the signal detection circuit is connected to the output end of the filter circuit, the signal output end of the level converter is connected to the signal detection end of the direct digital synthesizer, and the signal receiving end of the level converter is connected to the output end of the signal detection circuit.

10. The signal generator according to claim 9, characterized in that: The level converter includes a first level converter, and the signal detection circuit includes a one-hundred-and-fifty-sixth capacitor, a one-hundred-and-fifty-eighth capacitor, a tenth diode, a fifty-eighth resistor, and a level converter. The signal output end of the first level converter is connected to the direct digital synthesizer, the signal receiving end of the first level converter is connected to the first end of the fifty-eighth resistor, the second end of the fifty-eighth resistor is connected to the cathode of the tenth diode, the anode of the tenth diode is connected to the first end of the one-hundred-and-fifty-eighth capacitor and the first end of the one-hundred-and-fifty-sixth capacitor, the second end of the one-hundred-and-fifty-eighth capacitor is grounded, and the second end of the one-hundred-and-fifty-sixth capacitor is connected to the output end of the first low-pass filter circuit.

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