Test chip and repair system
By designing the second Josephson junction for testing on a quantum chip and using its test results to perform annealing modification of the first Josephson junction, the problem of surface metal layer failure during quantum chip resistance measurement is solved, and the chip performance is protected and improved.
Patent Information
- Application Number
- CN202420227885.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-30
- Publication Date
- 2025-04-11
- Estimated Expiration
- 2034-01-30
AI Technical Summary
The existing quantum chip annealing modification resistance process will damage the metal layer on the surface of the chip when measuring the qubit resistance, resulting in reduced low-temperature performance and loss.
Design a test chip that includes a substrate, a superconducting quantum chip and two Josephson junctions with the same structure. Among them, the second Josephson knot is used for testing, and the test results are used to modify the first Josephson knot. By performing resistance measurement of the second Josephson junction at room temperature, annealing parameters are obtained and laser annealing is performed to avoid damage to the first Josephson junction.
The detection and annealing modification are achieved without damaging the quantum chip, avoiding the reduction and loss of low-temperature performance.
Smart Images
Figure CN222750827U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of quantum bit chip technology, and in particular, relates to a test chip and repair system. Background Art
[0002] In a quantum computer of a superconducting physics system, the superconducting quantum chip is the core component of the superconducting quantum computer. The quantum bits on the superconducting quantum chip are superconducting quantum circuits built based on the Josephson structure. In order to improve the performance parameters of the quantum bits, the Josephson junction can be annealed by laser.
[0003] For the existing quantum chip annealing resistance modification process, the bit resistance needs to be measured before and after the quantum bit annealing process. The current method for achieving resistance measurement is metal probe plus source meter test, but this method will destroy the surface metal layer of the quantum chip while measuring the resistance, resulting in a certain reduction and loss in the low-temperature performance of the quantum chip. Therefore, how to complete the quantum chip detection without damaging the quantum chip and modify its resistance based on the detection results is a problem that needs to be solved at present.
[0004] It should be noted that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Utility Model Content
[0005] The purpose of the present application is to provide a test chip and repair system to solve the problem in the prior art that, in the process of annealing and modifying resistance of quantum chips, when measuring the bit resistance before and after the quantum bit annealing process, the surface of the quantum chip will be damaged, resulting in a certain reduction and loss in the low-temperature performance of the quantum chip. The system can obtain annealing process parameters for the quantum chip that needs annealing modification and perform annealing modification according to the parameters without destroying or damaging the quantum chip.
[0006] In order to solve the above technical problems, the utility model provides a test chip, comprising:
[0007] substrate;
[0008] A superconducting quantum chip manufactured on the surface of the substrate, wherein the superconducting quantum chip has a first Josephson junction;
[0009] A second Josephson junction manufactured on the substrate coplanar with the superconducting quantum chip, wherein the second Josephson junction has the same structure as the first Josephson junction;
[0010] The second Josephson junction is positioned adjacent to the edge of the superconducting quantum chip;
[0011] The second Josephson junction is used to be tested to obtain a test result, and the test result is used as a basis for modifying the first Josephson junction.
[0012] Preferably, the number of the superconducting quantum chips is two or more.
[0013] Preferably, all the superconducting quantum chips are separated from each other and arranged close to the central area of the substrate.
[0014] Preferably, the second Josephson junction is arranged close to the periphery of the substrate.
[0015] Preferably, the substrate is a sapphire substrate or a silicon substrate.
[0016] Preferably, the number of the first Josephson junctions is more than two.
[0017] Preferably, the number of the second Josephson junctions is more than two.
[0018] Preferably, all of the second Josephson junctions are arranged around the superconducting quantum chip.
[0019] The present application also provides a repair system for operating the test chip described in any one of the above items, characterized by comprising:
[0020] A conveying device, used for conveying the test chip;
[0021] A testing device disposed at one end of the transmission device, used for testing the room temperature resistance of the second Josephson junction;
[0022] The annealing device is arranged at one end of the conveying device away from the testing device, and is used to modify the room temperature resistance of the first Josephson junction.
[0023] A plurality of clamping devices matching the shape of the test chip are respectively located on the surfaces of the conveying device, the test device and the annealing device, and the test chip is fixed in the clamping devices.
[0024] Preferably, the conveying device is a conveyor belt.
[0025] Different from the commonly used measurement and modification devices, the present application adds a second Josephson junction for testing annealing process parameters next to the first Josephson junction required for the subsequent manufacture of a single superconducting quantum chip. And the first Josephson junction and the second Josephson junction are made using the same process, so the internal structure process parameters of the first Josephson junction and the second Josephson are the same. The second Josephson junction is used as a test group, and the first Josephson junction is characterized by the normal temperature resistance using the second Josephson junction (test group). Based on the obtained annealing parameters, the first Josephson is subjected to laser annealing operation, and the annealing parameters can be obtained without damaging the first Josephson junction (formal group), and the first Josephson junction is annealed according to the annealing parameters, so as to avoid the first Josephson junction from causing its low temperature performance to decline and loss due to the measurement of the annealing parameters. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 A schematic diagram of the structure of a test chip provided in an embodiment of the present application;
[0027] Figure 2 A schematic diagram of the structure of the repair system provided in an embodiment of the present application.
[0028] Explanation of the reference numerals: 1 - substrate, 11 - superconducting quantum chip, 111 - first Josephson junction, 12 - second Josephson junction, 2 - transmission device, 3 - testing device, 4 - annealing device, 5 - clamping device. DETAILED DESCRIPTION
[0029] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.
[0030] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.
[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0032] In quantum computers of superconducting physics systems, superconducting quantum chips are the core components of superconducting quantum computers. The quantum bits on the superconducting quantum chips are superconducting quantum circuits built based on the Josephson structure. In order to improve the performance parameters of the quantum bits, lasers are often used to anneal the Josephson junction.
[0033] Before the annealing operation is performed, the room temperature resistance parameters of the target Josephson junction must be obtained first. The current method for measuring the room temperature resistance is to use a metal probe plus a source meter test; specifically, the metal probe is inserted into the structural layer of the Josephson junction, and then a voltage is applied to test its resistance. However, this behavior will cause the surface layer of the Josephson junction to be damaged by the metal probe, thereby causing a certain degree of reduction and loss in the low temperature performance of the Josephson junction; therefore, how to complete the detection of the Josephson junction without damaging the Josephson junction and modify its resistance based on the detection results is a problem to be solved by this application.
[0034] The present invention provides a test chip, comprising:
[0035] Base 1;
[0036] A superconducting quantum chip 11 manufactured on the surface of the substrate 1, wherein the superconducting quantum chip 11 has a first Josephson junction 111;
[0037] A second Josephson junction 12 manufactured on the substrate 1 coplanar with the superconducting quantum chip 11, wherein the second Josephson junction 12 has the same structure as the first Josephson junction 111;
[0038] The second Josephson junction 12 is positioned adjacent to the edge of the superconducting quantum chip 11;
[0039] The second Josephson junction 12 is used to be tested to obtain a test result, and the test result is used as a basis for modifying the first Josephson junction 111 .
[0040] In the manufacturing process of the superconducting quantum chip 11, the superconducting quantum chip 11 is formed on the substrate 1 by a chip manufacturing process, and the superconducting quantum chip 11 includes a first Josephson junction 111. Generally speaking, after the superconducting quantum chip 11 is initially manufactured, the first Josephson junction 111 needs to be annealed and modified to achieve the specified performance parameters. In order to avoid the loss of superconducting quantum bit performance caused by directly inserting a probe into the electrode of the Josephson junction when the Josephson junction is tested at room temperature resistance as in the past; therefore, a second Josephson junction 12 is also provided in the embodiment of the present application, and the second Josephson junction 12 is used as a control group of the first Josephson junction 111 and is manufactured by the same process and the same flow as the first Josephson junction 111, so the internal structure of the second Josephson junction 12 is completely consistent with the first Josephson junction 111; in the manufacturing process of the superconducting quantum chip 11, the second Josephson junction 12 is only used to be inserted by a probe to test the room temperature resistance.
[0041] Further, in the manufacturing process of the second Josephson junction 12, in order not to occupy the area required by the superconducting quantum chip 11 and to be close to the superconducting quantum chip 11 for the convenience of subsequent process flow, the second Josephson junction 12 can be manufactured in the edge area close to the superconducting quantum chip 11. Then, the probe plus source meter is used to perform a normal temperature resistance test on the second Josephson junction 12, and the first Josephson junction 111 in the superconducting quantum chip 11 is laser annealed based on the test results obtained by the test. In general, by measuring the second Josephson junction 12 and then performing laser annealing on the first Josephson junction 111, the first Josephson junction 111 is not damaged by the probe during the test, and the laser annealing is completed to achieve the desired performance.
[0042] In some embodiments of the present application, the number of the superconducting quantum chips 11 is more than two.
[0043] In the manufacturing process of the superconducting quantum chip 11, a plurality of superconducting quantum chips 11 are often manufactured in the same batch; it is worth noting that since the plurality of superconducting quantum chips 11 in the batch are manufactured by the same process and the same parameters, the parameters of the quantum elements in the plurality of superconducting quantum chips 11 on the substrate 1 obtained in this batch can also be regarded as completely consistent, including the first Josephson junction 111 therein. Therefore, the parameters obtained after the above-mentioned room temperature resistance measurement of the second Josephson junction 12 are also applicable to the laser annealing modification of the first Josephson junction 111 in all the superconducting quantum chips 11 in the batch.
[0044] In some embodiments of the present application, all of the superconducting quantum chips 11 are separated from each other and arranged close to the central area of the substrate 1 .
[0045] In the subsequent process, multiple superconducting quantum chips 11 on the same batch and the same substrate 1 need to be separated to form multiple relatively independent superconducting quantum chips 11. Therefore, when multiple superconducting quantum chips 11 are manufactured, it is necessary to consider the separation between the multiple superconducting quantum chips 11 (such as cutting of the substrate 1, etc.), so the positions of each superconducting quantum chip 11 on the substrate 1 are separated from each other. In addition, in order to make the superconducting quantum chips 11 of this batch easier to manufacture and the mechanical moving distance as small as possible, all superconducting quantum chips 11 are arranged close to the central area of the substrate 1. Another beneficial effect of this arrangement is that the central area of the substrate 1 is operated, which can reduce the probability of the substrate 1 being broken to a certain extent.
[0046] In some embodiments of the present application, the second Josephson junction 12 is disposed close to the periphery of the substrate 1 .
[0047] Specifically, the second Josephson junction 12 is manufactured on the substrate 1 using the process used when manufacturing the first Josephson junction 111, and in order to allow all the superconducting quantum chips 11 to be completely and conveniently divided into separate superconducting quantum chips 11, the second Josephson junction 12 is manufactured at the peripheral position of the substrate 1; and after the superconducting quantum chip 11 is manufactured, the peripheral portion of the substrate 1 is relatively open and has no other superconducting elements, and the second Josephson junction 12 is provided here to reduce the impact on the superconducting quantum chip 11 to a certain extent. In addition, for the current manufacturing process, the superconducting quantum chip 11 is manufactured based on the substrate 1, and all structures of the superconducting quantum chip 11 cannot actually completely occupy the surface of the substrate 1, so some unused areas will be left at the peripheral portion of the substrate 1, and the second Josephson junction 12 is made in the peripheral area of the substrate 1, so the utilization rate of the surface of the substrate 1 can also be improved.
[0048] In some embodiments of the present application, the substrate 1 is a sapphire substrate or a silicon substrate.
[0049] The usual manufacturing materials of the chip, and the application in the superconducting quantum chip 11, the substrate 1 can be made of various appropriate materials, such as silicon or sapphire, which can be selected according to actual needs and is not limited to the above materials.
[0050] In some embodiments of the present application, the number of the first Josephson junctions 111 is more than two.
[0051] With the rapid advancement of quantum technology, there can often be dozens, hundreds or even thousands of bits in the same superconducting quantum chip 11, and the number of corresponding Josephson junctions is also increasing rapidly, and the test chip provided in the embodiment of the present application almost meets the use scenarios of all current superconducting quantum chips 11. In addition, the superconducting quantum chip 11 also has other components, such as signal lines, resonant cavities, ports, etc. During the manufacturing process of the superconducting quantum chip 11, the manufacturing position relationship between the Josephson junctions and other components should be reasonably distributed.
[0052] In some embodiments of the present application, the number of the second Josephson junctions 12 is more than two.
[0053] As mentioned above, in the test chip, the second Josephson junction 12 is manufactured as a test junction (control group) for testing in the test stage of the normal temperature resistance, and at least two probes are respectively inserted into the two electrodes of the second Josephson junction 12, and a voltage is applied to measure the normal temperature resistance of the second Josephson junction 12; however, if there is only one second Josephson junction 12, it is very likely that due to its manufacturing process or probe damage, there will be a gap between the actual parameters of the first Josephson junction 111 and the first Josephson junction 111 itself; therefore, a plurality of second Josephson junctions 12 are provided, and each second Josephson junction 12 is tested by the probe plus source meter to jointly complete the normal temperature resistance characterization, provide normal temperature resistance parameters that are relatively in line with reality, and subsequently perform laser annealing treatment on all the first Josephson junctions 111.
[0054] Specifically, all of the second Josephson junctions 12 are arranged around the superconducting quantum chip 11 .
[0055] Among them, in order to obtain more accurate parameters for characterizing the resistance at room temperature, a plurality of second Josephson junctions 12 are provided; as for the difference between the first Josephson junction 111 and the second Josephson junction 12 themselves, the two are manufactured through the same process, and during the manufacturing process, a plurality of second Josephson junctions 12 are arranged around the superconducting quantum chip 11, which not only reduces the moving distance of the instrument during the manufacturing process, but also reduces the natural effects such as oxidation of the material caused by the movement of the instrument, and never causes a parameter gap between the first Josephson junction 111 and the second Josephson junction 12 after being manufactured; all the second Josephson junctions 12 are arranged around the superconducting quantum chip 11, so as to maximize the first Josephson and the second Josephson junctions 12.
[0056] The present application also provides a repair system for operating the aforementioned test chip, comprising:
[0057] A conveying device 2, used for conveying the test chip;
[0058] A testing device 3 disposed at one end of the conveying device 2, for testing the room temperature resistance of the second Josephson junction 12;
[0059] The annealing device 4 disposed at one end of the conveying device 2 away from the testing device 3 is used to modify the room temperature resistance of the first Josephson junction 111 .
[0060] A plurality of clamping devices 5 matching the shape of the test chip are respectively located on the surfaces of the conveying device 2 , the testing device 3 and the annealing device 4 , and the test chip is fixed in the clamping devices 5 .
[0061] At present, the commonly used testing device 3 is a non-destructive probe station, which is mainly composed of components such as a slide, a probe seat, a scientific research camera and an illumination light source. The test chip is placed in the non-destructive probe station, and the electrical parameters of the second Josephson junction 12 therein are tested; in addition, the annealing device 4 is a laser annealing device, which is mainly composed of components such as a slide, a laser, a scientific research camera, an optical path switching component, a laser power monitor and a laser power regulator. The test chip is placed in the laser annealing device, and the first Josephson junction 111 thereof is subjected to an annealing modification process; in order to facilitate the transfer of the test chip, the embodiment of the present application also provides a conveying device 2 for transferring the test chip from the non-destructive probe station Transfer to the laser annealing equipment to realize the process flow; and, in order to make the test chip more stable on the repair equipment and avoid the test chip from slipping due to the vibration and movement of the various components of the repair equipment, a clamping device 5 is also provided to clamp and fix the test chip on the various components of the repair system; but the superconducting quantum chip 11 is generally relatively fragile, and may often be damaged by some mechanical clamping or collision behavior, causing the performance of the superconducting quantum chip 11 to degrade or be scrapped, so the selection of the clamping device 5 should meet the characteristics of sufficiently small damage to the superconducting quantum chip 11; the clamping device 5 can be a mortise and tenon structure or a ring buckle structure, which can be selected according to actual conditions.
[0062] Specifically, the conveying device 2 is a conveyor belt. One end of the conveyor belt is close to the non-destructive probe station, and the other end is close to the laser annealing equipment, so as to transfer the test chip between the non-destructive probe station and the laser annealing equipment to complete the room temperature resistance characterization of the second Josephson junction 12 and the laser annealing modified resistance of the first Josephson junction 111.
[0063] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "specific example" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.
[0064] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.
Claims
1. A test chip, characterized in that: include: Base (1); A superconducting quantum chip (11) manufactured on the surface of the substrate (1), wherein the superconducting quantum chip (11) has a first Josephson junction (111); a second Josephson junction (12) manufactured on the substrate (1) coplanarly with the superconducting quantum chip (11), wherein the second Josephson junction (12) has the same structure as the first Josephson junction (111); The second Josephson junction (12) is positioned adjacent to the edge of the superconducting quantum chip (11); The second Josephson junction (12) is used to be tested to obtain a test result, and the test result is used as a basis for modifying the first Josephson junction (111).
2. The test chip according to claim 1, characterized in that: The number of the superconducting quantum chips (11) is more than two.
3. The test chip according to claim 2, characterized in that: All of the superconducting quantum chips (11) are separated from each other and arranged close to the central area of the substrate (1).
4. The test chip according to claim 3, characterized in that: The second Josephson junction (12) is arranged close to the periphery of the substrate (1).
5. The test chip according to any one of claims 1 to 4, characterized in that: The substrate (1) is a sapphire substrate or a silicon substrate.
6. The test chip according to claim 1, characterized in that: The number of the first Josephson junctions (111) is two or more.
7. The test chip according to claim 6, characterized in that: The number of the second Josephson junctions (12) is two or more.
8. The test chip according to claim 7, characterized in that: All of the second Josephson junctions (12) are arranged around the superconducting quantum chip (11).
9. A repair system for operating the test chip according to any one of claims 1 to 8, characterized in that: include: A conveying device (2), used for conveying the test chip; A testing device (3) disposed at one end of the transmission device (2) and used for testing the room temperature resistance of the second Josephson junction (12); An annealing device (4) disposed at one end of the conveying device (2) away from the testing device (3), and used for modifying the room temperature resistance of the first Josephson junction (111); A plurality of clamping devices (5) matching the shape of the test chip are respectively located on the surfaces of the conveying device (2), the test device (3) and the annealing device (4), and the test chip is fixed in the clamping devices (5).
10. The repair system according to claim 9, characterized in that: The conveying device (2) is a conveyor belt.