High-speed data playback device

Abstract

The utility model relates to the technical field of data acquisition, in particular to a high-speed data playback device, which comprises a main control chip, a storage module, a channel selection module and a switching module. The main control chip controls the channel selection module through the switching module so as to select a suitable data transmission channel in the current scene; the main control chip can also select the operation mode of the storage module by controlling the switching module, so that the data transmission channel is matched with the operation mode of the storage module, the correct opening of the storage module is ensured, and the fault of the data playback device caused by wrong operation is avoided; according to the utility model, the technical problem that the channel configuration of the data recovery device is not flexible under the requirement of diversified data types is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of data acquisition, in particular to a high-speed data playback device. Background Art

[0002] A data recovery device is a device used to collect, process, store and recover data. In many fields, especially in the aerospace field, the data recovery device can effectively manage and reuse the collected data, reduce data loss and waste, and support in-depth analysis of the data, thereby optimizing flight performance, improving safety and promoting technological progress. Traditional data recovery devices are limited to supporting only single-channel data playback, which greatly limits their flexibility and breadth of application in processing complex, multi-dimensional data scenarios. Therefore, it is extremely important to solve the problem of data recovery device channel configuration.

[0003] The patent name that has been published is a Chinese utility model patent with the publication number CN216145101U, which is "A dual-channel high-speed data playback device". The various modules of this patent cooperate with each other to realize dual-channel data playback. Although the device provides multiple channels, each channel is designed to support only the transmission of data types in a fixed format. It can only transmit data types in a fixed format, which limits its breadth and practicality in practical applications. Utility Model Content

[0004] The purpose of the present application is to provide a high-speed data playback device, which solves the technical problem of inflexible channel configuration of a data recovery device under the requirements of diverse data types.

[0005] In order to solve the above technical problems, the solution adopted by this application is as follows:

[0006] The utility model provides a high-speed data playback device, comprising a main control chip and a storage module, wherein the input and output ends of the storage module are connected to the input and output end 1 of the main control chip; the utility model is characterized in that: the utility model further comprises a channel selection module and a switching module, wherein one end of the channel selection module is connected to an external device, and the other end is connected to the input and output end 2 of the main control chip; the input end of the switching module is connected to the signal output end of the main control chip, and the output end of the switching module is respectively connected to the enable end of the channel selection module and the enable end of the storage module;

[0007] The switching module includes a channel switching circuit; the channel switching circuit includes AND gate 1, AND gate 2, AND gate 3, NOT gate 1, and NOT gate 2; an input end of the AND gate 1, an input end of the AND gate 2, and an input end of the NOT gate 2 are connected as input end 1 of the channel switching circuit, and input end 1 of the channel switching circuit receives an external trigger signal; two input ends of the AND gate 1, an input end of the NOT gate 1, and an input end of the AND gate 3 are connected as input end 2 of the channel switching circuit, and input end 2 of the channel switching circuit is connected to a signal output end 1 of the main control chip; the output end of the NOT gate 1 is connected to input end 2 of the AND gate 2, and the output end of the NOT gate 2 is connected to input end 2 of the AND gate 3;

[0008] The output end of the AND gate 1 is set as the output end 1 of the channel switching circuit; the output end of the AND gate 2 is set as the output end 2 of the channel switching circuit, and the output end of the AND gate 3 is set as the output end 3 of the channel switching circuit;

[0009] The channel selection module includes an analog-to-digital converter, a digital-to-analog converter, and a common channel. One end of the analog-to-digital converter, one end of the digital-to-analog converter, and one end of the common channel are connected as one end of the channel switching module; the other end of the analog-to-digital converter, the other end of the digital-to-analog converter, and the other end of the common channel are connected as the other end of the channel switching module;

[0010] The enable end of the analog-to-digital converter, the enable end of the digital-to-analog converter, and the enable end of the common channel are collectively referred to as the enable end of the channel switching module. The enable end of the analog-to-digital converter, the enable end of the digital-to-analog converter, and the enable end of the common channel are respectively connected to the output end 2 of the channel switching circuit, the output end 3 of the channel switching circuit, and the output end 1 of the channel switching circuit.

[0011] In some embodiments, the switching module also includes a memory enabling circuit, and the memory enabling circuit includes AND gate 4, AND gate 5, AND gate 6, AND gate 7, AND gate 8, XOR gate 1, XOR gate 2, and NOT gate 3; the input terminal 1 of the XOR gate 1 is connected to the output terminal 2 of the channel switching circuit, the input terminal 1 of the AND gate 4 is connected to the write signal terminal of the main control chip, the input terminal 2 is connected to the output terminal 1 of the channel switching circuit, and the output terminal is connected to the input terminal 2 of the XOR gate 1; the output terminal of the XOR gate 1, the enable terminal of the storage module, and the input terminal 1 of the AND gate 5 are connected; the input terminal 2 of the AND gate 5 is connected to the priority control terminal of the main control chip, and the output terminal is connected to the memory. The enable end of the storage module is connected; the input end 1 of the AND gate 6 is connected to the output end 1 of the channel switching circuit, the input end 2 is connected to the read signal end of the main control chip, and the output end is connected to the input end 1 of the XOR gate 2; the input end 2 of the XOR gate 2 is connected to the output end 3 of the channel switching circuit, the output end of the XOR gate, the input end 1 of the AND gate 7, and the input end 1 of the AND gate 8 are connected; the input end 2 of the AND gate 7 is connected to the priority control end of the main control chip, the output end of the AND gate 7, the input end of the NOT gate 3, and the enable end of the storage module are connected; the input end 2 of the AND gate 8 is connected to the output end of the NOT gate 3, and the output end of the AND gate 8 is connected to the enable end of the storage module.

[0012] In some embodiments, the common channel also includes a field effect tube, the gate of the field effect tube serves as an enable end of the common channel and is connected to an output end of the channel switching module; the source of the field effect tube serves as one end of the common channel, and the drain of the field effect tube serves as the other end of the common channel.

[0013] In some embodiments, the common channel further includes a triode, and an output terminal 1 of the channel switching module is connected to a gate of the field effect tube through the triode.

[0014] In some embodiments, the storage module includes a memory 1 for recording data and a memory 2 for recording fault data, the input and output ends of the memory 1 are connected to the input and output ends of the memory 2 as the input and output ends of the storage module; the enable end of the memory 1 and the enable end of the memory 2 are respectively connected to the output end of the channel switching module.

[0015] In some embodiments, the main control chip is FPGA.

[0016] The technical solution of the present application has at least the following advantages and beneficial effects:

[0017] The utility model solves the technical problem of inflexible channel configuration of a data recovery device under the demand of diversified data types. When faced with diversified data types or changes in demand, the data playback device can flexibly adjust different channels through a switching module and a channel selection module to meet new transmission requirements, thereby expanding the scope of use of the data recovery device. The main control chip in the utility model is an FPGA chip, which has powerful data parallel processing capabilities and high-speed data processing characteristics, and can realize high-speed data transmission of the data recovery device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the overall structure of the utility model;

[0019] Figure 2 This is a channel switching circuit diagram of the utility model;

[0020] Figure 3 It is a memory enabling circuit diagram of the utility model;

[0021] Figure 4 This is a common channel circuit diagram of the utility model. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. If the terms "center", "upper", "lower", "inner", "outer", etc. indicate an orientation or position relationship based on the orientation or position relationship shown in the figure, or the orientation or position relationship in which the product of the application is usually placed when in use, it is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. It should also be noted that unless otherwise clearly specified and limited, if the terms "set", "install", and "connect" appear, they should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a connection between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] Example 1

[0025] Please refer to Figure 1-Figure 4 , the utility model provides a high-speed data playback device, which is the same as the prior art, and includes a main control chip and a storage module, wherein the input and output terminals of the storage module are connected to the input and output terminals of the main control chip;

[0026] The storage module includes a storage device 1 for recording data and a storage device 2 for recording fault data; the input and output terminals of the storage device 1 are connected to the input and output terminals of the storage device 2 as the input and output terminals of the storage module; the enable terminal of the storage device 1 and the enable terminal of the storage device 2 are respectively connected to the output terminal of the channel switching module;

[0027] The enable terminal of memory 1 includes a read enable terminal and a write enable terminal. If the read enable terminal of memory 1 receives a control signal, the memory starts to receive data transmitted by the main control chip; if the write enable terminal of memory 1 receives a control signal, the memory starts to transmit internal data to the main control chip. The enable terminal of memory 2 is the same as that of memory 1.

[0028] It needs to be explained that when the device is in the stage of collecting data, memory 1 receives all data transmitted by the main control chip, and memory 2 only needs to receive abnormal data after judgment and processing by the main control chip; when the device is in the stage of data playback, the main control chip outputs a control signal to preferentially control memory 2 to play back data first, and after all the data in memory 2 have been played back, the data playback function of memory 1 is turned on.

[0029] It should be noted that the main control chip is an FPGA chip, which has strong data parallel processing capabilities and high-speed data processing characteristics, and can realize high-speed data transmission of the data recovery device. The main control chip controls the read or write operation of memory one or memory two by outputting a control signal to the read or write enable terminal of memory one or memory two.

[0030] Different from the prior art, the present invention further comprises a channel selection module and a switching module, wherein one end of the channel selection module is connected to an external device, and the other end is connected to two input and output terminals of the main control chip; the input terminal of the switching module is connected to the signal output terminal of the main control chip, and the output terminal of the switching module is respectively connected to the enable terminal of the channel selection module and the enable terminal of the storage module;

[0031] The switching module includes a channel switching circuit; the channel switching circuit includes AND gate 1, AND gate 2, AND gate 3, NOT gate 1, and NOT gate 2; an input end of AND gate 1, an input end of AND gate 2, and an input end of NOT gate 2 are connected as input end 1 of the channel switching circuit, and input end 1 of the channel switching circuit receives an external trigger signal; a second input end of AND gate 1, an input end of NOT gate 1, and an input end of AND gate 3 are connected as input end 2 of the channel switching circuit, and input end 2 of the channel switching circuit is connected to a signal output end 1 of the main control chip; an output end of NOT gate 1 is connected to input end 2 of AND gate 2, and an output end of NOT gate 2 is connected to input end 2 of AND gate 3;

[0032] The output end of AND gate 1 is set as output end 1 of the channel switching circuit; the output end of AND gate 2 is set as output end 2 of the channel switching circuit; and the output end of AND gate 3 is set as output end 3 of the channel switching circuit;

[0033] The channel selection module includes an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a common channel. One end of the analog-to-digital converter, one end of the digital-to-analog converter, and one end of the common channel are connected as one end of the channel selection module; the other end of the analog-to-digital converter, the other end of the digital-to-analog converter, and the other end of the common channel are connected as the other end of the channel selection module;

[0034] The enable end of the analog-to-digital converter, the enable end of the digital-to-analog converter, and the enable end of the common channel are collectively referred to as the enable end of the channel switching module, and the enable end of the analog-to-digital converter, the enable end of the digital-to-analog converter, and the enable end of the common channel are respectively connected to the output end 2 of the channel switching circuit, the output end 3 of the channel switching circuit, and the output end 1 of the channel switching circuit.

[0035] It needs to be explained that when the analog-to-digital converter channel is turned on, it means that the data playback device is in the data acquisition stage, and the data transmitted by the external device is analog data; when the digital-to-analog converter channel is turned on, it means that the data recovery device is in the data playback stage, and the data output by the data recovery device is analog data; when the ordinary channel is turned on, it means that the data playback device and the external device interact with each other through digital signals. To determine whether the data playback device is collecting data or playing back data at this time, it is necessary to further determine based on the read or write control signal transmitted by the main control chip to the storage module.

[0036] For ease of understanding, Figure 2 As shown, the channel switching circuit includes an AND gate 1 U1, an AND gate 2 U2, an AND gate 3 U3, a NOT gate 1 U4, and a NOT gate 2 U5;

[0037] Specifically, the input terminal 1 of the AND gate U1, the input terminal 2 of the AND gate U2, and the input terminal of the NOT gate U5 are connected, and the input terminal is set here, and this input terminal is called the IN1 input terminal. The IN1 input terminal is the input terminal 1 of the channel switching circuit, which is used to connect to the external trigger signal; the input terminal 2 of the AND gate U1, the input terminal of the NOT gate U4, and the input terminal 1 of the AND gate U3 are connected, and the input terminal is set here, and this input terminal is called the IN2 input terminal. The IN2 input terminal is the input terminal 2 of the channel switching circuit, which is connected to the signal output terminal 1 of the main control chip; the output terminal of the AND gate U1 is set to OU T1 output terminal, OUT1 output terminal serves as input terminal one of the channel switching circuit, which is connected to the enable terminal of the common channel; input terminal two of gate U2 is connected to the output terminal of NAND gate U4, and the output terminal of gate U2 is set to OUT2 output terminal, and OUT2 output terminal serves as input terminal two of the channel switching circuit, which is connected to the enable terminal of the analog-to-digital converter; input terminal two of gate U3 is connected to the output terminal of NAND gate U5, and the output terminal of gate U3 is set to OUT3 output terminal, and OUT3 output terminal serves as input terminal three of the channel switching circuit, which is connected to the enable terminal of the digital-to-analog converter.

[0038] For ease of understanding, the working process of the channel switching circuit is now explained:

[0039] When receiving the signal from the main control chip and the external trigger signal at the same time, the AND gate U1 outputs a high level, at which time the common channel is turned on, and the data recovery device starts to transmit digital signal data with the external device;

[0040] When an external trigger signal is received but no signal from the main control chip is received, the AND gate U2 outputs a high level, at which time the analog-to-digital converter channel is turned on, and the data recovery device starts to collect the analog signal provided by the external device;

[0041] When a signal from the main control chip is received but no external trigger signal is received, AND gate U3 outputs a high level, at which time the digital-to-analog converter channel is turned on, and the data recovery device starts to play back the analog signal to the external device.

[0042] It should be noted that, under normal working conditions, only one of the three output terminals OUT1, OUT2 and OUT3 will output a high-level signal, and two or more channels will not be turned on at the same time.

[0043] It should be noted that the common channel includes a field effect tube, which is used for switching the channel, and its gate is connected to the output terminal 1 of the channel switching module as the enable terminal of the common channel; the source of the field effect tube is used as one end of the common channel, and the drain of the field effect tube is used as the other end of the common channel;

[0044] The common channel also includes a triode, and the output end 1 of the channel switching module is connected to the gate of the field effect tube through the triode.

[0045] For ease of understanding, Figure 4 As shown, the common channel includes field effect transistor Q1, transistor Q2, and resistors R1 and R2;

[0046] Specifically, one end of the resistor R2 is set to the input input end, which is connected to the OUT1 output end in the channel switching circuit; the other end of the resistor R2 is connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the power supply, the emitter of the transistor Q2, the gate of the field effect transistor, and one end of the resistor R1 are connected, and the other end of the resistor R1 is grounded; the drain of the field effect transistor Q1 is set to the data1 input and output end, which serves as one end of the common channel; the source of the field effect transistor Q1 is set to the data2 input and output end, which serves as the other end of the common channel.

[0047] Example 2

[0048] The difference between this embodiment and embodiment 1 is that the enable control terminal of the storage module is not only controlled by the main control chip, but is controlled by the channel switching circuit and the main control chip together, thereby ensuring the correct opening of the storage module and avoiding malfunction of the data playback device caused by erroneous operation.

[0049] The switching module also includes a memory enabling circuit, which includes AND gate 4, AND gate 5, AND gate 6, AND gate 7, AND gate 8, XOR gate 1, XOR gate 2, and NOT gate 3; the input terminal 1 of XOR gate 1 is connected to the output terminal 2 of the channel switching circuit, the input terminal 1 of AND gate 4 is connected to the write signal terminal of the main control chip, the input terminal 2 is connected to the output terminal 1 of the channel switching circuit, and the output terminal is connected to the input terminal 2 of XOR gate 1; the output terminal of XOR gate 1, the enabling terminal of the storage module, and the input terminal 1 of AND gate 5 are connected; the input terminal 2 of AND gate 5 is connected to the priority control terminal of the main control chip, and the output terminal is connected to the enabling terminal of the storage module. connected; input terminal 1 of AND gate 6 is connected to output terminal 1 of the channel switching circuit, input terminal 2 is connected to the read signal terminal of the main control chip, and the output terminal is connected to input terminal 1 of XOR gate 2; input terminal 2 of XOR gate 2 is connected to output terminal 3 of the channel switching circuit, the output terminal of the XOR gate, input terminal 1 of AND gate 7, and input terminal 1 of AND gate 8 are connected; input terminal 2 of AND gate 7 is connected to the priority control terminal of the main control chip, the output terminal of AND gate 7, the input terminal of NOT gate 3, and the enable terminal of the storage module are connected; input terminal 2 of AND gate 8 is connected to the output terminal of NOT gate 3, and the output terminal of AND gate 8 is connected to the enable terminal of the storage module.

[0050] For ease of understanding, Figure 3 As shown, the memory enabling circuit includes AND gate four U5, AND gate five U8, AND gate six U6, AND gate seven U9, AND gate eight U11, XOR gate one U4, XOR gate two U7, and NOT gate three U10;

[0051] Specifically, the input terminal one of the XOR gate U4 is called the IN3 input terminal, and the IN3 input terminal is connected to the OUT2 output terminal of the channel switching circuit; the input terminal one of the AND gate U5 is called the IN4 input terminal, and the IN4 input terminal one is connected to the write signal terminal of the main control chip; the input terminal two of the AND gate U5 is connected to the input terminal one of the AND gate U6, and an input terminal is set here, and this input terminal is called the IN5 input terminal, and the IN5 input terminal is connected to the OUT1 output terminal of the channel switching circuit; the output terminal of the AND gate U5 is connected to the input terminal two of the XOR gate U4, the output terminal of the XOR gate U4 is connected to the input terminal one of the AND gate U8, and an output terminal is set here, and the output terminal is called the OUT4 output terminal, and the OUT4 output terminal is connected to the write enable terminal of the memory one, the input terminal two of the AND gate U8 is connected to the input terminal two of the AND gate U9, and an input terminal is set here, and this input terminal is called the IN8 input terminal, and the IN8 input terminal is connected to the priority control terminal of the main control chip. The output end of the AND gate U8 is set to the OUT5 output end, and the OUT5 output end is connected to the write enable end of the memory two; the input end 2 of the AND gate U6 is set to the IN6 input end, and the IN6 input end is connected to the read signal end of the main control chip; the output end of the AND gate U6 is connected to the input end 1 of the XOR gate U7, and the input end 2 of the XOR gate U7 is set to the IN7 input end, and the IN7 input end is connected to the OUT3 output end of the channel switching circuit; the output end of the XOR gate U7, the input end 1 of the AND gate U9, and the input end 1 of the AND gate U11 are connected; the output end of the AND gate U9 is connected to the input end of the NOT gate U10, and an output end is set here, and this output end is called the OUT7 output end, and the OUT7 output end is connected to the read enable end of the memory two; the output end of the NOT gate U10 is connected to the input end 2 of the AND gate U11, and the output end of the AND gate U11 is called the OUT6 output end, and the OUT6 output end is connected to the read enable end of the memory one.

[0052] For ease of understanding, the working process of the memory enabling circuit is now described:

[0053] When the OUT2 output terminal outputs a signal, it means that the analog-to-digital converter channel is turned on, that is, the data playback device starts to collect analog data. At this time, after the XOR gate U4 receives a signal, the write channel is turned on, and the memory starts to continuously write data;

[0054] If the data collected by the main control chip is abnormal, the priority control terminal of the main control chip outputs a signal to open the memory 2, and the memory 2 starts to write the fault data until the data collected by the main control chip returns to normal, and the main control chip disconnects the signal of the write signal terminal of the memory 2;

[0055] When the OUT3 output terminal outputs a signal, it indicates that the digital-to-analog converter channel is turned on, that is, the data playback device starts to play back the data in the storage module. At this time, after the XOR gate 2 U4 receives the signal, the read channel is turned on; if the priority control terminal of the main control chip outputs a signal, the memory 2 starts to read data; if the priority control terminal of the main control chip does not output a signal, the memory 1 starts to read data;

[0056] When the OUT1 output terminal outputs a signal, it means that the normal channel is turned on. At this time, the main control chip needs to output a signal to determine whether it is a write operation or a read operation; if the write signal terminal of the main control chip outputs a control signal, the storage module starts the write operation. At this time, the specific process of the storage module is the same as the process when the analog-to-digital converter channel is turned on; if the read signal terminal of the main control chip outputs a control signal, the storage module starts the read operation. At this time, the specific process of the storage module is the same as the process when the digital-to-analog converter channel is turned on.

[0057] So far, various embodiments of the present invention have been described in detail. In order to avoid obscuring the concept of the present invention, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution of the present invention, and the scope of the present invention is defined by the attached claims.

Claims

1. A high-speed data playback device, comprising a main control chip and a storage module, wherein the input and output terminals of the storage module are connected to the input and output terminals of the main control chip; characterized in that: It also includes a channel selection module and a switching module, one end of the channel selection module is connected to the external device, and the other end is connected to the input and output terminals of the main control chip; the input end of the switching module is connected to the signal output terminal of the main control chip, and the output end of the switching module is respectively connected to the enable terminal of the channel selection module and the enable terminal of the storage module; The switching module includes a channel switching circuit; the channel switching circuit includes AND gate 1, AND gate 2, AND gate 3, NOT gate 1, and NOT gate 2; an input end of the AND gate 1, an input end of the AND gate 2, and an input end of the NOT gate 2 are connected as input end 1 of the channel switching circuit, and input end 1 of the channel switching circuit receives an external trigger signal; two input ends of the AND gate 1, an input end of the NOT gate 1, and an input end of the AND gate 3 are connected as input end 2 of the channel switching circuit, and input end 2 of the channel switching circuit is connected to a signal output end 1 of the main control chip; the output end of the NOT gate 1 is connected to input end 2 of the AND gate 2, and the output end of the NOT gate 2 is connected to input end 2 of the AND gate 3; The output end of the AND gate 1 is set as the output end 1 of the channel switching circuit; the output end of the AND gate 2 is set as the output end 2 of the channel switching circuit, and the output end of the AND gate 3 is set as the output end 3 of the channel switching circuit; The channel selection module includes an analog-to-digital converter, a digital-to-analog converter, and a common channel. One end of the analog-to-digital converter, one end of the digital-to-analog converter, and one end of the common channel are connected as one end of the channel switching module; the other end of the analog-to-digital converter, the other end of the digital-to-analog converter, and the other end of the common channel are connected as the other end of the channel switching module; The enable end of the analog-to-digital converter, the enable end of the digital-to-analog converter, and the enable end of the common channel are collectively referred to as the enable end of the channel switching module. The enable end of the analog-to-digital converter, the enable end of the digital-to-analog converter, and the enable end of the common channel are respectively connected to the output end 2 of the channel switching circuit, the output end 3 of the channel switching circuit, and the output end 1 of the channel switching circuit.

2. A high-speed data playback device according to claim 1, characterized in that: The switching module also includes a memory enabling circuit, which includes AND gate 4, AND gate 5, AND gate 6, AND gate 7, AND gate 8, XOR gate 1, XOR gate 2, and NOT gate 3; the input terminal 1 of the XOR gate 1 is connected to the output terminal 2 of the channel switching circuit, the input terminal 1 of the AND gate 4 is connected to the write signal terminal of the main control chip, the input terminal 2 is connected to the output terminal 1 of the channel switching circuit, and the output terminal is connected to the input terminal 2 of the XOR gate 1; the output terminal of the XOR gate 1, the enabling terminal of the storage module, and the input terminal 1 of the AND gate 5 are connected; the input terminal 2 of the AND gate 5 is connected to the priority control terminal of the main control chip, and the output terminal is connected to the priority control terminal of the storage module. The enable end is connected; the input end 1 of the AND gate 6 is connected to the output end 1 of the channel switching circuit, the input end 2 is connected to the read signal end of the main control chip, and the output end is connected to the input end 1 of the XOR gate 2; the input end 2 of the XOR gate 2 is connected to the output end 3 of the channel switching circuit, the output end of the XOR gate, the input end 1 of the AND gate 7, and the input end 1 of the AND gate 8 are connected; the input end 2 of the AND gate 7 is connected to the priority control end of the main control chip, the output end of the AND gate 7, the input end of the NOT gate 3, and the enable end of the storage module are connected; the input end 2 of the AND gate 8 is connected to the output end of the NOT gate 3, and the output end of the AND gate 8 is connected to the enable end of the storage module.

3. A high-speed data playback device according to claim 1, characterized in that: The common channel also includes a field effect tube, the gate of the field effect tube is connected to an output terminal of the channel switching module as an enable terminal of the common channel; the source of the field effect tube is used as one end of the common channel, and the drain of the field effect tube is used as the other end of the common channel.

4. A high-speed data playback device according to claim 3, characterized in that: The common channel also includes a triode, and an output end 1 of the channel switching module is connected to the gate of the field effect tube through the triode.

5. The high-speed data playback device according to claim 1, characterized in that: The storage module includes a memory 1 for recording data and a memory 2 for recording fault data. The input and output ends of the memory 1 are connected to the input and output ends of the memory 2 as the input and output ends of the storage module; the enable end of the memory 1 and the enable end of the memory 2 are respectively connected to the output end of the channel switching module.

6. The high-speed data playback device according to claim 1, characterized in that: The main control chip is a FPGA chip.

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