Display card fault recording circuit

Abstract

The utility model relates to a graphics card fault recording circuit, which comprises an MCU chip, a voltage regulation circuit, a unit temperature protection circuit and a binary recording circuit, the input end of the voltage regulation circuit is connected with each working voltage of a graphics card, the output end of the voltage regulation circuit is connected with the MCU chip, and the binary recording circuit is connected with the MCU chip. The unit temperature protection circuit is connected with a temperature protection signal, the output end of the unit protection circuit is connected with the MCU chip, and the binary recording circuit is connected with the MCU chip. Key voltage and temperature points of the display card are detected in real time through the MCU chip, when abnormal voltage is detected, digital codes corresponding to specific faults can be automatically generated and automatically stored in a specific register, reliable storage of fault information is ensured, PINs of the MCU chip are used as binary output interfaces, and by measuring the level states of the PINs, the fault information can be automatically stored in the specific register. A user can convert a fault code and quickly judge a fault condition.

Description

Technical Field

[0001] The utility model relates to the field of computer hardware design, in particular to a graphics card fault recording circuit. Background Art

[0002] Currently, when the graphics card is working normally, the GPU detects the various voltages of the graphics card, and the relevant voltage values ​​can only be displayed through software. The diagnosis and troubleshooting of graphics card failures usually rely on complex testing software and professional maintenance tools, which have the following problems:

[0003] 1. Faults caused by abnormal graphics card voltage will make the computer unable to work normally, making it impossible to use the test software;

[0004] 2. Traditional fault diagnosis requires maintenance personnel to use maintenance tools to check step by step according to circuit design drawings, which requires a high technical threshold and low efficiency;

[0005] 3. The existing graphics card circuit does not have the function of recording fault information and cannot provide important reference for subsequent fault analysis and repair. Summary of the invention

[0006] The utility model provides a graphics card fault recording circuit, aiming to solve the problem that the prior art is difficult to troubleshoot graphics card faults and has no fault recording.

[0007] The utility model provides a graphics card fault recording circuit, comprising an MCU chip, a voltage adjustment circuit, a unit temperature protection circuit and a binary recording circuit, wherein the input end of the voltage adjustment circuit is connected to each working voltage of the graphics card, the output end of the voltage adjustment circuit is connected to the MCU chip, the unit temperature protection circuit is connected to a temperature protection signal, the output end of the unit protection circuit is connected to the MCU chip, and the binary recording circuit is connected to the MCU chip.

[0008] As a further improvement of the present invention, the binary recording circuit includes resistors R10, R11, R12 and R13, one end of resistor R10 is connected to pin 20 of the MCU chip, one end of resistor R11 is connected to pin 21 of the MCU chip, one end of resistor R12 is connected to pin 22 of the MCU chip, one end of resistor R13 is connected to pin 23 of the MCU chip, and the other ends of resistor R10, R11, R12 and R13 are all grounded.

[0009] As a further improvement of the present utility model, the voltage adjustment circuit includes resistors R14, R15, R16, R17, R18 and R19, one end of resistor R14 is connected to a 12V voltage, the other end of resistor R14 is connected to one end of resistor R17, the other end of resistor R17 is grounded, pin 16 of the MCU chip is connected to the other end of resistor R14, one end of resistor R15 is connected to a 5V voltage, the other end of resistor R15 is connected to one end of resistor R18, the other end of resistor R18 is grounded, pin 9 of the MCU chip is connected to the other end of resistor R15, one end of resistor R16 is connected to a 3.3V voltage, the other end of resistor R16 is connected to one end of resistor R19, the other end of resistor R19 is grounded, and pin 8 of the MCU chip is connected to the other end of resistor R16.

[0010] As a further improvement of the present invention, the voltage adjustment circuit also includes resistors R20, R21, R22 and R23, one end of resistor R20 is connected to pin 4 of the MCU chip, one end of resistor R21 is connected to pin 6 of the MCU chip, one end of resistor R22 is connected to pin 5 of the MCU chip, one end of resistor R23 is connected to pin 7 of the MCU chip, and the other end of resistor R20, the other end of resistor R21, the other end of resistor R22 and the other end of resistor R23 are all connected to the 3.3V power supply of the graphics card connected to the motherboard through PCIE.

[0011] As a further improvement of the present utility model, pin 2 of the MCU chip is connected to pin 1 of the interface J1, pin 1 of the MCU chip is connected to pin 2 of the interface J1, pin 3 of the interface J1 is grounded, and the 3.3V power supply of the motherboard connected to the graphics card through PCIE is respectively connected to one end of resistor R8 and one end of resistor R9, the other end of resistor R8 is connected to pin 2 of the MCU chip, and the other end of resistor R9 is connected to pin 1 of the MCU chip.

[0012] As a further improvement of the present invention, the 10 pins of the MCU chip are respectively connected to one end of the capacitor C3 and one end of the capacitor C4, and the other end of the capacitor C3 and the other end of the capacitor C4 are both grounded.

[0013] As a further improvement of the present utility model, the unit temperature protection circuit includes a field effect tube Q1, the source of the field effect tube Q1 is connected to the temperature protection pins corresponding to the graphics card, video memory and MOS, the drain of the field effect tube Q1 is connected to the 15 pin of the MCU chip, the gate of the field effect tube Q1 is connected to a 1.8V voltage, one end of the resistor R24 ​​is connected to a 1.8V voltage, the other end of the resistor R24 ​​is connected to the source of the field effect tube Q1, one end of the resistor R25 is connected to a 3.3V voltage, and the other end of the resistor R25 is connected to the drain of the field effect tube Q1.

[0014] As a further improvement of the utility model, it also includes a graphics card reset detection circuit connected to the MCU chip, the graphics card reset detection circuit includes an AND gate U1, pins 1 and 2 of the AND gate U1 are connected to the reset signal of the motherboard, pin 4 of the AND gate U1 is connected to pin 14 of the MCU chip, pin 3 of the AND gate U1 is grounded, and pin 5 of the AND gate U1 is connected to a 3.3V voltage.

[0015] The beneficial effects of the utility model are as follows: the key voltage and temperature points of the graphics card are detected in real time through the MCU chip. When an abnormal voltage is detected, a digital code corresponding to a specific fault can be automatically generated and automatically saved in a specific register to ensure reliable storage of fault information. The PIN pins of the MCU chip are used as binary output interfaces. By measuring the level states of these PIN pins, the user can convert the fault code and quickly determine the fault condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a connection relationship diagram between various circuits of the utility model;

[0017] Figure 2 It is a specific circuit connection diagram of the MCU chip of the utility model;

[0018] Figure 3 It is a specific circuit connection diagram of the voltage regulating circuit of the utility model;

[0019] Figure 4 It is a specific circuit connection diagram of the unit temperature protection circuit of the utility model;

[0020] Figure 5 It is a specific circuit connection diagram of the graphics card reset detection circuit of the utility model;

[0021] Figure 6 It is a specific circuit connection diagram of the binary recording circuit of the utility model;

[0022] Figure 7 It is a binary matrix table of the utility model. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0024] The utility model provides a graphics card fault recording circuit, comprising an MCU chip, a voltage adjustment circuit, a unit temperature protection circuit and a binary recording circuit, wherein the input end of the voltage adjustment circuit is connected to each working voltage of the graphics card, the output end of the voltage adjustment circuit is connected to the MCU chip, the unit temperature protection circuit is connected to a temperature protection signal, the output end of the unit protection circuit is connected to the MCU chip, and the binary recording circuit is connected to the MCU chip.

[0025] As an embodiment of the utility model, the binary recording circuit includes resistors R10, R11, R12 and R13, one end of resistor R10 is connected to pin 20 of the MCU chip, one end of resistor R11 is connected to pin 21 of the MCU chip, one end of resistor R12 is connected to pin 22 of the MCU chip, one end of resistor R13 is connected to pin 23 of the MCU chip, and the other end of resistor R10, the other end of resistor R11, the other end of resistor R12 and the other end of resistor R13 are all grounded.

[0026] As another embodiment of the utility model, the voltage adjustment circuit includes resistors R14, R15, R16, R17, R18 and R19, one end of the resistor R14 is connected to a 12V voltage, the other end of the resistor R14 is connected to one end of the resistor R17, the other end of the resistor R17 is grounded, the 16 pin of the MCU chip is connected to the other end of the resistor R14, one end of the resistor R15 is connected to a 5V voltage, the other end of the resistor R15 is connected to one end of the resistor R18, the other end of the resistor R18 is grounded, the 9 pin of the MCU chip is connected to the other end of the resistor R15, one end of the resistor R16 is connected to a 3.3V voltage, the other end of the resistor R16 is connected to one end of the resistor R19, the other end of the resistor R19 is grounded, and the 8 pin of the MCU chip is connected to the other end of the resistor R16.

[0027] As another embodiment of the utility model, the voltage adjustment circuit also includes resistor R20, resistor R21, resistor R22 and resistor R23, one end of resistor R20 is connected to pin 4 of the MCU chip, one end of resistor R21 is connected to pin 6 of the MCU chip, one end of resistor R22 is connected to pin 5 of the MCU chip, one end of resistor R23 is connected to pin 7 of the MCU chip, and the other end of resistor R20, the other end of resistor R21, the other end of resistor R22 and the other end of resistor R23 are all connected to the 3.3V power supply of the graphics card connected to the motherboard through PCIE.

[0028] As another embodiment of the utility model, pin 2 of the MCU chip is connected to pin 1 of the interface J1, pin 1 of the MCU chip is connected to pin 2 of the interface J1, pin 3 of the interface J1 is grounded, and the 3.3V power supply of the motherboard connected to the graphics card through PCIE is respectively connected to one end of resistor R8 and one end of resistor R9, the other end of resistor R8 is connected to pin 2 of the MCU chip, and the other end of resistor R9 is connected to pin 1 of the MCU chip.

[0029] As another embodiment of the present utility model, the 10 pins of the MCU chip are respectively connected to one end of the capacitor C3 and one end of the capacitor C4, and the other end of the capacitor C3 and the other end of the capacitor C4 are both grounded.

[0030] As another embodiment of the utility model, the unit temperature protection circuit includes a field effect transistor Q1, the source of the field effect transistor Q1 is connected to the temperature protection pins corresponding to the graphics card, video memory and MOS, the drain of the field effect transistor Q1 is connected to pin 15 of the MCU chip, the gate of the field effect transistor Q1 is connected to a 1.8V voltage, one end of the resistor R24 ​​is connected to a 1.8V voltage, the other end of the resistor R24 ​​is connected to the source of the field effect transistor Q1, one end of the resistor R25 is connected to a 3.3V voltage, and the other end of the resistor R25 is connected to the drain of the field effect transistor Q1.

[0031] As another embodiment of the utility model, it also includes a graphics card reset detection circuit connected to the MCU chip, and the graphics card reset detection circuit includes an AND gate U1, and pins 1 and 2 of the AND gate U1 are connected to the reset signal of the motherboard, pin 4 of the AND gate U1 is connected to pin 14 of the MCU chip, pin 3 of the AND gate U1 is grounded, and pin 5 of the AND gate U1 is connected to a 3.3V voltage.

[0032] The utility model provides a graphics card fault recording circuit, which detects the key voltage and temperature points of the graphics card in real time through the MCU chip. When an abnormal voltage is detected, it can automatically generate a digital code corresponding to a specific fault and automatically save it to a specific register to ensure reliable storage of fault information. At the same time, this solution uses the PIN pins of the MCU chip as a binary output interface. By measuring the level status of these PIN pins, the user can convert the fault code. In addition, it also supports directly reading the fault code in the register through the I2C interface, so as to quickly determine the fault type.

[0033] like Figure 2 As shown, this circuit constitutes a minimum system of an MCU chip.

[0034] like Figure 3As shown in the figure, since the working voltages of the graphics card are different, in order to adapt to the IO level specification of the MCU chip, the voltage signal higher than VDD is adjusted to 3.3V by voltage division, and the voltage signal lower than VDD is detected by the PGOOD signal of the power IC, and PGOOD is pulled up to 3.3V, so as not to affect the working voltage of the graphics card. Each signal is connected to the MCU chip to detect each working voltage.

[0035] like Figure 4 As shown, the THERM_OVER* network is connected to the temperature protection PINs corresponding to the graphics card GPU, video memory, and MOS. Since the graphics card IO level specification is 1.8V, a level conversion is required to convert it to 3.3V to adapt to the IO specification of the MCU chip. When the temperature of one of the units reaches the protection value, the network will be pulled down to 0V.

[0036] like Figure 5 As shown, PEX_RST is the reset signal of PCIE. The signal is filtered into a 3.3V signal PEX_RST_BUF through the AND gate U1. This signal is the reset signal sent to the graphics card after the motherboard is initialized. This signal can be used to determine whether the motherboard has completed initialization.

[0037] like Figure 6 As shown in Figure 1, it is a binary matrix composed of four IO interfaces of the MCU chip. The binary matrix table is as follows: Figure 7 As shown, 0 represents a low level, 1 represents a high level (3.3V), and DEC is the abbreviation for decimal system.

[0038] The design logic of this scheme is as follows:

[0039] MCU chip connection Figure 3 The GPU working voltage and PGOOD signal after processing are used to determine whether the corresponding voltage is powered on normally according to the high and low levels of each signal. Figure 4 The THERM_OVER signal in the graphics card is used to determine whether the graphics card triggers temperature protection through high and low levels.

[0040] Since it takes a process to power up each voltage of the graphics card, the MCU chip will make a misjudgment when the rated voltage value is not reached. Therefore, it is necessary to wait until the graphics card is powered on before detecting its various signals. Since the computer design specification requires that each voltage of the graphics card must be powered on before the motherboard PEX_RST signal is sent, the PEX_RST_BUF signal can be connected through the MCU chip, and all signals are detected only when the signal is high. Considering the situation that the computer is shut down, the MCU VDD power-off speed is slower than the GPU voltage power-off speed. In this way, the MCU chip is still working, which will cause misjudgment of the GPU voltage. Since the PEX_RST_BUF signal will be pulled low when the computer is shut down, the GPU will not shut down until it detects that this signal is low. Therefore, it can be set in the MCU chip to stop fault detection when the PEX_RST_BUF signal is low.

[0041] When the MCU chip detects a fault, Figure 7 As listed in the binary matrix, the fault is saved in the form of decimal code to ROM, and is expressed in the form of high and low levels at the PB0~PB3 interface. For example: when there is no abnormality, PB0~PB3 are all set to low level, and the no abnormality code is 0 and does not need to be saved; when NVVDD_PGOOD is low level, PB0 and PB1 output high level, PB2 and PB3 are set to low level, and the decimal code 3 is saved in the ROM of the MCU chip.

[0042] When the computer is turned on and the MCU chip is initialized, the MCU chip automatically reads the value stored in the ROM, and converts the read value into binary according to TABLE 1 to initialize PB0~PB3. When troubleshooting, you can directly measure the voltage of PB0~PB3 to determine what fault has occurred in the graphics card. You can also connect the I2C interface J1 of the MCU chip through a fixture and directly read the code stored in the ROM to determine the fault.

[0043] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A graphics card fault recording circuit, characterized in that: It includes an MCU chip, a voltage adjustment circuit, a unit temperature protection circuit and a binary recording circuit. The input end of the voltage adjustment circuit is connected to each working voltage of the graphics card, the output end of the voltage adjustment circuit is connected to the MCU chip, the unit temperature protection circuit is connected to a temperature protection signal, the output end of the unit temperature protection circuit is connected to the MCU chip, and the binary recording circuit is connected to the MCU chip.

2. A graphics card fault recording circuit according to claim 1, characterized in that: The binary recording circuit includes resistors R10, R11, R12 and R13, one end of resistor R10 is connected to pin 20 of the MCU chip, one end of resistor R11 is connected to pin 21 of the MCU chip, one end of resistor R12 is connected to pin 22 of the MCU chip, one end of resistor R13 is connected to pin 23 of the MCU chip, and the other ends of resistor R10, R11, R12 and R13 are all grounded.

3. A graphics card fault recording circuit according to claim 1, characterized in that: The voltage adjustment circuit includes resistor R14, resistor R15, resistor R16, resistor R17, resistor R18 and resistor R19, one end of resistor R14 is connected to a 12V voltage, the other end of resistor R14 is connected to one end of resistor R17, the other end of resistor R17 is grounded, pin 16 of the MCU chip is connected to the other end of resistor R14, one end of resistor R15 is connected to a 5V voltage, the other end of resistor R15 is connected to one end of resistor R18, the other end of resistor R18 is grounded, pin 9 of the MCU chip is connected to the other end of resistor R15, one end of resistor R16 is connected to a 3.3V voltage, the other end of resistor R16 is connected to one end of resistor R19, the other end of resistor R19 is grounded, and pin 8 of the MCU chip is connected to the other end of resistor R16.

4. A graphics card fault recording circuit according to claim 3, characterized in that: The voltage adjustment circuit also includes resistor R20, resistor R21, resistor R22 and resistor R23. One end of resistor R20 is connected to pin 4 of the MCU chip, one end of resistor R21 is connected to pin 6 of the MCU chip, one end of resistor R22 is connected to pin 5 of the MCU chip, one end of resistor R23 is connected to pin 7 of the MCU chip, and the other ends of resistor R20, resistor R21, resistor R22 and resistor R23 are all connected to the 3.3V power supply of the graphics card connected to the motherboard through PCIE.

5. A graphics card fault recording circuit according to claim 1, characterized in that: Pin 2 of the MCU chip is connected to pin 1 of the interface J1, pin 1 of the MCU chip is connected to pin 2 of the interface J1, pin 3 of the interface J1 is grounded, the 3.3V power supply of the motherboard connected to the graphics card through PCIE is respectively connected to one end of resistor R8 and one end of resistor R9, the other end of resistor R8 is connected to pin 2 of the MCU chip, and the other end of resistor R9 is connected to pin 1 of the MCU chip.

6. A graphics card fault recording circuit according to claim 1, characterized in that: Pin 10 of the MCU chip is connected to one end of the capacitor C3 and one end of the capacitor C4 respectively, and the other end of the capacitor C3 and the other end of the capacitor C4 are both grounded.

7. A graphics card fault recording circuit according to claim 1, characterized in that: The unit temperature protection circuit includes a field effect tube Q1, the source of the field effect tube Q1 is connected to the temperature protection pins corresponding to the graphics card, video memory and MOS, the drain of the field effect tube Q1 is connected to the 15 pin of the MCU chip, the gate of the field effect tube Q1 is connected to a 1.8V voltage, one end of the resistor R24 ​​is connected to a 1.8V voltage, the other end of the resistor R24 ​​is connected to the source of the field effect tube Q1, one end of the resistor R25 is connected to a 3.3V voltage, and the other end of the resistor R25 is connected to the drain of the field effect tube Q1.

8. A graphics card fault recording circuit according to claim 1, characterized in that: It also includes a graphics card reset detection circuit connected to the MCU chip, the graphics card reset detection circuit includes an AND gate U1, pins 1 and 2 of the AND gate U1 are connected to the reset signal of the motherboard, pin 4 of the AND gate U1 is connected to pin 14 of the MCU chip, pin 3 of the AND gate U1 is grounded, and pin 5 of the AND gate U1 is connected to a 3.3V voltage.

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