Power amplification circuit and radio frequency chip

Abstract

The utility model is suitable for the technical field of wireless communication radio frequency chip design, and particularly relates to a power amplification circuit and a radio frequency chip. The power amplification circuit provided by the utility model comprises a signal input end, an envelope detector, a control voltage generation network, a power amplifier and a signal output end, the signal input end is connected with the input end of the envelope detector and the first input end of the power amplifier, the output end of the envelope detector is connected with the input end of the control voltage generation network, the output end of the control voltage generation network is connected with the second input end of the power amplifier, and the output end of the power amplifier is connected with the signal output end. Therefore, the power amplification circuit provided by the utility model improves the efficiency and the linearity of the power amplifier at the same time, and compared with an out-phase power amplifier, the power amplification circuit does not need signal decomposition, so that the limitation on the bandwidth is reduced.

Description

Technical Field

[0001] The utility model is applicable to the technical field of wireless communication radio frequency chip design, and in particular relates to a power amplifier circuit and a radio frequency chip. Background Art

[0002] The power amplifier is one of the most energy-consuming devices in the RF front end of wireless communication equipment. Improving the efficiency of the power amplifier is crucial to reducing the power consumption of the entire RF front end. Generally, the power amplifier can achieve the highest efficiency when the power is close to saturation. However, the linearity of the power amplifier in the saturation region usually deteriorates seriously due to gain compression and other reasons. Therefore, high efficiency and high linearity are often not achieved at the same time for the power amplifier.

[0003] Existing power amplifiers mainly use envelope tracking technology and out-of-phase power amplifier technology to improve the efficiency of power amplifiers. Envelope tracking technology is a widely used method to improve the efficiency of power amplifiers. It adjusts the drain / collector voltage of the power amplifier according to the input RF power, so that the power amplifier always works in a saturated state, thereby effectively improving the average efficiency of the power amplifier in the entire power range. However, since the gain of the power amplifier changes with the bias voltage, in general, the linearity of the envelope tracking amplifier is worse than that of the constant voltage power amplifier.

[0004] The out-of-phase power amplifier technology decomposes a non-constant envelope signal into two constant envelope signals for linear amplification, so that the power amplifier can always work at the peak power (high efficiency point). In addition, for the constant envelope signal, a switching power amplifier can also be used to maximize efficiency. However, in the out-of-phase power amplifier architecture, after the modulated signal is decomposed into a constant envelope signal, the bandwidth of the signal will be significantly expanded, which will have higher requirements for the bandwidth of the power amplifier, and there will be a problem of consistency between the two branches, which requires a very complex adaptive algorithm to solve, and the hardware implementation is also difficult.

[0005] Therefore, a new power amplifier circuit and radio frequency chip are urgently needed to solve the above problems. Utility Model Content

[0006] The utility model provides a power amplifier circuit and a radio frequency chip, aiming to simultaneously improve the linearity and efficiency of the power amplifier.

[0007] In a first aspect, the utility model provides a power amplifier circuit, the power amplifier circuit comprising a signal input terminal, an envelope detector, a control voltage generating network, a power amplifier and a signal output terminal;

[0008] The signal input end is connected to the input end of the envelope detector and the first input end of the power amplifier, the output end of the envelope detector is connected to the input end of the control voltage generating network, the output end of the control voltage generating network is connected to the second input end of the power amplifier, and the output end of the power amplifier is connected to the signal output end; the envelope detector is used to output the envelope signal in the modulated signal input by the signal input end to the control voltage generating network, and the control voltage generating network is used to output the corresponding control voltage to the power amplifier according to the envelope signal.

[0009] Preferably, the control voltage generating network includes an analog-to-digital converter, a register and a digital-to-analog converter, the input end of the analog-to-digital converter serves as the input end of the control voltage generating network, the output end of the analog-to-digital converter is connected to the input end of the register, the output end of the register is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter serves as the output end of the control voltage generating network; the analog-to-digital converter is used to convert the envelope signal into a digital signal, the register is used to determine the value of the control voltage according to the digital signal, and the digital-to-analog converter is used to generate a corresponding control voltage according to the value of the control voltage.

[0010] Preferably, the power amplifier includes an input matching network, a signal amplification network and an output matching network, the input end of the input matching network is connected to an external bias voltage, the output end of the input matching network is connected to the first input end of the signal amplification network, the first input end of the signal amplification network serves as the first input end of the power amplifier, the second input end of the signal amplification network serves as the second input end of the power amplifier, the output end of the signal amplification network is connected to the input end of the output matching network, and the output end of the output matching network serves as the output end of the power amplifier.

[0011] Preferably, the input matching network includes a first capacitor and a first inductor, the first end of the first capacitor is grounded, the second end of the first capacitor is connected to the first end of the first inductor, the first end of the first inductor serves as the input end of the input matching network, and the second end of the first inductor serves as the output end of the input matching network.

[0012] Preferably, the signal amplification network includes a first transistor, a second transistor and a second capacitor, the base of the first transistor serves as the first input end of the signal amplification network, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the emitter of the second transistor, the collector of the second transistor serves as the output end of the signal amplification network, the base of the second transistor serves as the second input end of the signal amplification network, the first end of the second capacitor is connected to the base of the second transistor, and the second end of the second capacitor is grounded.

[0013] Preferably, the output matching network includes a third capacitor and a second inductor, the first end of the second inductor serves as the input end of the output matching network, the second end of the second inductor serves as the output end of the output matching network, the first end of the third capacitor is connected to the second end of the second inductor, and the second end of the third capacitor is grounded.

[0014] In a second aspect, the utility model further provides a radio frequency chip, wherein the radio frequency chip comprises a power amplifier circuit as described in any one of the above embodiments.

[0015] Compared with the prior art, the power amplifier circuit provided by the utility model includes a signal input terminal, an envelope detector, a control voltage generating network, a power amplifier and a signal output terminal; the signal input terminal is connected to the input terminal of the envelope detector and the first input terminal of the power amplifier, the output terminal of the envelope detector is connected to the input terminal of the control voltage generating network, the output terminal of the control voltage generating network is connected to the second input terminal of the power amplifier, and the output terminal of the power amplifier is connected to the signal output terminal; the envelope detector is used to output the envelope signal in the modulated signal input by the signal input terminal to the control voltage generating network, and the control voltage generating network is used to output the corresponding control voltage to the power amplifier according to the envelope signal. In this way, the power amplifier circuit provided by the utility model improves the efficiency and linearity of the power amplifier at the same time, and compared with the out-of-phase power amplifier, the utility model does not need to perform signal decomposition, thereby reducing the limitation on bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The utility model is described in detail below in conjunction with the accompanying drawings. The above and other aspects of the utility model will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0017] Figure 1 It is a circuit structure diagram of a power amplifier circuit provided by an embodiment of the utility model;

[0018] Figure 2 It is a circuit structure diagram of a power amplifier of the power amplifier circuit provided by an embodiment of the utility model;

[0019] Figure 3 It is a schematic diagram showing the improvement of the efficiency and linearity of a power amplifier according to an embodiment of the utility model.

[0020] In the figure, 100, power amplifier circuit, 1, signal input terminal, 2, envelope detector, 3, control voltage generating network, 4, power amplifier, 5, signal output terminal, 31, analog-to-digital converter, 32, register, 33, digital-to-analog converter, 41, input matching network, 42, signal amplification network, 43, output matching network. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0022] Embodiment 1

[0023] Please refer to Figure 1-Figure 2 , the utility model provides a power amplifier circuit 100, the power amplifier circuit 100 comprises a signal input terminal 1, an envelope detector 2, a control voltage generating network 3, a power amplifier 4 and a signal output terminal 5;

[0024] The signal input terminal 1 is connected to the input terminal of the envelope detector 2 and the first input terminal of the power amplifier 4, the output terminal of the envelope detector 2 is connected to the input terminal of the control voltage generating network 3, the output terminal of the control voltage generating network 3 is connected to the second input terminal of the power amplifier 4, and the output terminal of the power amplifier 4 is connected to the signal output terminal 5; the envelope detector 2 is used to output the envelope signal in the modulated signal input from the signal input terminal 1 to the control voltage generating network 3, and the control voltage generating network 3 is used to output the corresponding control voltage V according to the envelope signal 0 To the power amplifier 4.

[0025] In the embodiment of the utility model, the control voltage generation network 3 includes an analog-to-digital converter 31, a register 32 and a digital-to-analog converter 33, the input end of the analog-to-digital converter 31 serves as the input end of the control voltage generation network 3, the output end of the analog-to-digital converter 31 is connected to the input end of the register 323, the output end of the register 32 is connected to the input end of the digital-to-analog converter 33, and the output end of the digital-to-analog converter 33 serves as the output end of the control voltage generation network 3; the analog-to-digital converter 31 is used to convert the envelope signal into a digital signal, and the register 32 is used to determine the control voltage V according to the digital signal 0 The digital-to-analog converter 33 is used to control the voltage V0 The value of the corresponding control voltage V 0 .

[0026] In the embodiment of the utility model, the power amplifier 4 includes an input matching network 41, a signal amplification network 42 and an output matching network 43. The input end of the input matching network 41 is connected to an external bias voltage V b The output end of the input matching network 41 is connected to the first input end of the signal amplifying network 42, the first input end of the signal amplifying network 42 serves as the first input end of the power amplifier 4, the second input end of the signal amplifying network 42 serves as the second input end of the power amplifier 4, the output end of the signal amplifying network 42 is connected to the input end of the output matching network 43, the output end of the output matching network 43 serves as the output end of the power amplifier 4.

[0027] In an embodiment of the utility model, the input matching network 41 includes a first capacitor C1 and a first inductor L1, the first end of the first capacitor C1 is grounded, the second end of the first capacitor C1 is connected to the first end of the first inductor L1, the first end of the first inductor L1 serves as the input end of the input matching network 41, and the second end of the first inductor L1 serves as the output end of the input matching network 41.

[0028] In an embodiment of the utility model, the signal amplification network 42 includes a first transistor Q1, a second transistor Q2 and a second capacitor C2, the base of the first transistor Q1 serves as the first input end of the signal amplification network 42, the emitter of the first transistor Q1 is grounded, the collector of the first transistor Q1 is connected to the emitter of the second transistor Q2, the collector of the second transistor Q2 serves as the output end of the signal amplification network 42, the base of the second transistor Q2 serves as the second input end of the signal amplification network 42, the first end of the second capacitor C2 is connected to the base of the second transistor Q2, and the second end of the second capacitor C2 is grounded.

[0029] In an embodiment of the utility model, the output matching network 43 includes a third capacitor C3 and a second inductor L2, the first end of the second inductor L2 serves as the input end of the output matching network 43, the second end of the second inductor L2 serves as the output end of the output matching network 43, the first end of the third capacitor C3 is connected to the second end of the second inductor L2, and the second end of the third capacitor C3 is grounded.

[0030] Specifically, the specific circuit structure of the power amplifier 4 is as follows: Figure 2 As shown, the output power can be controlled by the base of the second transistor Q2 to control the voltage V 0When the power amplifier 4 is close to the saturation region, a corresponding control voltage V can be provided to the power amplifier 4 at different input powers. 0 This ensures that the power amplifier 4 is in a saturated state, thereby achieving high efficiency. At the same time, the output power of the power amplifier 4 is linearly related to the input power, thereby maximizing its linearity.

[0031] In the embodiment of the utility model, the envelope detector 2 detects the envelope signal of the RF power input by the signal input terminal 1, and provides the envelope signal to the analog-to-digital converter 31 in the control voltage generating network 3 for analog-to-digital conversion. The register 32 stores the envelope signal and the control voltage V 0 The mapping relationship between them, and the way to obtain the mapping relationship, such as Figure 3 As shown, Figure 3 is a schematic diagram of the efficiency and linearity improvement of the power amplifier 4 according to the embodiment of the utility model. When the control voltage V 0 When the value of V changes from 2.4V to 2.8V, the output power and the input power present different transmission lines. Several different control voltages V can be recorded in register 32. 0 In order to improve the linearity of the power amplifier 4 in the high efficiency region, it is necessary to ensure that the output power satisfies the linear relationship between the input power and the input power. Based on the different control voltages V 0 The input power and output power values ​​under the control voltage V can be adjusted at a specific input power. 0 , thereby satisfying the linear relationship between output power and input power. The analog-to-digital converter 31 converts the envelope signal into a digital signal and transmits it to the register 32. The register 32 determines the control voltage V according to the digital signal provided by the analog-to-digital converter 31. 0 The value of the control voltage V 0 The value is transmitted to the digital-to-analog converter 33, and the digital-to-analog converter 33 generates a control voltage V 0 Provided to the base of the second transistor Q2, so that the first transistor Q1 for amplifying the signal can be biased at a specific external bias voltage V under different input powers b Under this condition, the goals of high efficiency and high linearity are achieved.

[0032] Compared with the prior art, the power amplifier circuit provided by the utility model includes a signal input terminal, an envelope detector, a control voltage generating network, a power amplifier and a signal output terminal; the signal input terminal is connected to the input terminal of the envelope detector and the first input terminal of the power amplifier, the output terminal of the envelope detector is connected to the input terminal of the control voltage generating network, the output terminal of the control voltage generating network is connected to the second input terminal of the power amplifier, and the output terminal of the power amplifier is connected to the signal output terminal; the envelope detector is used to output the envelope signal in the modulated signal input by the signal input terminal to the control voltage generating network, and the control voltage generating network is used to output the corresponding control voltage to the power amplifier according to the envelope signal. In this way, the power amplifier circuit provided by the utility model improves the efficiency and linearity of the power amplifier at the same time, and compared with the out-of-phase power amplifier, the utility model does not need to perform signal decomposition, thereby reducing the limitation on bandwidth.

[0033] Embodiment 2

[0034] The embodiment of the utility model further provides a radio frequency chip, which includes the power amplifier circuit 100 as described in the above embodiment and can achieve the same technical effect. Please refer to the description in the above embodiment and will not be repeated here.

[0035] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0036] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiments of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms of equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A power amplifier circuit, characterized in that: The power amplifier circuit includes a signal input terminal, an envelope detector, a control voltage generating network, a power amplifier and a signal output terminal; The signal input end is connected to the input end of the envelope detector and the first input end of the power amplifier respectively, the output end of the envelope detector is connected to the input end of the control voltage generating network, the output end of the control voltage generating network is connected to the second input end of the power amplifier, and the output end of the power amplifier is connected to the signal output end; the envelope detector is used to output the envelope signal in the modulated signal input by the signal input end to the control voltage generating network, and the control voltage generating network is used to output the corresponding control voltage to the power amplifier according to the envelope signal.

2. The power amplifier circuit according to claim 1, characterized in that: The control voltage generation network includes an analog-to-digital converter, a register and a digital-to-analog converter, the input end of the analog-to-digital converter serves as the input end of the control voltage generation network, the output end of the analog-to-digital converter is connected to the input end of the register, the output end of the register is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter serves as the output end of the control voltage generation network; The analog-to-digital converter is used to convert the envelope signal into a digital signal, the register is used to determine the value of the control voltage according to the digital signal, and the digital-to-analog converter is used to generate a corresponding control voltage according to the value of the control voltage.

3. The power amplifier circuit according to claim 1, characterized in that: The power amplifier includes an input matching network, a signal amplification network and an output matching network. The input end of the input matching network is connected to an external bias voltage, the output end of the input matching network is connected to the first input end of the signal amplification network, the first input end of the signal amplification network serves as the first input end of the power amplifier, the second input end of the signal amplification network serves as the second input end of the power amplifier, the output end of the signal amplification network is connected to the input end of the output matching network, and the output end of the output matching network serves as the output end of the power amplifier.

4. The power amplifier circuit according to claim 3, characterized in that: The input matching network includes a first capacitor and a first inductor, the first end of the first capacitor is grounded, the second end of the first capacitor is connected to the first end of the first inductor, the first end of the first inductor serves as the input end of the input matching network, and the second end of the first inductor serves as the output end of the input matching network.

5. The power amplifier circuit according to claim 3, characterized in that: The signal amplification network includes a first transistor, a second transistor and a second capacitor; the base of the first transistor serves as the first input end of the signal amplification network, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the emitter of the second transistor, the collector of the second transistor serves as the output end of the signal amplification network, the base of the second transistor serves as the second input end of the signal amplification network, the first end of the second capacitor is connected to the base of the second transistor, and the second end of the second capacitor is grounded.

6. The power amplifier circuit according to claim 3, characterized in that: The output matching network includes a third capacitor and a second inductor; the first end of the second inductor serves as the input end of the output matching network, the second end of the second inductor serves as the output end of the output matching network, the first end of the third capacitor is connected to the second end of the second inductor, and the second end of the third capacitor is grounded.

7. A radio frequency chip, characterized in that: The radio frequency chip includes the power amplifier circuit as described in any one of claims 1-6.

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