Frequency hopping signal real-time detection method and system based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor)

Abstract

The invention discloses a frequency hopping signal real-time detection method and system based on FPGA + DSP. The system comprises a time frequency analysis module, a data communication module and a frequency hopping signal detection module. The method comprises the following steps: a time frequency analysis module performs analog-to-digital conversion and digital down-conversion on an intermediate frequency signal received from a radio frequency end, and performs short-time Fourier transform on a zero intermediate frequency signal by adopting a four-pipeline processing mode; the data communication module transmits the frequency spectrum information from the FPGA to the DSP through an SRIO protocol; the frequency hopping signal detection module calculates a dynamic threshold of a current frame signal according to the received frequency spectrum information, and completes preliminary detection of the signal according to a threshold value; and carrying out binarization processing and connected domain marking on the detected frequency spectrum, screening non-frequency hopping signals according to time-frequency information of a connected domain, and packaging and uploading parameter information of the detected frequency hopping signals to an upper computer. The method is simple in algorithm, low in hardware resource requirement and high in detection efficiency, and the feasibility of engineering implementation is improved.

Description

Technical Field

[0001] The invention relates to the technical field of signal detection, in particular to a real-time detection method and system for frequency hopping signals based on FPGA+DSP. Background Art

[0002] As the battle for radio waves in the field of communication intensifies, the commonly used fixed-frequency signals are seriously threatened. In order to ensure reliable communication, an anti-interference communication system, the frequency hopping communication system, came into being. Frequency hopping communication has been increasingly widely used due to its strong anti-interference and anti-interception capabilities.

[0003] The frequency hopping communication system is a communication method in which the carrier frequency of the transmission signal of the sender and receiver changes discretely according to a predetermined rule. The carrier frequency used in the communication changes randomly under the control of a pseudo-random change code. Compared with fixed-frequency communication, frequency hopping communication is more concealed and difficult to intercept. As long as the other party is not clear about the law of carrier frequency hopping, it is difficult to intercept our communication content. At the same time, frequency hopping communication also has good anti-interference ability. Even if some frequency points are interfered, normal communication can still be carried out on other uninterrupted frequency points.

[0004] In the civilian field, there is strong noise interference in the communication frequency band. Due to the fast hopping speed and large frequency set of the frequency hopping signal, in most cases, the interference frequency band can be avoided and communication can continue, which greatly improves the communication quality. In recent years, frequency hopping communication radio stations have played a pivotal role. Their excellent confidentiality performance makes it more difficult to search, intercept, analyze and identify the other party's communication targets. For this reason, it is very important to carry out research on key technologies of frequency hopping reconnaissance.

[0005] At present, many scholars at home and abroad have carried out in-depth research on the detection technology of frequency hopping signals and proposed many detection methods. The invention patent CN 116886124 A discloses a frequency hopping signal tracking and suppression method. Through noise reduction and binarization, image information extraction, clustering and feature extraction, frequency hopping detection is performed, which effectively solves the problems of high energy consumption, easy to miss hopping and low interference success rate in the existing technology. However, there are still the following problems that need to be solved urgently: First, most detection algorithms only consider the effect of simulation implementation, and their high complexity and large amount of calculation are often impossible to implement in actual engineering; second, due to limited hardware processing resources, most methods are difficult to meet the real-time requirements of frequency hopping detection, and cannot achieve relatively fast signal detection. In order to solve the above problems, it is necessary to optimize the detection algorithm and increase the schedulable hardware resources to achieve real-time and fast detection of frequency hopping signals. Summary of the invention

[0006] The object of the present invention is to provide a method and system for real-time detection of frequency hopping signals based on FPGA+DSP with simple algorithm, low hardware resource requirement and high detection efficiency.

[0007] The technical solution to realize the present invention is: a real-time detection method of frequency hopping signals based on FPGA+DSP, based on a time-frequency analysis module, a data communication module and a frequency hopping signal detection module, specifically comprising the following steps:

[0008] Step 1: The time-frequency analysis module performs analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end;

[0009] Step 2: The time-frequency analysis module performs digital down-conversion and double decimation on the digital intermediate frequency signal;

[0010] Step 3: The time-frequency analysis module performs short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode;

[0011] Step 4: The data communication module performs high-speed transmission of spectrum data between FPGA and DSP through the SRIO protocol;

[0012] Step 5: The frequency hopping signal detection module adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to preliminarily complete the frequency hopping signal detection;

[0013] Step 6: The frequency hopping signal detection module performs binarization processing on the signal after preliminary detection;

[0014] Step 7: The frequency hopping signal detection module marks the connected domain of the binary data matrix, obtains the signal time-frequency information consisting of the start time and the start frequency, and completes the screening of non-frequency hopping signals.

[0015] A frequency hopping signal real-time detection system based on FPGA+DSP, the system is used to implement the frequency hopping signal real-time detection method based on FPGA+DSP, the system includes a time-frequency analysis module, a data communication module and a frequency hopping signal detection module, wherein:

[0016] The time-frequency analysis module is used to perform analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end, perform digital down-conversion and double decimation on the digital intermediate frequency signal to reduce the sampling rate and data volume, and perform short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode;

[0017] The data communication module is used for high-speed transmission of spectrum data between FPGA and DSP through SRIO protocol;

[0018] The frequency hopping signal detection module adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to perform frequency hopping signal detection, performs binarization processing on the detected signal to reduce data storage resources, marks the connected domain of the binary data matrix, obtains the signal time-frequency information composed of the start time and the start frequency, and completes the screening of non-frequency hopping signals based on this.

[0019] A mobile terminal comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the program, the real-time detection method for frequency hopping signals based on FPGA+DSP is implemented.

[0020] A computer-readable storage medium stores a computer program, which implements the steps of the real-time detection method of frequency-hopping signals based on FPGA+DSP when executed by a processor.

[0021] Compared with the prior art, the present invention has the following significant advantages: (1) FPGA and DSP are used as the hardware architecture of the detection system, wherein FPGA has abundant logic resources and DSP has abundant computing and storage resources, thereby meeting the hardware resource requirements for real-time and rapid detection of frequency-hopping signals; (2) In the time-frequency analysis module, a four-stage pipeline short-time Fourier transform is adopted to ensure the continuity of high-speed signal processing; (3) In the frequency-hopping signal detection module, a detection algorithm based on adaptive dynamic threshold and connected domain marking is adopted, thereby reducing the complexity of the algorithm, improving the detection efficiency, and improving the feasibility of engineering implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The present invention is a schematic structural diagram of a frequency hopping signal real-time detection system based on FPGA+DSP.

[0023] Figure 2 The present invention is a flowchart of a method for real-time detection of frequency hopping signals based on FPGA+DSP.

[0024] Figure 3 It is a schematic diagram of the process of ADC data format conversion in the present invention.

[0025] Figure 4 It is a schematic diagram of the process of digital down-conversion in the present invention.

[0026] Figure 5 Schematic diagram of the process flow of the four-stage pipeline STFT processing in the present invention. DETAILED DESCRIPTION

[0027] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0028] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0029] The present invention relates to a real-time detection method for frequency hopping signals based on FPGA+DSP. Firstly, analog-to-digital conversion is performed on an intermediate frequency signal received from a radio frequency end, and digital down-conversion is performed on an output digital intermediate frequency signal to reduce a sampling rate and a data volume; then, short-time Fourier transform is performed on a zero intermediate frequency signal in a four-pipeline processing mode; and spectrum information is transmitted from the FPGA to the DSP through an SRIO protocol; then, a dynamic threshold of a current frame signal is calculated according to the received spectrum information, and preliminary detection of the signal is completed with the threshold value; finally, binarization processing and connected domain marking are performed on the detected spectrum, non-frequency hopping signals are screened according to the time-frequency information of the connected domain, and parameter information of the detected frequency hopping signal is packaged and uploaded to a host computer.

[0030] The present invention provides a real-time detection method for frequency hopping signals based on FPGA+DSP, based on a time-frequency analysis module, a data communication module and a frequency hopping signal detection module, and specifically comprises the following steps:

[0031] Step 1: The time-frequency analysis module performs analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end;

[0032] Step 2: The time-frequency analysis module performs digital down-conversion and double decimation on the digital intermediate frequency signal;

[0033] Step 3: The time-frequency analysis module performs short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode;

[0034] Step 4: The data communication module performs high-speed transmission of spectrum data between FPGA and DSP through the SRIO protocol;

[0035] Step 5: The frequency hopping signal detection module adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to preliminarily complete the frequency hopping signal detection;

[0036] Step 6: The frequency hopping signal detection module performs binarization processing on the signal after preliminary detection;

[0037] Step 7: The frequency hopping signal detection module marks the connected domain of the binary data matrix, obtains the signal time-frequency information consisting of the start time and the start frequency, and completes the screening of non-frequency hopping signals.

[0038] As a specific example, the time-frequency analysis module described in step 1 performs analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end, as follows:

[0039] The connection between the ADC acquisition module and the FPGA uses the standard LPC FMC interface. The FPGA first configures the registers of the clock chip AD9516 through the SPI bus to output a 250MHz differential clock to the sampling chip LTC2158. At the same time, the registers of the LTC2158 are configured through the SPI bus to start ADC sampling normally; then the clock signal and data signal sampled by the ADC and input to the FPGA are format converted.

[0040] As a specific example, the time-frequency analysis module described in step 2 performs digital down-conversion and two-fold decimation on the digital intermediate frequency signal, as follows:

[0041] Since the maximum bandwidth that can actually detect the signal is only 60MHz, and the effective frequency band of the digital signal collected by the ADC is distributed within the set range of 153.6MHz, in order to meet the bandpass sampling law in, A higher sampling rate of 204.8MHz is required, which results in a larger amount of output data, but the effective frequency band of the signal occupies less space, resulting in a certain waste of resources. Therefore, the signal needs to be digitally down-converted to reduce the signal data rate.

[0042] Digital down-conversion consists of mixing and filtering. First, the DDS IP core in the FPGA generates a 153.6MHz local oscillator signal. Then, the local oscillator signal is multiplied with the intermediate frequency signal output by the ADC for mixing to achieve the shift of the spectrum to the baseband. Finally, the zero intermediate frequency IQ signal passes through an FIR filter with a passband of 30MHz and a stopband of 51.2MHz to filter out the effective frequency band signal and complete the double extraction of the signal to reduce the sampling rate and data rate.

[0043] As a specific example, the time-frequency analysis module described in step 3 performs short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode, as follows:

[0044] Short-time Fourier transform (STFT), also known as windowed Fourier transform, is to multiply the signal to be analyzed by a window function of limited length before Fourier transform to intercept the signal for a period of time, and then perform Fourier transform to obtain the spectrum information of this period of time; as the window function slides on the time axis, the time information of different time periods can be intercepted, so that not only the spectrum information of the entire signal to be analyzed is obtained, but also the time information of the corresponding spectrum is understood;

[0045] For a given stationary signal x(t)∈L 2 R, where L 2represents the space of square integrable functions, R represents the set of real numbers, then the short-time Fourier transform STFT(t,ω) of the signal x(t) is defined as:

[0046]

[0047] Where t represents the time variable, ω represents the frequency variable, τ represents the integral variable, x(τ) represents the input signal, and h(τ-t) represents the window function;

[0048] The discrete form of STFT(t,ω) is STFT(n,k):

[0049]

[0050] In the formula, n represents the discrete time variable, k represents the discrete frequency variable, m represents the summation variable, x(m) represents the discrete time series of the original signal x(t), N represents the number of discrete short-time Fourier transform points, and h(nm) represents the discrete form of the window function.

[0051] Basically, no prior information is needed to use STFT for time-frequency analysis, but attention should be paid to the choice of window function: the length of the window determines the time resolution and frequency resolution, and the shape of the window determines the main lobe width and spectrum leakage of the spectrum. Since each signal point participates in the calculation of multiple STFT points, if the number of FFT calculations for each signal point is reduced, the amount of data calculation and algorithm complexity will be greatly reduced. Therefore, the length of the window is adjusted to the number of FFT points, and the sliding step of the window is adjusted to the length of the window; because the final time-frequency diagram only requires accurate reading of the main lobe frequency without considering the amplitude accuracy, the window function type selects a rectangular window with a narrow main lobe width that is easy to distinguish;

[0052] Since the output speed of DDC data is greater than the calculation speed of subsequent STFT, there will be a processing time difference between the two. The DDC data during this period will be lost, making the processed signal discontinuous. To solve this problem, a four-pipeline STFT process is designed to continuously store DDC data during the time difference between DDC and STFT processing. Four pipelines are used for parallel processing to achieve data buffering. This ensures that when the data in RAM1 is being transmitted by STFT and SRIO, the DDC data is continuously stored in RAM2, RAM3 and RAM4 in sequence, thereby achieving continuous signal processing.

[0053] As a specific example, the frequency hopping signal detection module described in step 5 adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to preliminarily complete the frequency hopping signal detection, as follows:

[0054] Step 5.1, calculate the power spectrum of the current frame signal, and limit the power spectrum;

[0055] Step 5.2, obtain the noise power spectrum through FIR filtering to obtain the noise distribution in the signal, and perform threshold gain on the noise power as the dynamic threshold for signal detection;

[0056] Step 5.3: Perform preliminary detection and processing on the power spectrum of the effective signal according to the threshold value, and record the FFT index of all the power greater than the threshold value to indicate the location of the effective frequency point;

[0057] Step 5.4, estimate the center frequency of the effective frequency point based on the FFT index data, remove the influence of the sidelobe frequency, and further determine the presence or absence of the effective frequency point signal by comparing the bandwidth occupied by the initially detected effective frequency point with the minimum frequency bandwidth. If there is a signal, the maximum amplitude point of the bandwidth occupied by the effective frequency point is considered to be the center frequency; if there is no signal, the effective frequency point is filtered out.

[0058] As a specific example, the frequency hopping signal detection module described in step 6 performs binarization processing on the signal after preliminary detection, as follows:

[0059] The original signal spectrum is binarized according to the FFT index of the effective frequency point detected by the detection algorithm to obtain a 0 / 1 data matrix to reduce data storage resources.

[0060] As a specific example, the frequency hopping signal detection module described in step 7 marks the connected domain of the binary data matrix, obtains the signal time-frequency information composed of the start time and the start frequency, and completes the screening of non-frequency hopping signals, as follows:

[0061] Step 7.1: If the pixel values ​​of two adjacent pixels in the image are the same, their pixel regions are considered to be connected. The two pixels are merged together and marked as a connected region. The connected regions are divided into 4-adjacent and 8-adjacent regions according to their positional relationship.

[0062] Step 7.2: Use the 0 / 1 data matrix composed of the binary spectrum data of each time frame as a time-frequency image of the signal, mark the connected domains of the signals in the time-frequency image, and thus obtain the bandwidth and residence time occupied by each hop signal;

[0063] Step 7.3: In view of the fact that a sudden situation may occur in the actual signal and cause the connected domain to be broken, a connected domain repair algorithm is used to repair the broken connected domain;

[0064] Step 7.4: According to the difference between the frequency hopping signal and other signals in terms of time-frequency morphology, the frequency hopping signal is screened out, and the bandwidth, dwell time and frequency hopping set parameter information of the frequency hopping signal are uploaded to the host computer.

[0065] The present invention provides a frequency hopping signal real-time detection system based on FPGA+DSP, which is used to implement the frequency hopping signal real-time detection method based on FPGA+DSP. The system includes a time-frequency analysis module, a data communication module and a frequency hopping signal detection module, wherein:

[0066] The time-frequency analysis module is used to perform analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end, perform digital down-conversion and double decimation on the digital intermediate frequency signal to reduce the sampling rate and data volume, and perform short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode;

[0067] The data communication module is used for high-speed transmission of spectrum data between FPGA and DSP through SRIO protocol;

[0068] The frequency hopping signal detection module adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to perform frequency hopping signal detection, performs binarization processing on the detected signal to reduce data storage resources, marks the connected domain of the binary data matrix, obtains the signal time-frequency information composed of the start time and the start frequency, and completes the screening of non-frequency hopping signals based on this.

[0069] The present invention also provides a mobile terminal, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the FPGA+DSP-based real-time frequency hopping signal detection method when executing the program.

[0070] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in the real-time detection method of frequency-hopping signals based on FPGA+DSP are implemented.

[0071] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0072] Example 1

[0073] like Figure 1 As shown, this embodiment provides a frequency hopping signal real-time detection system based on FPGA+DSP, which is used to implement the frequency hopping signal real-time detection method based on FPGA+DSP. The system includes a time-frequency analysis module, a data communication module and a frequency hopping signal detection module;

[0074] The time-frequency analysis module is used to implement the following functions:

[0075] First, perform analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end;

[0076] Second, digital down-conversion and two-fold decimation are performed on the digital intermediate frequency signal to reduce the sampling rate and data volume;

[0077] Third, short-time Fourier transform is performed on the zero-IF signal in pipeline processing mode;

[0078] The data communication module is used to implement the following functions:

[0079] High-speed transmission of spectrum data between FPGA and DSP through SRIO protocol;

[0080] The frequency hopping signal detection module is used to implement the following functions:

[0081] First, design a frequency hopping signal detection algorithm based on adaptive dynamic threshold: first, calculate the power spectrum of the current frame signal and limit the power spectrum; then, obtain the noise power spectrum through FIR filtering to obtain the noise distribution in the signal, and then perform appropriate threshold gain on the noise power to use it as the dynamic threshold for signal detection; finally, compare the threshold value with the original signal power at the corresponding position to preliminarily complete the frequency hopping signal detection;

[0082] Second, binarization is performed on the detected signal to reduce data storage resources;

[0083] Third, the connected domains of the binary data matrix are marked to obtain the signal time-frequency information consisting of the start time and the start frequency, and based on this, the non-frequency hopping signals such as fixed-frequency signals, swept-frequency signals and burst signals are screened.

[0084] Example 2

[0085] like Figure 2 As shown, this embodiment provides a real-time detection method for frequency hopping signals based on FPGA+DSP, comprising the following steps:

[0086] Step 1: The time-frequency analysis module performs analog-to-digital conversion on the intermediate frequency signal received from the RF end, as follows:

[0087] The connection between the ADC acquisition module and the FPGA uses the standard LPC FMC interface. The FPGA first configures the register of the clock chip AD9516 through the SPI bus to output a 250MHz differential clock to the sampling chip LTC2158. At the same time, the register of the LTC2158 is configured through the SPI bus to start ADC sampling normally; then the clock signal and data signal after ADC sampling and input to the FPGA are format converted, such as Figure 3 shown.

[0088] Step 2: The time-frequency analysis module performs digital down-conversion and double decimation on the digital intermediate frequency signal to reduce the sampling rate and data volume, as follows:

[0089] Since the maximum bandwidth of the actual detectable signal is only 60MHz, and the effective frequency band of the digital signal collected by the ADC is distributed around 153.6MHz, in order to satisfy the bandpass sampling law in, A higher sampling rate of 204.8MHz is required, which results in a larger amount of output data, but the effective frequency band of the signal occupies less space, resulting in a certain waste of resources. Therefore, the signal needs to be digitally down-converted to reduce the signal data rate.

[0090] Digital down-conversion consists of mixing and filtering, such as Figure 4 As shown, first, the DDSIP core in the FPGA generates a 153.6MHz local oscillator signal; then the local oscillator signal is multiplied with the intermediate frequency signal output by the ADC for mixing to achieve the shift of the spectrum to the baseband; finally, the zero intermediate frequency IQ signal passes through a FIR filter with a passband of 30MHz and a stopband of 51.2MHz to filter out the effective frequency band signal and complete the double extraction of the signal to reduce the sampling rate and data rate.

[0091] Step 3: The time-frequency analysis module performs short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode, as follows:

[0092] Short-time Fourier transform (STFT), also known as windowed Fourier transform, is one of the most classic and mature methods in time-frequency analysis. Its implementation principle is to multiply the signal to be analyzed by a window function of limited length before Fourier transform to intercept the signal for a period of time, and then perform Fourier transform to obtain the spectrum information of this period of time; and as the window function slides on the time axis, the time information of different time periods can be intercepted, so that not only the spectrum information of the entire signal to be analyzed is obtained, but also the time information of the corresponding spectrum can be understood, which is of great help in analyzing non-stationary signals such as frequency hopping signals;

[0093] In other words, the short-time Fourier transform can also be called the windowed Fourier transform. For a given stationary signal x(t)∈L 2 R, the short-time Fourier transform of the signal x(t) is defined as:

[0094] STFT(t,ω)=∫x(τ)h(τ-t)e -jωτ dτ

[0095] Where h(t) is the window function;

[0096] Its discrete form is:

[0097]

[0098] Where WN =e -j2π / N ;

[0099] Basically, no prior information is needed to use STFT for time-frequency analysis, but attention should be paid to the choice of window function: the length of the window determines the time resolution and frequency resolution, and the shape of the window determines the main lobe width and spectrum leakage of the spectrum. Since each signal point participates in the calculation of multiple STFT points, if the number of FFT calculations for each signal point is reduced, the amount of data calculation and algorithm complexity will be greatly reduced. Therefore, the length of the window is adjusted to the number of FFT points, and the sliding step of the window is adjusted to the length of the window; because the final time-frequency diagram only requires accurate reading of the main lobe frequency without considering the amplitude accuracy, the window function type can choose a rectangular window with a narrow main lobe width that is easy to distinguish;

[0100] The output speed of DDC data is greater than the subsequent STFT calculation speed, which will lead to a processing time difference between the two. The DDC data during this period will be lost, making the processed signal discontinuous. In order to solve this problem, a four-pipeline STFT process is adopted, such as Figure 5 As shown in the figure, the core of the design is that the storage of DDC data does not stop within the time difference between the processing of the two modules. The parallel processing of the pipeline can be used to realize data buffering and improve the overall processing speed. After testing, the time for DDC to fill a RAM is 80us, the time required to complete the STFT of 8192 points is 153us, and the transmission time of an SRIO is 57us. Therefore, four pipelines are used for parallel processing to ensure that when the data in RAM1 is performing STFT and SRIO transmission, the DDC data can be stored in RAM2, RAM3 and RAM4 in sequence, thereby realizing continuous signal processing.

[0101] Step 4: The data communication module performs high-speed transmission of spectrum data between FPGA and DSP through the SRIO protocol;

[0102] Step 5: The frequency hopping signal detection module uses a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to preliminarily complete the frequency hopping signal detection, as follows:

[0103] For the 8192-point FFT spectrum information of the current frame received by SRIO, it contains the spectrum information of the entire 102.4Mhz bandwidth. In order to reduce the amount of data processing, the 4800-point FFT spectrum information of the 60MHz effective signal bandwidth is intercepted;

[0104] Step 5.1, calculate the power spectrum of the spectrum of the effective signal of the current frame, and after limiting the power spectrum, filter out the noise power spectrum through the FIR filter;

[0105] Step 5.2: After thresholding the noise power spectrum, a dynamic threshold is obtained. The power spectrum of the effective signal is preliminarily detected and processed according to the threshold value, and the FFT index of all the power greater than the threshold value is recorded to indicate the location of the effective frequency point;

[0106] Step 5.3: Estimate the center frequency of the effective frequency point based on the FFT index data, remove the influence of the sidelobe frequency, and further determine the presence or absence of the frequency point signal by comparing the bandwidth occupied by the initially detected effective frequency point with the minimum frequency bandwidth. If there is a signal, the maximum amplitude point of the frequency band is considered to be the center frequency; if there is no signal, the frequency point is filtered out.

[0107] Step 6: The frequency hopping signal detection module performs binarization processing on the detected signal to reduce data storage resources, as follows:

[0108] The original signal spectrum is binarized according to the FFT index of the effective frequency point detected by the detection algorithm to obtain a 0 / 1 data matrix.

[0109] Step 7: The frequency hopping signal detection module marks the connected domain of the binary data matrix to obtain the signal time-frequency information composed of the start time and the start frequency, and completes the screening of non-frequency hopping signals based on this, as follows:

[0110] Step 7.1: If two adjacent pixels in the image have the same pixel value, their pixel regions are considered to be connected. The two pixels can be merged together and marked as a connected region. According to the positional relationship of the connected region, it can be divided into 4-adjacent and 8-adjacent regions.

[0111] Step 7.2: Use the 0 / 1 data matrix consisting of 4800 points of binary spectrum data of each time frame as a time-frequency image of the signal, mark the connected domains of the signals in the time-frequency image, and thus obtain the occupied bandwidth and residence time of each hop signal;

[0112] Step 7.3: In view of the fact that a sudden situation may occur in the actual signal and cause the connected domain to be broken, a connected domain repair algorithm is used to repair the broken connected domain;

[0113] Step 7.4: According to the difference between the frequency hopping signal and other signals in terms of time-frequency morphology, the frequency hopping signal is selected, and its occupied bandwidth, dwell time and frequency hopping set parameter information are uploaded to the host computer.

[0114] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A real-time detection method for frequency hopping signals based on FPGA+DSP, characterized in that: Based on the time-frequency analysis module, the data communication module and the frequency hopping signal detection module, the specific steps include: Step 1: The time-frequency analysis module performs analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end; Step 2: The time-frequency analysis module performs digital down-conversion and double decimation on the digital intermediate frequency signal; Step 3: The time-frequency analysis module performs short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode; Step 4: The data communication module performs high-speed transmission of spectrum data between FPGA and DSP through the SRIO protocol; Step 5: The frequency hopping signal detection module adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to preliminarily complete the frequency hopping signal detection; Step 6: The frequency hopping signal detection module performs binarization processing on the signal after preliminary detection; Step 7: The frequency hopping signal detection module marks the connected domain of the binary data matrix, obtains the signal time-frequency information consisting of the start time and the start frequency, and completes the screening of non-frequency hopping signals.

2. The method for real-time detection of frequency hopping signals based on FPGA+DSP according to claim 1, characterized in that: The time-frequency analysis module described in step 1 performs analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end, as follows: The connection between the ADC acquisition module and the FPGA uses the standard LPC FMC interface. The FPGA first configures the registers of the clock chip AD9516 through the SPI bus to output a 250MHz differential clock to the sampling chip LTC2158. At the same time, the registers of the LTC2158 are configured through the SPI bus to start ADC sampling normally; then the clock signal and data signal sampled by the ADC and input to the FPGA are format converted.

3. The real-time detection method for frequency hopping signals based on FPGA+DSP according to claim 2 is characterized in that: The time-frequency analysis module described in step 2 performs digital down-conversion and double decimation on the digital intermediate frequency signal, as follows: Digital down-conversion consists of mixing and filtering. First, the DDS IP core in the FPGA generates a 153.6MHz local oscillator signal. Then, the local oscillator signal is multiplied with the intermediate frequency signal output by the ADC for mixing to achieve the shift of the spectrum to the baseband. Finally, the zero intermediate frequency IQ signal passes through an FIR filter with a passband of 30MHz and a stopband of 51.2MHz to filter out the effective frequency band signal and complete the double extraction of the signal to reduce the sampling rate and data rate.

4. The method for real-time detection of frequency hopping signals based on FPGA+DSP according to claim 3 is characterized in that: The time-frequency analysis module described in step 3 performs short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode, as follows: For a given stationary signal x(t)∈L 2 R, where L 2 represents the space of square integrable functions, R represents the set of real numbers, then the short-time Fourier transform STFT(t,ω) of the signal x(t) is defined as: Where t represents the time variable, ω represents the frequency variable, τ represents the integral variable, x(τ) represents the input signal, and h(τ-t) represents the window function; The discrete form of STFT(t,ω) is STFT(n,k): In the formula, n represents the discrete time variable, k represents the discrete frequency variable, m represents the summation variable, x(m) represents the discrete time series of the original signal x(t), N represents the number of discrete short-time Fourier transform points, and h(nm) represents the discrete form of the window function. The length of the window determines the time resolution and frequency resolution, and the shape of the window determines the main lobe width and spectrum leakage of the spectrum. The length of the window is adjusted to the number of points for FFT, and the sliding step of the window is adjusted to the length of the window; Select rectangular window as the window function type; A four-pipeline STFT processing is designed to continuously store DDC data within the time difference between DDC and STFT processing. Four pipelines are used for parallel processing to achieve data buffering. This ensures that when the data in RAM1 is being transmitted through STFT and SRIO, the DDC data is continuously stored in RAM2, RAM3, and RAM4 in sequence, thereby achieving continuous signal processing.

5. The method for real-time detection of frequency hopping signals based on FPGA+DSP according to claim 4, characterized in that: The frequency hopping signal detection module described in step 5 adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to preliminarily complete the frequency hopping signal detection, as follows: Step 5.1, calculate the power spectrum of the current frame signal, and limit the power spectrum; Step 5.2, obtain the noise power spectrum through FIR filtering to obtain the noise distribution in the signal, and perform threshold gain on the noise power as the dynamic threshold for signal detection; Step 5.3: Perform preliminary detection and processing on the power spectrum of the effective signal according to the threshold value, and record the FFT index of all the power greater than the threshold value to indicate the location of the effective frequency point; Step 5.4, estimate the center frequency of the effective frequency point based on the FFT index data, remove the influence of the sidelobe frequency, and further determine the presence or absence of the effective frequency point signal by comparing the bandwidth occupied by the initially detected effective frequency point with the minimum frequency bandwidth. If there is a signal, the maximum amplitude point of the bandwidth occupied by the effective frequency point is considered to be the center frequency; if there is no signal, the effective frequency point is filtered out.

6. The method for real-time detection of frequency hopping signals based on FPGA+DSP according to claim 5, characterized in that: The frequency hopping signal detection module described in step 6 performs binarization processing on the signal after preliminary detection, as follows: The original signal spectrum is binarized according to the FFT index of the effective frequency point detected by the detection algorithm to obtain a 0 / 1 data matrix to reduce data storage resources.

7. The method for real-time detection of frequency hopping signals based on FPGA+DSP according to claim 6, characterized in that: The frequency hopping signal detection module described in step 7 marks the connected domain of the binary data matrix, obtains the signal time-frequency information composed of the start time and the start frequency, and completes the screening of non-frequency hopping signals, as follows: Step 7.1: If the pixel values ​​of two adjacent pixels in the image are the same, their pixel regions are considered to be connected. The two pixels are merged together and marked as a connected region. The connected regions are divided into 4-adjacent and 8-adjacent regions according to their positional relationship. Step 7.2: Use the 0 / 1 data matrix composed of the binary spectrum data of each time frame as a time-frequency image of the signal, mark the connected domains of the signals in the time-frequency image, and thus obtain the bandwidth and residence time occupied by each hop signal; Step 7.3: In case of a broken connected domain in the actual signal, a connected domain repair algorithm is used to repair the broken connected domain; Step 7.4: According to the difference between the frequency hopping signal and other signals in terms of time-frequency morphology, the frequency hopping signal is screened out, and the bandwidth, dwell time and frequency hopping set parameter information of the frequency hopping signal are uploaded to the host computer.

8. A frequency hopping signal real-time detection system based on FPGA+DSP, characterized in that: The system is used to implement the real-time detection method of frequency hopping signals based on FPGA+DSP as described in any one of claims 1 to 7, and the system includes a time-frequency analysis module, a data communication module and a frequency hopping signal detection module, wherein: The time-frequency analysis module is used to perform analog-to-digital conversion on the intermediate frequency signal received from the radio frequency end, perform digital down-conversion and double decimation on the digital intermediate frequency signal to reduce the sampling rate and data volume, and perform short-time Fourier transform on the zero intermediate frequency signal in a pipeline processing mode; The data communication module is used for high-speed transmission of spectrum data between FPGA and DSP through SRIO protocol; The frequency hopping signal detection module adopts a frequency hopping signal detection algorithm based on an adaptive dynamic threshold to perform frequency hopping signal detection, performs binarization processing on the detected signal to reduce data storage resources, marks the connected domain of the binary data matrix, obtains the signal time-frequency information composed of the start time and the start frequency, and completes the screening of non-frequency hopping signals based on this.

9. A mobile terminal comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the real-time detection method for frequency hopping signals based on FPGA+DSP as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the real-time detection method for frequency hopping signals based on FPGA+DSP as described in any one of claims 1 to 7 are implemented.

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