Image split acquisition and transmission circuit

Abstract

The utility model discloses an image split acquisition and transmission circuit, belongs to the technical field of image acquisition, and solves the problems that low-definition and low-memory image transmission is still carried out in a wireless communication mode, and once high-definition and large-memory image transmission is carried out, the image is more easily interfered by noise signals, and the image transmission efficiency is low. And loss is easy to occur in the transmission process. Comprising a plurality of image sensors, the plurality of image sensors are distributed in an array mode, images collected by the image sensors are different, and the image sensors are used for collecting the images and outputting image signals; the utility model provides a multiplexer. According to the image split acquisition and transmission circuit, the array image sensor, the multiplexer, the master control module and the wireless module are utilized to realize efficient acquisition and stable wireless transmission of images, the reading circuit is matched to ensure accurate digitalization of signals, the process is optimized to maintain high-definition image quality, and distortion is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of image acquisition, in particular to an image split acquisition and transmission circuit. Background Art

[0002] Image acquisition circuit is a special electronic system responsible for converting optical images into electrical signals for further processing and analysis. It usually consists of an image sensor, an analog signal processing unit, an analog-to-digital converter (ADC), a digital signal processing unit, and an interface circuit. The image sensor, such as CCD or CMOS type, is the core of the circuit, which captures the light signal of the scene and converts it into an analog image signal. The analog signal processing unit includes amplifiers and filters to optimize the signal quality. The analog-to-digital converter converts the analog signal into a digital format for the digital signal processing unit to perform operations such as denoising, sharpening, and color correction. The digital signal processing unit may include a microcontroller or FPGA, which is responsible for executing complex image processing algorithms. Finally, the interface circuit, such as USB or Ethernet, transmits the processed image data to other devices or storage media. Image acquisition circuits are widely used in security monitoring, medical imaging, industrial detection, scientific research and exploration, and are essential for realizing automated and intelligent visual systems.

[0003] At present, the main method for transmitting images after acquisition is wireless communication. However, wireless communication is only suitable for transmitting low-definition and low-memory images. However, once high-definition and large-memory images are transmitted, the image will be more susceptible to interference from noise signals and is also prone to loss during the transmission process, ultimately causing the received image to be distorted and blurred.

[0004] Therefore, an image split acquisition and transmission circuit is proposed to solve or alleviate the above problems. Utility Model Content

[0005] The utility model aims to solve the shortcomings in the prior art and proposes an image split acquisition and transmission circuit.

[0006] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0007] An image split acquisition and transmission circuit, comprising:

[0008] Image sensors, the number of the image sensors is several, the image sensors are arranged in a distributed array, and the images collected by the image sensors are different, and the image sensors are used to collect images and output image signals;

[0009] A multiplexer, wherein the number of input terminals of the multiplexer is greater than or equal to the number of image sensors, and the multiplexer receives a plurality of image signals for transmission or merging;

[0010] A main control module, whose input end is coupled to the output end of the multiplexer, and the main control module receives and processes the image signal from the multiplexer;

[0011] A wireless communication module is coupled to the main control module, and the wireless communication module enables the main control module to communicate with the outside world remotely.

[0012] Preferably, it further comprises a data register, which is coupled to the main control module and is used to receive the image signal processed by the main control module.

[0013] Preferably, the multiplexer is a 74HC156 dual 2-4 line demultiplexer.

[0014] Preferably, the main control module is an FPGA chip, and the wireless communication module is an esp8266wifi module.

[0015] Preferably, the image sensor includes a pixel array, a plurality of readout circuits, and a control circuit, the pixel array includes a plurality of pixel units distributed in a rectangular array, each of the readout circuits is respectively connected to a plurality of pixel units arranged in a column, and each of the readout circuits is also respectively connected to the control circuit.

[0016] Preferably, the readout circuit includes a ramp generator, a voltage comparison circuit, a counter circuit, and a negation control circuit;

[0017] The ramp generator outputs a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively; the first input terminal of the voltage comparison circuit is connected to the pixel unit; the second input terminal of the voltage comparison circuit is connected to the ramp generator; the counter circuit is connected to the comparison circuit; the counter circuit counts and stores digital code values; the inversion control circuit is connected to the counter circuit; and between the first quantization time period and the second quantization time period, the inversion control signal is outputted by the mode selection signal.

[0018] Preferably, the voltage comparison circuit is a voltage comparator, the counter circuit is a reversible counter, and the inversion control circuit can adopt a signal source.

[0019] The utility model has the following beneficial effects:

[0020] The image split acquisition and transmission circuit of the utility model utilizes array image sensors, multiplexers, main control modules and wireless modules to realize efficient image acquisition and stable wireless transmission, cooperates with the readout circuit to ensure accurate signal digitization, optimizes the process to maintain high-definition image quality and reduce distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a structural block diagram of the utility model;

[0023] Figure 2 It is a structural block diagram of the image sensor in the utility model;

[0024] Figure 3 It is a wiring diagram of the pixel array in the utility model;

[0025] Figure 4 It is a structural block diagram of the readout circuit in the utility model;

[0026] Figure 5 This is the wiring diagram of the multiplexer in the utility model.

[0027] 1. Image sensor; 101. Pixel array; 102. Readout circuit; 1021. Ramp generator; 1022. Voltage comparison circuit; 1023. Counter circuit; 1024. Inversion control circuit; 103. Control circuit; 2. Multiplexer; 3. Main control module; 4. Data register; 5. Wireless communication module. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0031] In the description of the present utility model, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the utility model product is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present utility model.

[0032] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0033] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] An image split acquisition and transmission circuit, such as Figure 1 As shown, it includes an image sensor 1, a multiplexer 2, a main control module 3, a wireless communication module 5, and a data register 4. Figure 5 As shown, the multiplexer 2 is a 74HC156 dual 2-4 line demultiplexer, the main control module 3 is an FPGA chip, and the wireless communication module 5 is an esp8266 wi fi module.

[0035] The number of image sensors 1 is several, and the several image sensors 1 are arranged in an array distribution, and the images collected by each image sensor 1 are different. The image sensor 1 is used to collect images and output image signals. The number of input ends of the multiplexer 2 is greater than or equal to the number of image sensors 1. The multiplexer 2 receives several image signals for transmission or merging. The input end of the main control module 3 is coupled to the output end of the multiplexer 2. The main control module 3 receives and processes the image signal from the multiplexer 2. The wireless communication module 5 is coupled to the main control module 3. The wireless communication module 5 realizes external remote communication interaction of the main control module 3. The data register 4 is coupled to the main control module 3. The data register 4 is used to receive the image signal processed by the main control module 3.

[0036] like Figure 2 As shown, the image sensor 1 includes a pixel array 101, a plurality of readout circuits 102, and a control circuit 103. Figure 3 As shown, the pixel array 101 includes a plurality of pixel units distributed in a rectangular array, each readout circuit 102 is respectively connected to a plurality of pixel units arranged in a column, and each readout circuit 102 is also respectively connected to a control circuit 103 .

[0037] like Figure 4 As shown, the readout circuit 102 includes a ramp generator 1021, a voltage comparison circuit 1022, a counter circuit 1023, and an inversion control circuit 1024. The voltage comparison circuit 1022 is a voltage comparator, the counter circuit 1023 is a reversible counter, and the inversion control circuit 1024 can use a signal source.

[0038] The ramp generator 1021 outputs a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit, respectively. The first input terminal of the voltage comparison circuit 1022 is connected to the pixel unit, and the second input terminal of the voltage comparison circuit 1022 is connected to the ramp generator 1021. The voltage comparison circuit 1022 compares the reset signal or the pixel signal output by the pixel unit with the ramp voltage signal, and outputs a reset pulse signal or a pixel pulse signal. The counter circuit 1023 is connected to the comparison circuit, and counts the first pulse signal in the first quantization time period and stores the first digital code value; in the second quantization time period, the counter circuit 1023 counts the second pulse signal based on the second digital code value and stores it as a third digital code value. The first pulse signal and the second pulse signal are reset pulse signals and pixel pulse signals to each other. The inversion control circuit 1024 is connected to the counter circuit 1023, and between the first quantization time period and the second quantization time period, the inversion control signal is triggered by the mode selection signal to output the inversion control signal, so that the counter circuit 1023 is triggered by the inversion control signal to invert the first digital code value to the second digital code value and store it.

[0039] The readout circuit 102 of the above-mentioned image sensor 1 is connected by a ramp generator 1021, a voltage comparison circuit 1022, a counter circuit 1023 and an inversion control circuit 1024. When switching the count, the inversion control circuit 1024 is set to control the counter circuit 1023 to invert the first digital code value into a second digital code value, so that in the second quantization time period, the counter circuit 1023 counts the third digital code value based on the second digital code value, thereby realizing correlated double sampling, eliminating fixed pattern noise, and improving imaging quality. In addition, in the readout circuit 102, there is no need to set a buffer and an additional holding circuit, which simplifies the circuit structure, reduces power consumption, and ensures that the counter circuit 1023 operates in a high-frequency counting mode.

[0040] The image split acquisition and transmission circuit in the utility model realizes efficient image acquisition and wireless transmission through a series of components. First, multiple image sensors 1 are distributed in an array, each independently acquires images and outputs image signals. These image signals are sent to a multiplexer 2, such as 74HC156, to transmit or merge image signals according to the needs of the main control module 3. Subsequently, the main control module 3, preferably an FPGA chip, receives the output of the multiplexer 2 and performs image processing tasks. The processed image signal is temporarily stored in the data register 4, ready for wireless transmission. The wireless communication module 5, such as the ESP8266 Wi-Fi module, is coupled to the main control module 3 and is responsible for remote communication transmission of the image signal. In this process, the readout circuit 102 of each image sensor 1, including a ramp generator 1021, a voltage comparison circuit 1022, a counter circuit 1023 and an inversion control circuit 1024, works together to ensure accurate reading and digitization of the image signal. The entire system is designed to achieve stable transmission of high-definition images by optimizing image acquisition and processing processes and utilizing wireless communication technology, maintaining image quality and reducing distortion and blur even in complex environments.

[0041] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. An image split acquisition and transmission circuit, characterized in that: include An image sensor (1), wherein the number of the image sensors (1) is a plurality, the plurality of image sensors (1) are arranged in an array, and the images collected by each of the image sensors (1) are different, and the image sensor (1) is used to collect images and output image signals; A multiplexer (2), the number of input terminals of the multiplexer (2) being greater than or equal to the number of image sensors (1), and the multiplexer (2) receiving a plurality of image signals for transmission or merging; A main control module (3), whose input end is coupled to the output end of the multiplexer (2), and the main control module (3) receives and processes the image signal from the multiplexer (2); A wireless communication module (5), the wireless communication module (5) is coupled to the main control module (3), and the wireless communication module (5) enables the main control module (3) to interact with external remote communications.

2. The image split acquisition and transmission circuit according to claim 1, characterized in that: It also comprises a data temporary register (4), the data temporary register (4) being coupled to the main control module (3), and the data temporary register (4) being used to receive the image signal processed by the main control module (3).

3. The image split acquisition and transmission circuit according to claim 1, characterized in that: The multiplexer (2) is a 74HC156 dual 2-4 line demultiplexer.

4. The image split acquisition and transmission circuit according to claim 1, characterized in that: The main control module (3) is an FPGA chip, and the wireless communication module (5) is an esp8266wifi module.

5. The image split acquisition and transmission circuit according to claim 1, characterized in that: The image sensor (1) comprises a pixel array (101), a plurality of readout circuits (102), and a control circuit (103); the pixel array (101) comprises a plurality of pixel units distributed in a rectangular array; each of the readout circuits (102) is respectively connected to a plurality of pixel units arranged in a column; and each of the readout circuits (102) is also respectively connected to the control circuit (103).

6. The image split acquisition and transmission circuit according to claim 5, characterized in that: The readout circuit (102) comprises a ramp generator (1021), a voltage comparison circuit (1022), a counter circuit (1023), and an inversion control circuit (1024); The ramp generator (1021) outputs a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively; a first input terminal of the voltage comparison circuit (1022) is connected to the pixel unit; a second input terminal of the voltage comparison circuit (1022) is connected to the ramp generator (1021); the counter circuit (1023) is connected to the comparison circuit; the counter circuit (1023) counts and stores digital code values; the inversion control circuit (1024) is connected to the counter circuit (1023) and outputs an inversion control signal triggered by a mode selection signal between the first quantization time period and the second quantization time period.

7. The image split acquisition and transmission circuit according to claim 6, characterized in that: The voltage comparison circuit (1022) is a voltage comparator, the counter circuit (1023) is a reversible counter, and the inversion control circuit (1024) can adopt a signal source.

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