Solar cell

Abstract

The present application relates to a solar cell comprising: a semiconductor substrate having a first conductivity type; the first cell structure comprises a tunneling dielectric layer and a doped polycrystalline silicon layer, the tunneling dielectric layer is located on the backlight surface of the semiconductor substrate, and the doped polycrystalline silicon layer has a first conduction type; the first passivation structure is positioned on the surface of the doped polycrystalline silicon layer and covers the first side surface of the first battery structure; the second cell structure comprises an intrinsic amorphous silicon layer, a second conductive type doping layer and a transparent conductive film layer which are arranged in sequence, and the second cell structure extends to the partial surface, away from the first cell structure, of the first passivation structure from the backlight surface of the semiconductor substrate along the second side face of the first cell structure, the second side surface is opposite to the first side surface; the first grid line penetrates through the first passivation structure and extends to the doped polycrystalline silicon layer; the second grid line is located on the surface, away from the second conductive type doping layer, of the transparent conductive film layer. The performance of the solar cell can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell. Background Art

[0002] At present, solar cells, a new energy technology, are experiencing an unprecedented development trend. Among them, crystalline silicon solar cells have been dominating the photovoltaic industry with a market share of more than 90%. With such a huge volume and broad market prospects, crystalline silicon solar cells are also developing continuously.

[0003] However, the performance of existing solar cells needs to be further improved. Utility Model Content

[0004] Based on this, it is necessary to provide a solar cell with further improved performance in order to solve the above technical problems.

[0005] A solar cell, comprising:

[0006] The semiconductor substrate has a first conductivity type and is provided with a light incident surface and a light-receiving surface that are oppositely arranged;

[0007] A first cell structure includes a tunnel dielectric layer and a doped polysilicon layer, wherein the tunnel dielectric layer is located on the backlight surface of the semiconductor substrate, and the doped polysilicon layer has the first conductivity type and is located on the surface of the tunnel dielectric layer away from the semiconductor substrate;

[0008] A first passivation structure is located on a surface of the doped polysilicon layer away from the tunnel dielectric layer and covers a first side surface of the first battery structure;

[0009] A second battery structure, comprising an intrinsic amorphous silicon layer, a second conductive type doped layer and a transparent conductive film layer arranged in sequence from close to the semiconductor substrate to far away from the semiconductor substrate, and the second battery structure extends from the backlight surface of the semiconductor substrate along the second side surface of the first battery structure to a portion of the surface of the first passivation structure away from the first battery structure, the second side surface is arranged opposite to the first side surface, and one of the second conductive type and the first conductive type is P type, and the other is N type;

[0010] A first gate line, passing through the first passivation structure and extending to the doped polysilicon layer;

[0011] The second gate line is located on a surface of the transparent conductive film layer away from the second conductive type doped layer.

[0012] In one embodiment, the first battery structure further includes:

[0013] An isolation layer is located between the doped polysilicon layer and the second conductive type doped layer.

[0014] In one embodiment, the isolation layer includes an intrinsic polysilicon layer.

[0015] In one embodiment, the solar cell further comprises:

[0016] The second passivation structure covers the light incident surface of the semiconductor substrate.

[0017] In one embodiment, the first passivation structure and the second passivation structure have the same film layer structure, and both include a passivation layer and an anti-reflection layer.

[0018] In one embodiment, the material of the passivation layer includes hydrogenated aluminum oxide, and the material of the anti-reflection layer includes hydrogenated silicon nitride.

[0019] In one embodiment, the portion of the backlight surface of the semiconductor substrate in contact with the intrinsic amorphous silicon layer is a textured surface.

[0020] In one embodiment, the solar cell further includes an isolation trench, wherein the isolation trench penetrates and extends to a portion of the second cell structure on the surface of the first passivation structure.

[0021] In one embodiment, the second conductive type doped layer includes a hydrogenated microcrystalline silicon layer, a microcrystalline silicon oxide layer, or a microcrystalline silicon oxycarbide layer.

[0022] In one of the embodiments, the semiconductor substrate comprises an N-type silicon substrate.

[0023] In the above-mentioned solar cell, the first grid line and the second grid line are arranged on the back of the solar cell. At this time, the front of the cell for receiving light is completely free of grid lines, so that the light incident on the cell is fully absorbed, thereby improving the light utilization rate of the cell. At the same time, on the back of the solar cell, the dangling bonds on the surface of the semiconductor substrate 100 can be chemically passivated by the tunneling dielectric layer of the first cell structure and the intrinsic amorphous silicon layer of the second cell structure, greatly reducing the interface recombination on the surface of the semiconductor substrate. In addition, field passivation can be formed by the doped polysilicon layer of the first cell structure, thereby further reducing the recombination of photogenerated carriers. At the same time, the first passivation structure can perform good passivation on both the back and side of the first cell structure, thereby further improving the cell performance.

[0024] Moreover, the solar cells in some embodiments of the present application can also improve some technical problems of traditional BC cells. For example, the traditional TBC cell has a concentric circle effect caused by boron doping. In some embodiments of the present application, the first conductivity type can be N-type, and the doped polysilicon layer can be only phosphorus-doped without boron doping, thereby solving the concentric circle problem of the traditional TBC cell. For another example, in the traditional HBC cell, the structure of phosphorus-doped hydrogenated microcrystalline silicon is easily damaged by laser, while the second conductivity type doped layer of the present application can adopt a boron-doped hydrogenated microcrystalline silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 is a schematic diagram of a cross-sectional structure of a solar cell in one embodiment of the present application;

[0027] Figures 2 to 7 It is a schematic diagram of the cross-sectional structure of a solar cell during the preparation process in one embodiment of the present application.

[0028] Description of reference numerals:

[0029] 100-semiconductor substrate, 200-first battery structure, 210-tunneling dielectric layer, 2101-ultra-thin oxide layer, 220-doped polysilicon layer, 2201-doped polysilicon material layer, 230-intrinsic polysilicon layer, 2301-intrinsic polysilicon material layer, 310-first passivation structure, 320-second passivation structure, 301-passivation layer, 3011-passivation material layer, 302-anti-reflection layer, 3021-anti-reflection material layer, 400-second battery structure, 410-intrinsic amorphous silicon layer, 420-second conductive type doped layer, 430-transparent conductive film layer, 500-first gate line, 600-second gate line, 10-first side surface, 20-second side surface, 30-isolation groove. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0033] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be intervening layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. In addition, the same reference numerals always represent the same elements.

[0034] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements placed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or directly, but also through another layer, region, element, etc. placed therebetween.

[0035] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0036] When a statement such as "at least one (of)..." is located after a list of elements, it modifies the entire list of elements rather than the individual elements in the list. The term "and / or" as used herein includes any and all combinations of one or more related listed items. As used in the application documents, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0037] In one embodiment, see Figure 1 , a solar cell is provided, including a semiconductor substrate 100 , a first cell structure 200 , a first passivation structure 310 , a second cell structure 400 , a first gate line 500 , and a second gate line 600 .

[0038] The semiconductor substrate 100 has a first conductivity type. The first conductivity type may be an N-type or a P-type. As an example, the semiconductor substrate 100 may include an N-type silicon substrate. Meanwhile, the semiconductor substrate 100 is provided with a light incident surface and a backlight surface arranged opposite to each other. The light incident surface may be used to receive light.

[0039] The first cell structure 200 includes a tunnel dielectric layer 210 and a doped polysilicon layer 220 .

[0040] The tunnel dielectric layer 210 is located on the backlight surface of the semiconductor substrate 100, and its material may be, for example, a tunnel oxide layer. Meanwhile, the thickness of the tunnel dielectric layer 210 may be, for example, 1.3 nm to 1.6 nm.

[0041] The doped polysilicon layer 220 is located on the surface of the tunnel dielectric layer 210 away from the semiconductor substrate 100. The doped polysilicon layer has a first conductivity type, and thus has the same conductivity type as the semiconductor substrate 100. When the first conductivity type is N-type, the material of the doped polysilicon layer may be, for example, phosphorus-doped polysilicon.

[0042] As an example, the process of forming the first cell structure 200 on the backlight surface of the semiconductor substrate 100 may be as follows:

[0043] First, the semiconductor substrate 100 is pre-cleaned. Then, a 300nm-500nm blocking sacrificial layer is plated on the backlight surface of the cleaned semiconductor substrate 100. The material of the blocking sacrificial layer can be, for example, silicon nitride. After that, the semiconductor substrate 100 with the blocking sacrificial layer plated on the backlight surface is cleaned again. Next, the light incident surface of the semiconductor substrate 100 is textured using the blocking sacrificial layer as a barrier, so as to texture the light incident surface on one side to form a textured surface of uniform size. Then, the organic matter and metal ions on the textured surface of the light incident surface are cleaned by a cleaning solution (such as RCA-1 and RCA-2). Then the pyramid structure of the smooth surface is formed. Finally, hydrofluoric acid can be used to remove the oxide layer on the textured surface and the blocking sacrificial layer on the backlight surface.

[0044] Then, see Figure 2 A double-sided ultra-thin oxide layer 2101 can be prepared on the light incident surface and the backlight surface of the semiconductor substrate 100 using a thermal oxidation method. The thickness of the ultra-thin oxide layer 2101 can be approximately 1.3 nm-1.6 nm.

[0045] Afterwards, a whole intrinsic polysilicon material layer 2301 may be deposited on the ultra-thin oxide layer 2101 on the backlight surface by low pressure chemical vapor deposition (LPCVD) or the like. The thickness of the intrinsic polysilicon material layer 2301 may be about 100nm-500nm. Next, the intrinsic polysilicon material layer 2301 may be doped and annealed by laser to form a doped polysilicon material layer 2201. When the annealing process is performed, the annealing temperature may be 850°C-950°C, for example, 900°C. The annealing time may be 25 minutes-35 minutes, for example, 30 minutes.

[0046] Afterwards, see Figure 3 , a groove can be formed through the doped polysilicon material layer 2201 (or the intrinsic polysilicon material layer 2301) and the ultra-thin silicon oxide that penetrates the backlight surface of the semiconductor substrate 100, thereby exposing the backlight surface of the semiconductor substrate 100 located on at least one side of the first battery structure 200. It can be understood that a plurality of periodically repeated solar cell structural units can be formed on the same semiconductor substrate 100. Figure 1-Figure 7 Only one structural unit of a solar cell is shown.

[0047] As an example, the grooving may be performed by laser, and after the grooving, KOH or the like may be used to eliminate the laser cutting damage caused by the laser grooving.

[0048] After the grooves are formed, the remaining ultra-thin oxide layer 2101 on the backlight surface forms a tunnel dielectric layer 210, and the remaining doped polysilicon material layer 2201 forms a doped polysilicon layer 220. The remaining ultra-thin oxide layer 2101 on the light incident surface can be retained or removed, which is not limited here.

[0049] Please continue reading Figure 1 The first passivation structure 310 is located on the surface of the doped polysilicon away from the tunnel dielectric layer 210 and covers the first side surface 10 of the first battery structure 200, so that the first battery structure 200 can be well passivated. The first passivation structure 310 can be a multi-layer structure. Of course, it can also be a single-layer structure, which is not limited here.

[0050] As an example, the preparation process of the first passivation structure 310 may be:

[0051] Through the deposition process, the first structural material layer is deposited on the entire surface of the structure on the backlight surface side of the semiconductor substrate 100 after the first battery structure 200 is formed. The first structural material layer can be a multi-layer film layer or a single-layer film layer. Then, an opening can be made in the first passivation material layer 3011 by laser opening or the like, thereby forming the first passivation structure 310.

[0052] The second battery structure 400 includes an intrinsic amorphous silicon layer 410, a second conductive type doped layer 420, and a transparent conductive film layer 430. The intrinsic amorphous silicon layer 410, the second conductive type doped layer 420, and the transparent conductive film layer 430 are sequentially arranged in a direction from close to the semiconductor substrate 100 to far away from the semiconductor substrate 100. One of the second conductive type and the first conductive type is P type, and the other is N type.

[0053] At the same time, the second battery structure 400 (including the intrinsic amorphous silicon layer 410, the second conductive type doped layer 420 and the transparent conductive film layer 430) extends from the backlight surface of the semiconductor substrate 100 along the second side surface 20 of the first battery structure 200 to the surface of the first passivation structure 310 away from the first battery structure 200. The second side surface 20 is arranged opposite to the first side surface 10.

[0054] At this time, the second cell structure 400 covers the backlight surface of the semiconductor substrate 100 exposed by the opening in the first passivation structure 310, and completely covers the second side surface 20 of the first cell structure 200. The intrinsic amorphous silicon layer 410 of the second cell structure 400 can perform passivation isolation between the second cell structure 400 and the first cell structure 200.

[0055] As an example, see Figure 6 , the formation process of the second battery structure 400 may be:

[0056] The intrinsic amorphous silicon layer 410 is deposited by using a deposition process such as plasma enhanced chemical vapor deposition (PECVD) or hot filament chemical vapor deposition (HWCVD). The intrinsic amorphous silicon layer 410 may be a single layer or a stacked layer intrinsic amorphous silicon structure.

[0057] Subsequently, a second conductive type doping layer 420 may be deposited on the intrinsic amorphous silicon layer 410 using a deposition process such as PECVD or HWCVD. The second conductive type doping layer 420 may include a hydrogenated microcrystalline silicon layer, a microcrystalline silicon oxide layer (μc-SiOx:H layer) or a microcrystalline carbon oxide silicon layer (μc-SiCxOy:H layer), etc. When the second conductive type is P-type, the second conductive type doping layer 420 may include a boron-doped microcrystalline carbon oxide silicon layer or a boron-doped microcrystalline silicon oxide layer or a boron-doped hydrogenated microcrystalline silicon layer or a boron-doped amorphous silicon layer, etc. Among them, the microcrystalline carbon oxide silicon layer may be a structural film layer formed by doping carbon dioxide in a microcrystalline silicon oxide layer.

[0058] Next, a transparent conductive film layer 430 may be deposited on the second conductive type doped layer 420 (such as a boron-doped microcrystalline silicon oxide layer) at low temperature by using a deposition method such as active plasma deposition (RPD). The transparent conductive film layer 430 may include, but is not limited to, a transparent conductive oxide film doped with a transition metal based on an indium oxide main material. For example, the transparent conductive film layer 430 may include, but is not limited to, indium oxide doped with tungsten, cerium, molybdenum, zirconium, titanium, hafnium, zinc, and manganese.

[0059] It is understandable that, since the first battery structure 200 and the first passivation structure 310 have been stacked and formed on part of the backlight surface of the semiconductor substrate 100 before the second battery structure 400 is formed, there is a height difference between the remaining exposed backlight surface of the semiconductor substrate 100 and the exposed surface of the first passivation structure 310. Therefore, when the intrinsic amorphous silicon layer 410, the second conductive type doped layer 420 and the transparent conductive film layer 430 are sequentially deposited by the RPD method to form the second battery structure 400, the amount of the second battery structure 400 falling on the surface of the first passivation structure 310 away from the opening in the first passivation structure 310 is very small or almost non-existent. Therefore, the second battery structure 400 can also be formed by the whole surface deposition method. Figure 6 The second battery structure 400 is shown in the structural form. Of course, the formation method of the second battery structure 400 is not limited to this.

[0060] The first gate line 500 penetrates the first passivation structure 310 and extends to the doped polysilicon layer 220 .

[0061] As an example, when forming the first gate line 500, a photoresist (such as a positive photoresist) can be firstly spin-coated. Then, the photoresist is exposed and developed by a photolithography machine to form a patterned photoresist with an opening. Afterwards, the first passivation structure 310 is etched based on the patterned photoresist to form an electrode opening. Then, a first conductive material layer can be formed in the electrode opening and on the surface of the patterned photoresist by evaporation or the like. The material of the first conductive material layer can be protected but not limited to a metal material (such as metal aluminum). Afterwards, the patterned photoresist can be removed by a degumming solution such as an ultrasonic instrument and an acetone wet method, and the redundant first conductive material layer can be peeled off. The remaining first conductive material layer forms the first gate line 500 in contact with the doped polysilicon layer 220.

[0062] The second gate line 600 is located on a surface of the transparent conductive film layer 430 away from the second conductive type doped layer 420 .

[0063] As an example, when forming the second gate line 600, the second gate line 600 in contact with the transparent conductive film layer 430 may be formed by copper electroplating, evaporation, screen printing, steel plate printing, laser transfer, etc. on the transparent conductive film layer 430. The material of the second gate line may include but is not limited to a metal material (such as metallic silver).

[0064] In this embodiment, the first grid line 500 and the second grid line 600 are arranged on the back of the solar cell. At this time, the front of the cell for receiving light is completely shielded by no grid lines, so that the light incident on the cell is fully absorbed, improving the light utilization rate of the cell.

[0065] At the same time, on the back side of the solar cell, the dangling bonds on the surface of the semiconductor substrate 100 can be chemically passivated by the tunneling dielectric layer 210 of the first cell structure 200 and the intrinsic amorphous silicon layer 410 of the second cell structure 400, which greatly reduces the interface recombination on the surface of the semiconductor substrate 100. In addition, field passivation can be formed by the doped polysilicon layer 220 of the first cell structure 200, thereby further reducing the recombination of photogenerated carriers. At the same time, the first passivation structure 310 can perform good passivation on both the back side and the side of the first cell structure 200, thereby further improving the cell performance.

[0066] Moreover, the solar cells in some embodiments of the present application can also improve some technical problems of traditional BC cells. For example, the traditional TBC cell has a concentric circle effect caused by boron doping. In some embodiments of the present application, the first conductivity type can be N-type, and the doped polysilicon layer 220 can be only phosphorus-doped without boron doping, thereby solving the concentric circle problem of the traditional TBC cell. For another example, in the traditional HBC cell, the structure of phosphorus-doped hydrogenated microcrystalline silicon is easily damaged by laser, while the second conductivity type doping layer 420 of the present application can adopt a boron-doped hydrogenated microcrystalline silicon layer.

[0067] In one embodiment, the first battery structure 200 further includes an isolation layer. The isolation layer is located between the doped polysilicon layer 220 and the second conductive type doped layer 420, so as to better isolate the two and effectively isolate the electron and hole collection areas.

[0068] In one embodiment, please refer to Figure 1 , the isolation layer may include an intrinsic polysilicon layer 230 .

[0069] At this time, see Figure 2 In the process of forming the first battery structure 200, after forming an intrinsic polysilicon material layer 2301 on the ultra-thin silicon oxide on the backlight surface of the semiconductor substrate 100, when doping the intrinsic polysilicon material layer 2301, the intrinsic polysilicon material layer 2301 can be locally doped. After doping, the intrinsic polysilicon material layer 2301 and the doped polysilicon material layer 2201 can be arranged alternately. Figure 3 When laser grooving is performed to expose the backlight surface of the semiconductor substrate 100 located on at least one side of the first battery structure 200, laser grooving can be performed on a portion of the doped polysilicon material layer 2201, and / or laser grooving can be performed on a portion of the intrinsic polysilicon material layer 2301.

[0070] At this time, an isolation layer (intrinsic polysilicon layer 230 ) may be simply and effectively formed between the doped polysilicon layer 220 and the second conductive type doped layer 420 .

[0071] Of course, in other embodiments, the material and formation method of the isolation layer are not limited thereto.

[0072] In one embodiment, see Figure 1 The solar cell further includes a second passivation structure 320. The second passivation structure 320 covers the light incident surface of the semiconductor substrate 100, thereby effectively passivating the light incident surface.

[0073] As an example, the second passivation structure 320 may be formed simultaneously with the first passivation structure 310 , so as to have the same film structure. Meanwhile, the second passivation structure 320 and the first passivation structure 310 may both include a passivation layer 301 and an anti-reflection layer 302 .

[0074] At this point in the solar cell preparation process, please refer to Figure 4 , a passivation material layer 3011 with a thickness of 6 nm to 10 nm can be deposited simultaneously on the light incident surface side and the backlight surface side of the semiconductor substrate 100 by atomic layer deposition (ALD) or the like. Then, an anti-reflection material layer 3021 with a thickness of 80 nm to 110 nm can be formed on the surface of the passivation layer 301 on both sides of the semiconductor substrate 100 by tube plasma enhanced chemical vapor deposition (PECVD) or the like.

[0075] Next, see Figure 5 , a laser can be used to remove the local anti-reflection material layer 3021 and the passivation material layer 3011 located on the backlight surface of the semiconductor substrate 100, thereby forming an opening. The remaining anti-reflection material layer 3021 after the laser opening forms the anti-reflection layer 302, and the remaining passivation material layer 3011 forms the passivation layer 301. The passivation layer 301 and the anti-reflection layer 302 located on the backlight surface side of the semiconductor substrate 100 form a first passivation structure 310, and the passivation layer 301 and the anti-reflection layer 302 located on the light incident surface side of the semiconductor substrate 100 form a second passivation structure 320. Among them, the material of the passivation layer 301 can include but is not limited to hydrogenated aluminum oxide, and the material of the anti-reflection layer 302 can include but is not limited to hydrogenated silicon nitride.

[0076] Afterwards, KOH may be used to remove laser cutting damage from the laser-opened area. Finally, the semiconductor substrate 100 after the first passivation structure 310 and the second passivation structure 320 are formed is cleaned again.

[0077] At this time, the passivation layer 301 can effectively passivate both sides of the semiconductor substrate 100. At the same time, the anti-reflection layer 302 located in the second passivation structure 320 can improve the light absorption rate. In addition, the first passivation structure 310 and the second passivation structure 320 can be formed at the same time, thereby simplifying the battery manufacturing process.

[0078] Of course, the second passivation structure 320 and the first passivation structure 310 may also be formed asynchronously, and the film structures of the two may also be different, which is not limited here.

[0079] In one embodiment, see Figure 1 The portion of the backlight surface of the semiconductor substrate 100 that contacts the intrinsic amorphous silicon layer 410 is a textured surface.

[0080] At this time, see Figure 5 After forming the first passivation structure 310 and before forming the second battery structure 400, the backlight surface of the semiconductor substrate 100 exposed by the first passivation structure 310 may be textured first, so that the backlight surface of the semiconductor substrate 100 forms a textured surface. The textured surface is in contact with the intrinsic amorphous silicon layer 410 of the second battery structure 400 formed subsequently.

[0081] As an example, see Figure 4 as well as Figure 5 After the first passivation structure 310 including the passivation layer 301 and the anti-reflection layer 302 is formed simultaneously, a cleaning sacrificial material layer with a thickness of 50nm to 60nm can be formed on the surface of the anti-reflection material layer 3021 on both sides of the semiconductor substrate 100. The material of the cleaning sacrificial material layer can be the same as that of the anti-reflection material layer 3021, or they can be different.

[0082] At this time, before subsequently using laser to open the anti-reflection material layer 3021 and the passivation material layer 3011, the sacrificial material layer may be opened first.

[0083] Then, KOH is used to remove the laser cutting damage, and after the semiconductor substrate 100 is cleaned again, local texturing can be performed at the laser opening to form a uniformly textured surface on its surface. Then, the organic matter and metal ions on the textured surface are cleaned by a cleaning liquid (such as RCA-1 and RCA-2). After cleaning, the 50nm-60nm excess cleaning sacrificial layer can be basically removed, and then the pyramid structure of the smooth surface is formed.

[0084] In one embodiment, see Figure 1 The solar cell further includes an isolation trench 30 . The isolation trench 30 penetrates a portion of the second cell structure 400 extending to the surface of the first passivation structure 310 .

[0085] At this time, see Figure 6 as well as Figure 7 After forming the second battery structure 400 (including the intrinsic amorphous silicon layer 410 , the second conductive type doped layer 420 and the transparent conductive film layer 430 ), the portion of the second battery structure 400 extending to the surface of the first passivation structure 310 may be laser grooved to form the isolation trench 30 .

[0086] In this embodiment, the isolation trench 30 can effectively prevent the two first gate lines 500 from being short-circuited with the second gate line 600, thereby ensuring the battery performance.

[0087] In the description of this specification, the description with reference to the terms "one embodiment", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0088] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: The semiconductor substrate has a first conductivity type and is provided with a light incident surface and a light-receiving surface that are oppositely arranged; A first cell structure includes a tunnel dielectric layer and a doped polysilicon layer, wherein the tunnel dielectric layer is located on the backlight surface of the semiconductor substrate, and the doped polysilicon layer has the first conductivity type and is located on the surface of the tunnel dielectric layer away from the semiconductor substrate; A first passivation structure is located on a surface of the doped polysilicon layer away from the tunnel dielectric layer and covers a first side surface of the first battery structure; A second battery structure, comprising an intrinsic amorphous silicon layer, a second conductive type doped layer and a transparent conductive film layer arranged in sequence from close to the semiconductor substrate to far away from the semiconductor substrate, and the second battery structure extends from the backlight surface of the semiconductor substrate along the second side surface of the first battery structure to a portion of the surface of the first passivation structure away from the first battery structure, the second side surface is arranged opposite to the first side surface, and one of the second conductive type and the first conductive type is P type, and the other is N type; A first gate line, passing through the first passivation structure and extending to the doped polysilicon layer; The second gate line is located on a surface of the transparent conductive film layer away from the second conductive type doped layer.

2. The solar cell according to claim 1, characterized in that The first battery structure further comprises: An isolation layer is located between the doped polysilicon layer and the second conductive type doped layer.

3. The solar cell according to claim 2, characterized in that: The isolation layer includes an intrinsic polysilicon layer.

4. The solar cell according to claim 1, characterized in that The solar cell further comprises: The second passivation structure covers the light incident surface of the semiconductor substrate.

5. The solar cell according to claim 4, characterized in that: The first passivation structure and the second passivation structure have the same film layer structure, and both include a passivation layer and an anti-reflection layer.

6. The solar cell according to claim 5, characterized in that The material of the passivation layer includes hydrogenated aluminum oxide, and the material of the anti-reflection layer includes hydrogenated silicon nitride.

7. The solar cell according to claim 1, characterized in that The portion of the backlight surface of the semiconductor substrate in contact with the intrinsic amorphous silicon layer is a textured surface.

8. The solar cell according to claim 1, characterized in that The solar cell further includes an isolation trench, wherein the isolation trench penetrates a portion of the second cell structure extending to a surface of the first passivation structure.

9. The solar cell according to claim 1, characterized in that: The second conductive type doped layer includes a hydrogenated microcrystalline silicon layer, a microcrystalline silicon oxide layer or a microcrystalline silicon oxycarbide layer.

10. The solar cell according to claim 1, characterized in that: The semiconductor substrate comprises an N-type silicon substrate.

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