Semiconductor package

Abstract

The utility model provides a semiconductor packaging piece, which comprises a first electronic component and a second electronic component, a second electronic component directly bonded to the first electronic component, a side surface of the second electronic component and a top surface of the first electronic component defining an accommodating space; the filling material is located in the containing space, the filling material comprises a first gap, the first gap exposes a part of the top surface of the first electronic element and a part of the side surface of the second electronic element, and the width of the first gap is gradually increased in the direction from top to bottom. The utility model aims to provide a semiconductor packaging piece so as to at least enhance the structural stability of the semiconductor packaging piece.

Description

Technical Field

[0001] The utility model relates to a semiconductor package. Background Art

[0002] The packaging development area will develop towards fine line width, and in 3D stacking, it is hoped that the pitch will be reduced to meet more input and output (IO) connections and shorter connection paths. The currently developed hybrid bond is one of the technologies for reducing the pitch when connecting other dies, and how to package the hybrid bond into a terminal chip is the current development focus.

[0003] High-density memory and dynamic random access memory (DRAM) die stacking packaging is an industry trend. After stacking wafers or die integration, subsequent packaging is a key process in the future. However, the integrated solution of packaging and testing (OSAT) faces challenges among the front-end industries. How to package after the hybrid combination of packaging and testing is a key issue.

[0004] See also Figure 1 , the current die 1 to wafer 2 (D2W) bonding includes memory + application-specific integrated circuit (ASIC) chips, DRAM + DRAM, DRAM + logic devices. See Figure 2 The current wafer 2 to wafer 2 (Wafer to Wafer, W2W) bonding includes memory + DRAM, DRAM + DRAM, memory + application-specific integrated circuit (ASIC) chips.

[0005] Figures 3 to 8 The current mass production process of D2W is shown, including: Figure 3 , Die 1 to Wafer 2 (D2W) hybrid bonding; see Figure 4 , performing a chemical vapor deposition (CVD) process to fill the gaps between the tube cores 1 with SiO2 material 4; see Figure 5 , perform a chemical mechanical polishing (CMP) process; see Figure 6 ,Will Figure 5 The structure shown is bonded to a carrier (eg, a glass carrier) 3; see Figure 7 , performing a middle-of-line (MEOL) process [forming an interlayer dielectric (ILD) layer 5 of a polyimide (PI) material using a chemical vapor deposition (CVD) process, and forming a circuit in the ILD layer 5 (ie, forming an RDL)]; see Figure 8, remove the carrier 3, perform a grinding process to expose the tube core 1, and then form a heat dissipation layer 6. The use of multiple front-end processes requires a very high price of equipment, which will increase the overall development cost (for example Figure 4 The CVD process shown, Figure 5 The CMP process shown will increase by approximately US$12M), and if we consider that OSAT fabs must also have the same capabilities, the overall production cost will increase significantly.

[0006] The existing process of stacking a multi-layer structure includes: forming a through substrate via (TSV), a back-end process, and stacking a small outline IC (SOIC). Utility Model Content

[0007] In view of the problems existing in the related art, an object of the present invention is to provide a semiconductor package to at least enhance the structural stability of the semiconductor package.

[0008] To achieve the above-mentioned purpose, the utility model provides a semiconductor package, including: a first electronic component; a second electronic component directly bonded to the first electronic component, the side surface of the second electronic component and the top surface of the first electronic component defining an accommodation space; a filling material located in the accommodation space, wherein the filling material includes a first gap, the first gap exposes a portion of the top surface of the first electronic component and a portion of the side surface of the second electronic component, and the width of the first gap gradually increases from top to bottom.

[0009] In some embodiments, the semiconductor package also includes: a third electronic component, which is arranged side by side with the second electronic component and directly bonded to the first electronic component, the side surface of the third electronic component, the side surface of the second electronic component, and the top surface of the first electronic component together define an accommodating space, and the first gap is closer to the side surface of the second electronic component than to the center axis of the accommodating space.

[0010] In some embodiments, in a cross-sectional view through the first electronic component, the second electronic component, and the third electronic component, the first void has a triangular shape.

[0011] In some embodiments, the semiconductor package further includes: a second gap located at a position where a side surface of the third electronic component and a top surface of the first electronic component intersect.

[0012] In some embodiments, the second gap exposes a portion of a side surface of the third electronic component.

[0013] In some embodiments, the second gap exposes a portion of the top surface of the first electronic component.

[0014] In some embodiments, second gaps exist around the third electronic component.

[0015] In some embodiments, the first gap exists around the second electronic component.

[0016] In some embodiments, the filling material exposes a top surface of the second electronic component.

[0017] In some embodiments, a top surface of the filling material is lower than a top surface of the second electronic component.

[0018] In some embodiments, a top surface of the filling material has a highest height at a location where the second electronic component is connected.

[0019] In some embodiments, an end of the top surface of the filling material connects to an end of the top surface of the second electronic component.

[0020] In some embodiments, an end of the top surface of the filling material includes a curved surface.

[0021] In some embodiments, the curved surface is concave downward.

[0022] In some embodiments, the semiconductor package further comprises:

[0023] The heat dissipation layer is located on the second electronic component and adheres to the top surface of the second electronic component.

[0024] In some embodiments, the heat dissipation layer also conforms to the top surface of the filling material.

[0025] In some embodiments, the filler material includes fiberglass.

[0026] An embodiment of the present application also provides a semiconductor package, comprising: a first electronic component; a second electronic component directly bonded to the first electronic component; a heat dissipation layer surrounding at least a portion of a top surface and a side surface of the second electronic component; and a filling material encapsulating the second electronic component and the heat dissipation layer, wherein an outer surface of the filling material includes a curved surface.

[0027] In some embodiments, the heat dissipation layer directly contacts the second electronic component.

[0028] In some embodiments, the filling material exposes a top surface of the heat dissipation layer, and a portion of an outer surface of the filling material connected to the heat dissipation layer includes a curved surface.

[0029] In some embodiments, the filling material includes a first portion and a second portion, the first portion is located between the heat dissipation layer and the second electronic component, and the second portion is located outside the heat dissipation layer.

[0030] The beneficial technical effects of the utility model are:

[0031] The filling material of the present application is not prone to peeling off from the second electronic component, thereby enhancing the structural stability of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A prior art D2W structure is shown.

[0033] Figure 2 A prior art W2W structure is shown.

[0034] Figure 3 A prior art D2W hybrid joint is shown.

[0035] Figure 4 The prior art is shown to use SiO2 material to fill the gaps between the dies.

[0036] Figure 5 A prior art CMP process is shown.

[0037] Figure 6 It shows that the prior art Figure 5 The structure shown is coupled to a support.

[0038] Figure 7 The prior art method for forming an ILD layer and the circuits therein is shown.

[0039] Figure 8 The prior art for forming a heat dissipation layer is shown.

[0040] Fig. 9 A semiconductor package according to an embodiment of the present application is shown.

[0041] Fig.10 It is shown that the filling material is disposed over the first electronic component, the second electronic component, and the third electronic component.

[0042] Fig.11 It is shown that the filling material covers the top surface of the first electronic component and the second and third electronic components.

[0043] Fig.12 A spin coating process is shown to form the filling material.

[0044] Fig.13 The surface of the filling material is shown to be planarized by a spin coating process.

[0045] Figures 14 to 18 Semiconductor packages according to different embodiments of the present application are respectively shown. DETAILED DESCRIPTION

[0046] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.

[0047] The embodiments of the present application will be described in detail below. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar reference numerals. The embodiments of the accompanying drawings described herein are illustrative, graphical, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.

[0048] As used herein, the terms "substantially," "substantially," "essentially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred precisely as well as instances where the event or circumstance occurred very approximately.

[0049] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivative terms (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific direction.

[0050] For convenience of description, “first”, “second”, “third”, etc. may be used herein to distinguish different components in one figure or a series of figures. “First”, “second”, “third”, etc. are not intended to describe the corresponding components.

[0051] Fig. 9 A semiconductor package 100 according to an embodiment of the present application is shown, comprising: a first electronic component 11; a second electronic component 12 directly bonded to the first electronic component 11, wherein the side surface of the second electronic component 12 and the top surface of the first electronic component 11 define an accommodating space 20; a filling material 30 located within the accommodating space 20, wherein the filling material 30 comprises a first gap 41, wherein the first gap 41 exposes a portion of the top surface of the first electronic component 11 and a portion of the side surface of the second electronic component 12, and the width of the first gap 41 gradually increases from top to bottom.

[0052] In some embodiments, the semiconductor package 100 further includes: a third electronic component 13, which is arranged side by side with the second electronic component 12 and directly bonded to the first electronic component 11, the side surface of the third electronic component 13, the side surface of the second electronic component 12, and the top surface of the first electronic component 11 together define the accommodation space 20, and the first gap 41 is closer to the side surface of the second electronic component 12 than to the central axis 201 of the accommodation space 20. In some embodiments, the second electronic component 12 and the third electronic component 13 are semiconductor dies.

[0053] In some embodiments, in a cross-sectional view through the first electronic component 11 , the second electronic component 12 , and the third electronic component 13 , the first void 41 has a triangular shape.

[0054] In some embodiments, the semiconductor package 100 further includes a second gap 42 located at a position where a side surface of the third electronic component 13 and a top surface of the first electronic component 11 intersect.

[0055] In some embodiments, the second gap 42 exposes a portion of a side surface of the third electronic component 13 .

[0056] In some embodiments, the second gap 42 exposes a portion of the top surface of the first electronic component 11 .

[0057] In some embodiments, second gaps 42 exist around the third electronic component 13 .

[0058] In some embodiments, first gaps 41 exist around the second electronic component 12 .

[0059] In some embodiments, the filling material 30 exposes the top surface of the second electronic component 12 .

[0060] In some embodiments, the height of the top surface of the filling material 30 is lower than the height of the top surface of the second electronic component 12 .

[0061] In some embodiments, the top surface of the filling material 30 has the highest height at the location where the second electronic component 12 is connected.

[0062] In some embodiments, an end of the top surface of the filling material 30 connects to an end of the top surface of the second electronic component 12 .

[0063] In some embodiments, the end of the top surface of the filling material 30 includes a curved surface 34. The filling material 30 of the present application is formed by a spin coating or hot pressing process, so the top surface is not filled (not flush with the top surfaces of the second electronic component 12 and the third electronic component 13), but includes a curved surface 34.

[0064] In some embodiments, the curved surface 34 is concave downward.

[0065] In some embodiments, the semiconductor package 100 further includes:

[0066] The heat dissipation layer 50 is located on the second electronic component 12 and adheres to the top surface of the second electronic component 12 .

[0067] In some embodiments, the heat dissipation layer 50 also adheres to the top surface of the filling material 30. Since the top surface of the portion of the filling material 30 located between the second electronic component 12 and the third electronic component is recessed downward, the portion of the heat dissipation layer 50 also extends downward to between the second electronic component 12 and the third electronic component 13, thereby increasing the heat dissipation effect.

[0068] In some embodiments, the filling material 30 includes glass fiber. In some embodiments, the material of the filling material 30 is, for example, the material of the filler in patent document CN113380751A.

[0069] Figure 10 to Figure 11 FIG. 1 shows a formation process of a semiconductor package 100 according to some embodiments of the present application, wherein the first air gap 41, the second air gap 42 and the curved surface 34 are not shown, and the positions and shapes of the first air gap 41, the second air gap 42 and the curved surface 34 are similar to those of FIG. 1 . Fig. 9 same.

[0070] See also Fig.10 The jig 101 sets the filling material 30 above the first electronic component 11 , the second electronic component 12 and the third electronic component 13 .

[0071] See also Fig.11 , a heating and pressurizing lamination process is performed to make the filling material 30 cover the top surface of the first electronic component 11 and the second electronic component 12 and the third electronic component 13, and the surface of the filling material 30 is flattened by heating and pressurizing, and then the flattening effect is achieved by baking (Cure), replacing the CVD and CMP processes of the prior art, and reducing the production cost. In some embodiments, the temperature of heating and pressurizing is greater than the glass transition temperature (Tg) of the filling material 30. In some embodiments, the filling material 30 can be a mold material (Mold), a dry film (Dry film), a non-conductive film (NCF), anisotropic conductive film (ACF), a prepreg (prepreg, PP), a flame retardant 4-level material (FR4), an Ajinomoto build-up film (Ajinomoto build-up film, ABF), a bismaleimide-triazine (BT) pressed film, and other materials.

[0072] Figure 12 to Figure 13FIG. 1 shows a formation process of a semiconductor package 100 according to some other embodiments of the present application, wherein the first air gap 41, the second air gap 42 and the curved surface 34 are not shown, and the positions and shapes of the first air gap 41, the second air gap 42 and the curved surface 34 are similar to those of FIG. 1 . Fig. 9 same.

[0073] See also Fig.12 , a spin coating process is performed to form the filling material 30. In some embodiments, the filling material 30 can be a coating material such as spin-on glass (SOG) (silicon dioxide material), polyimide (PI), etc.

[0074] See also Fig.13 The surface of the filling material 30 is flattened by a spin coating process, and then the flattening effect is achieved by curing, thereby replacing the CVD and CMP processes of the prior art and reducing the production cost.

[0075] Figures 14 to 18 FIG. 1 shows a semiconductor package 100 according to some other embodiments of the present application, wherein the first electronic component 11 and the first air gap 41 and the second air gap 42 are omitted, and the positions and shapes of the first electronic component 11 and the first air gap 41 and the second air gap 42 are similar to those in FIG. Fig. 9 Similarly, the semiconductor package 100 includes: a first electronic component 11; a second electronic component 12 directly bonded to the first electronic component 11; a heat dissipation layer 50 surrounding at least a portion of the top surface and side surface of the second electronic component 12; a filling material 30 encapsulating the second electronic component 12 and the heat dissipation layer 50, and the outer surface of the filling material 30 includes a curved surface 34.

[0076] See also Fig.14 and Fig.15 In some embodiments, the heat dissipation layer 50 directly contacts the second electronic component 12 .

[0077] See also Fig.14 In some embodiments, the filling material 30 exposes the top surface of the heat dissipation layer 50 , and a portion of the outer surface of the filling material 30 connected to the heat dissipation layer 50 includes a curved surface 34 .

[0078] See also Figures 16 to 18 In some embodiments, the filling material 30 includes a first portion 31 and a second portion 32 , the first portion 31 is located between the heat dissipation layer 50 and the second electronic component 12 , and the second portion 32 is located outside the heat dissipation layer 50 .

[0079] exist Fig.14In the illustrated embodiment, a physical vapor deposition (PVD) process is first performed to form the heat dissipation layer 50 of Cu material, and then a spin coating process is performed to form the filling material 30 of molding compound or SOG.

[0080] exist Fig.15 In the illustrated embodiment, a PVD process is first performed to form the heat dissipation layer 50 of Cu material, and then a lamination process is performed to form the filling material 30 of dry film, NCF, ACF, PP, FR4, ABF, BT lamination, etc.

[0081] exist Fig.16 In the illustrated embodiment, a lamination process is first performed to form a first portion 31 of a filling material 30 whose material is a dry film, NCF, ACF, PP, FR4, ABF, BT film, etc., and then a PVD process is performed to form a heat dissipation layer 50 of a Cu material, and then a spin coating process is performed to form a second portion 32 of the filling material 30 whose material is a molding compound or SOG, etc.

[0082] exist Fig.17 and Fig.18 In the illustrated embodiment, a lamination process is first performed to form a first portion 31 of a filling material 30 whose material is a dry film, NCF, ACF, PP, FR4, ABF, BT film, etc., and then a PVD process is performed to form a heat dissipation layer 50 of a Cu material, and then a lamination process is performed to form a second portion 32 of a filling material 30 whose material is a dry film, NCF, ACF, PP, FR4, ABF, BT film, etc. Fig.18 The pads 121 and 131 of the second electronic component 12 and the third electronic component of the semiconductor package 100 are shown in FIG. Fig.17 The embodiment shown is thin.

[0083] The material of the filling material 30 in the embodiment of the present application may be PP (thickness less than 10 μm), FR4 (thickness less than 2 μm), ABF (thickness ranges from 5 μm to 50 μm), BT (thickness less than 1 μm), molding compound (thickness ranges from 2 μm to 50 μm), dry film, NCF (thickness less than 50 μm), ACF (thickness less than 1 μm), PI or SOG, etc.

[0084] The material of the heat dissipation layer 50 of the embodiment of the present application can be Ti (thickness greater than 100 angstroms to 1000 angstroms), Cu (thickness greater than 100 angstroms to 2000 angstroms), TiN (thickness greater than 100 angstroms to 2000 angstroms), Au (thickness greater than 500 angstroms to 2000 angstroms), Ag (thickness greater than 100 angstroms), AlCu (thickness greater than 1000 angstroms), TiM (thickness greater than 500 angstroms), Cu foil (thickness greater than 3000 angstroms), Ta / TaN (thickness greater than 30 angstroms), SiC / SiCN (thickness greater than 50 angstroms), SiN / SiO2 (thickness greater than 50 angstroms), etc.

[0085] See also Fig.18 , distance A represents the distance between the bottom surface of the heat dissipation layer 50 and the bottom surface of the filling material 30, and is also the thickness of the first portion 31; distance B represents the thickness of the heat dissipation layer 50; distance C represents the maximum thickness of the second portion 32; distance D represents the distance between the second electronic component 12 and the third electronic component 13; distance E represents the thickness of the portion of the filling material 30 located above the top surface of the heat dissipation layer 50. In some embodiments, distance A < distance C, and distance A can be 0 (for example Fig.14 and Fig.15 In some embodiments, distance B ≤ distance A, and distance C ≥ distance B. In some embodiments, distance C > distance A, or distance C < distance A (distance C can be greater than Fig.16 The embodiment shown is thinner), or the filling material 30 includes only the first portion 31, and the second portion 32 does not exist. In some embodiments, the distance D>1μm, and the distance D can be as follows Fig.14 and Fig.15 As shown, two materials are included, and the distance D can be as follows Figures 16 to 18 In some embodiments, the distance E can be greater than 0, that is, Fig.15 , Fig.17 and Fig.18 The filler material 30 shown includes a portion covering the topmost surface of the heat dissipation layer 50. In some embodiments, the distance E may be equal to 0, that is, Fig.14 , Fig.16 The fill material 30 is shown exposing the topmost surface of the heat dissipation layer 50 .

[0086] The embodiment of the present application provides a solution for hybrid bonding of packages, including using a hot pressing process to form a filling material 30, which improves the yield of hybrid bonding products and reduces the production cost by about US$1.2M. The materials / processes at the OSAT end include the formation of a substrate, the formation of a redistribution layer (RDL), and a coating or lamination process. The embodiment of the present application focuses on the middle process and stacks a layer of electronic components (a first electronic component 12 and a third electronic component 13).

[0087] The filling material 30 of the present application is formed by a spin coating or thermal imprinting process, so there is a first gap 41 located at the corner of the accommodating space 20, which reduces the production cost, and the lamination process can also control the warping after bonding to avoid delamination between the filling material 30 and the second electronic component, thereby enhancing the structural stability.

[0088] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A semiconductor package, characterized in that: include: a first electronic component; a second electronic component directly bonded to the first electronic component, wherein a side surface of the second electronic component and a top surface of the first electronic component define an accommodation space; A filling material is located in the accommodating space, wherein the filling material includes a first gap, the first gap exposes a portion of the top surface of the first electronic component and a portion of the side surface of the second electronic component, and the width of the first gap gradually increases from top to bottom.

2. The semiconductor package according to claim 1, wherein: Also includes: A third electronic component is arranged side by side with the second electronic component and is directly bonded to the first electronic component, wherein a side surface of the third electronic component, a side surface of the second electronic component, and a top surface of the first electronic component together define the accommodating space, and the first gap is closer to the side surface of the second electronic component than to the central axis of the accommodating space.

3. The semiconductor package according to claim 2, wherein: The first gap has a triangular shape in a cross-sectional view through the first electronic component, the second electronic component, and the third electronic component.

4. The semiconductor package according to claim 1, wherein: The first gaps exist around the second electronic component.

5. The semiconductor package according to claim 1, wherein: The filling material exposes a top surface of the second electronic component.

6. The semiconductor package according to claim 5, wherein: A top surface of the filling material has a height lower than a height of the top surface of the second electronic component.

7. The semiconductor package according to claim 6, wherein: An end portion of the top surface of the filling material is connected to an end portion of the top surface of the second electronic component.

8. The semiconductor package according to claim 7, wherein: The end portion of the top surface of the filling material includes a curved surface, and the curved surface is recessed downward.

9. The semiconductor package according to claim 5, wherein: Also includes: The heat dissipation layer is located on the second electronic component and adheres to the top surface of the second electronic component. The heat dissipation layer also adheres to the top surface of the filling material.

10. The semiconductor package according to claim 1, wherein: The filling material includes glass fibers.

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