Display device

Abstract

There is provided a display device including: a display panel including pixels connected to scan lines and data lines; a flexible printed circuit board connected to the display panel; a light emission test circuit on the flexible printed circuit board and connected to the data line; and a plurality of resistors adjacent to opposite sides of the light emission test circuit and connected to the light emission test circuit. The display device can prevent or reduce damage to a light emission test circuit and reduce a brightness difference of a display panel during a pixel light emission test.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0064399 filed in the Korean Intellectual Property Office on May 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of some embodiments of the present disclosure described herein relate to a display device. Background Art

[0003] Generally, electronic devices that display images to users, such as smart phones, digital cameras, notebook computers, navigation systems, and smart TVs, include a display device for displaying images. The display device generates images and provides the generated images to the user through a display screen.

[0004] The display device includes a plurality of pixels for displaying an image, scan lines connected to the pixels, and data lines connected to the pixels. The pixels receive data voltages through the data lines in response to scan signals received through the scan lines. The pixels display images by emitting brightness corresponding to the data voltages.

[0005] When manufacturing a display device, a light emitting test circuit can be used to determine whether a pixel is functioning properly. The light emitting test circuit can be connected to a data line and apply a test signal to a pixel. The pixel is turned on in response to the test signal, and a pixel that fails to turn on or does not generate normal brightness is determined to be a defective pixel.

[0006] A light emission test circuit includes a plurality of transistors for switching transmission of a test signal. The transistors may be susceptible to external static electricity and may be damaged by the external static electricity. A technique for preventing or reducing damage to transistors of a light emission test circuit may be desired.

[0007] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore the information discussed in this background section does not necessarily constitute prior art. Utility Model Content

[0008] The utility model aims to provide a display device, which can prevent or reduce damage to a light emitting test circuit and reduce the brightness difference of a display panel during a pixel light emitting test.

[0009] According to some embodiments, a display device includes: a display panel including pixels connected to scan lines and data lines; a flexible printed circuit board connected to the display panel; a light emitting test circuit on the flexible printed circuit board and connected to the data lines; and a plurality of resistors adjacent to opposite sides of the light emitting test circuit to be connected to the light emitting test circuit.

[0010] According to some embodiments, a display device can prevent or reduce damage to a light emission test circuit and reduce a brightness difference of a display panel during a pixel light emission test. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of some embodiments of the present disclosure will become apparent by describing in more detail aspects of some embodiments of the present disclosure with reference to the accompanying drawings.

[0012] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0013] Figure 2 It is shown Figure 1 Schematic diagram of a cross section of a display device shown in .

[0014] Figure 3 It is shown Figure 2 Schematic diagram of a cross section of a display panel shown in .

[0015] Figure 4 is a view showing a cross-section of a display panel according to some embodiments of the present disclosure.

[0016] Figure 5 yes Figure 2 A plan view of the display panel shown in FIG.

[0017] Figure 6 yes Figure 5 0 is a cross-sectional view of a light-emitting element and a transistor of a pixel shown in FIG.

[0018] Fig. 7A and Figure 7B yes Figure 5 An enlarged view of a flexible printed circuit board from which a data driver is removed is shown in FIG.

[0019] Figure 8 It is shown that the positioning Fig. 7A 2 is a diagram showing a configuration of a light emitting test section on a flexible printed circuit board on the left side shown in FIG.

[0020] Fig. 9 It is schematically shown Figure 8 Schematic diagram of a planar configuration of a first transistor and a first resistor and a second resistor shown in .

[0021] Fig.10 is with Fig. 7A and Figure 7B The corresponding plan view shows that there is a Figure 8 A view of the flexible printed circuit board of the first lighting test circuit is shown in FIG.

[0022] Fig.11 is a diagram showing a configuration of a display device according to a comparative example. DETAILED DESCRIPTION

[0023] In the specification, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another component, it should be understood that the former can be directly on, directly connected to or coupled to the latter, and can also be on, connected to or coupled to the latter via a third intervening component.

[0024] The same reference numerals refer to the same components. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, proportion and size of the components are exaggerated.

[0025] The term "and / or" includes one or more combinations of the associated listed items.

[0026] Although the terms "first", "second", etc. can be used to describe various components, the components should not be interpreted as being limited by the terms. The terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles "one", "a (kind / person)", and "the (the)" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent.

[0027] In addition, the terms "below," "under," "on," "over," etc. are used to describe the relationship between components shown in the drawings. The terms are relative and are described with reference to the directions indicated in the drawings.

[0028] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined herein.

[0029] It will be understood that the terms "include", "comprising", "having", etc. indicate the existence of the features, quantities, steps, operations, elements or components or their combinations described in the specification, but do not exclude the possibility of the existence or addition of one or more other features, quantities, steps, operations, elements or components or their combinations.

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0031] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0032] Reference Figure 1 , the display device DD may have a plane defined by the first direction DR1 and the second direction DR2. The display device DD may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. However, the embodiments of the present disclosure are not limited thereto, and the display device DD may have various shapes such as a circle or a polygon.

[0033] A top surface of the display device DD in a third direction DR3 crossing the first and second directions DR1 and DR2 may be defined as a display surface DS and may have a plane defined by the first and second directions DR1 and DR2. An image generated by the display device DD may be provided to a user through the display surface DS.

[0034] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA, and may define a boundary of the display device DD printed in a color (e.g., a set or predetermined color). That is, according to some embodiments, the non-display area NDA may be positioned in the periphery of the display area DA (or positioned outside the occupied area of ​​the display area DA).

[0035] The display device DD may be used in large electronic devices such as televisions, monitors, or external billboards. In addition, the display device DD may be used in small and medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation systems, game consoles, smart phones, tablet computers, or cameras. However, the above examples are provided for illustrative purposes only, and as will be understood by those skilled in the art, the display device DD may be applied to any other electronic device without departing from the spirit and scope of the embodiments according to the present disclosure.

[0036] Figure 2 It is shown Figure 1 Schematic diagram of a cross section of a display device shown in .

[0037] Figure 2 A cross section of the display device DD when viewed in a first direction DR1 is shown.

[0038] Reference Figure 2 , the display device DD may include a display panel DP, an input sensing part ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0039] According to some embodiments of the present disclosure, the display panel DP may include a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, etc. In the following, it is described that the display panel DP is an organic light-emitting display panel.

[0040] The input sensing part ISP may be positioned on the display panel DP. The input sensing part ISP may include a plurality of sensing parts for sensing external input in a capacitive manner. When manufacturing the display device DD, the input sensing part ISP may be directly manufactured on the display panel DP. However, according to the embodiments of the present disclosure, it is not limited thereto, and the input sensing part ISP may be manufactured as a panel separated from the display panel DP and attached to the display panel DP through an adhesive layer.

[0041] The anti-reflection layer RPL may be positioned on the input sensing part ISP. When manufacturing the display device DD, the anti-reflection layer RPL may be directly manufactured on the input sensing part ISP. However, according to the embodiment of the present disclosure, it is not limited thereto, and the anti-reflection layer RPL may be manufactured as a separate panel and attached to the input sensing part ISP through an adhesive layer.

[0042] The anti-reflection layer RPL may be defined as an external light anti-reflection film. The anti-reflection layer RPL may reduce the reflectivity of external light incident from the top surface of the display device DD toward the display panel DP. Through the anti-reflection layer RPL, the user does not perceive the external light.

[0043] When external light directed toward the display panel DP is reflected from the display panel DP and provided to an external user again, the user may visually perceive the external light like a mirror. To prevent or reduce this phenomenon, the anti-reflection layer RPL may include a plurality of color filters for displaying the same color as the pixels of the display panel DP.

[0044] The color filter may filter the external light to the same color as the pixel. In this case, the external light may not be perceived by the user. However, according to the embodiment of the present disclosure, it is not limited thereto, and the anti-reflection layer RPL may include a phase retarder and / or a polarizer to reduce the reflectivity of the external light.

[0045] The window WIN may be positioned on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing part ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0046] The panel protection film PPF may be positioned under the display panel DP. The panel protection film PPF may protect the bottom surface of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0047] The first adhesive layer AL1 may be disposed between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF may be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be disposed between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL may be bonded to each other through the second adhesive layer AL2.

[0048] Figure 3 It is shown Figure 2 Schematic diagram of a cross section of a display panel shown in .

[0049] Figure 3 A cross section of the display panel DP when viewed in the first direction DR1 is shown, and an input sensing part ISP is shown together with the display panel DP.

[0050] Reference Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL, a display element layer DP-OLED, an encapsulation substrate EN-SB, a sealing layer SAL, and a filler FL. The circuit element layer DP-CL may be positioned on the substrate SUB. The display element layer DP-OLED may be positioned on the circuit element layer DP-CL.

[0051] A plurality of pixels may be positioned through the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor positioned in the circuit element layer DP-CL and a light emitting element positioned in the display element layer DP-OLED and connected to the transistor.

[0052] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The display element layer DP-OLED may be positioned in the display area DA. The encapsulation substrate EN-SB may be positioned on the display element layer DP-OLED. Each of the substrate SUB and the encapsulation substrate EN-SB may be of a rigid type. According to this structure, the display panel DP may be of a rigid type.

[0053] The sealing layer SAL may be disposed between the substrate SUB and the encapsulation substrate EN-SB. The sealing layer SAL may be positioned in the non-display area NDA. The sealing layer SAL may bond the substrate SUB and the encapsulation substrate EN-SB. The display element layer DP-OLED may be sealed between the substrate SUB and the encapsulation substrate EN-SB by the sealing layer SAL. The sealing layer SAL may include a photocurable material.

[0054] The filler FL may be disposed between the substrate SUB and the encapsulation substrate EN-SB. The filler FL may be disposed in a space sealed by the sealing layer SAL between the substrate SUB and the encapsulation substrate EN-SB. The filler FL may include a thermosetting material.

[0055] The input sensing part ISP may be directly positioned on the display panel DP. For example, the input sensing part ISP may be directly positioned on the encapsulation substrate EN-SB.

[0056] Figure 4 is a view showing a cross-section of a display panel according to some embodiments of the present disclosure.

[0057] Reference Figure 4 The display panel DP' may include a circuit element layer DP-CL positioned on the substrate SUB, a display element layer DP-OLED positioned on the circuit element layer DP-CL, and a thin film encapsulation layer TFE positioned on the display element layer DP-OLED.

[0058] The display panel DP' may be a flexible display panel. For example, the substrate SUB may include a flexible plastic material such as polyimide. The arrangement structure of the circuit element layer DP-CL and the display element layer DP-OLED may be similar to Figure 3 The arrangement structures of the circuit element layer DP-CL and the display element layer DP-OLED shown in FIG. 5 are the same.

[0059] The thin film encapsulation layer TFE may be positioned on the circuit element layer DP-CL so as to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may include an inorganic layer and an organic layer between the inorganic layers. The inorganic layer may protect the pixel from moisture / oxygen. The organic layer may protect the pixel from foreign matter such as dust particles. According to some embodiments, Figure 2 The input sensing part ISP shown in FIG. 1 may be directly positioned on the thin film encapsulation layer TFE.

[0060] Figure 5 yes Figure 2 A plan view of the display panel shown in FIG.

[0061] Reference Figure 5 , the display device DD may include a display panel DP, a scan driver SDV, a plurality of data drivers DDV, a plurality of flexible printed circuit boards FPCB, an emission driver EDV, and a printed circuit board PCB.

[0062] The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA and the non-display area NDA of the display panel DP may be respectively Figure 2 The display area DA shown in FIG. 1 corresponds to the non-display area NDA.

[0063] The display panel DP may have a rectangular shape having short sides extending in the first direction DR1 and long sides extending in the second direction DR2 However, the shape of the display panel DP is not limited thereto.

[0064] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, and a plurality of emission lines EL1 to ELm. Each of "m" and "n" is a positive integer.

[0065] The pixels PX may be positioned in the display area DA. The scan driver SDV and the emission driver EDV may be positioned in the non-display area NDA adjacent to a short side of the display panel DP.

[0066] The pixel PX may include a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels. The first pixels may display red, the second pixels may display green, and the third pixels may display blue.

[0067] When viewed from above a plane, the data driver DDV may be positioned adjacent to a lower side of the display panel DP, which is defined as one of the long sides of the display panel DP. When viewed from above a plane defined by the first direction DR1 and the second direction DR2 (e.g., when viewed in a plan view), the printed circuit board PCB may be positioned adjacent to the lower side of the display panel DP.

[0068] The flexible printed circuit board FPCB may be connected between the lower side of the display panel DP and the printed circuit board PCB. The data drivers DDV may be manufactured as integrated circuit chips and may be mounted on the flexible printed circuit boards FPCB, respectively. For example, four flexible printed circuit boards FPCB and four data drivers DDV are shown, but the number of the flexible printed circuit boards FPCB and the number of the data drivers DDV are not limited thereto.

[0069] The scan lines SL1 to SLm may extend in the second direction DR2 to be connected to the pixels PX and the scan driver SDV. The emission lines EL1 to ELm may extend in the second direction DR2 to be connected to the pixels PX and the emission driver EDV.

[0070] The data lines DL1 to DLn may extend in the first direction DR1 so as to be connected to the pixels PX and the data driver DDV. A plurality of data lines may be connected to each of the data drivers DDV.

[0071] According to some embodiments, the display device DD may further include a timing controller for controlling the operation of the scan driver SDV, the data driver DDV, and the emission driver EDV. The timing controller may be manufactured in the form of an integrated circuit chip and mounted on a printed circuit board PCB. The timing controller may be connected to the data driver DDV, the scan driver SDV, and the emission driver EDV through the printed circuit board PCB and the flexible printed circuit board FPCB.

[0072] The display device DD may include a plurality of test pad (or referred to as "solder pad") portions TPP positioned on the display panel DP. Each of the test pad portions TPP may be positioned in an area of ​​the display panel DP between a pair of corresponding flexible printed circuit boards FPCB among the flexible printed circuit boards FPCB. Each of the test pad portions TPP may be connected to a light emitting test portion (hereinafter referred to as "light emitting test portion") positioned on a pair of corresponding flexible printed circuit boards FPCB. Fig. 7A and Figure 7B ). Fig. 7A and Figure 7B This configuration is described in detail.

[0073] The scan driver SDV may generate a plurality of scan signals. The scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages. The data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The emission driver EDV may generate a plurality of emission signals. The emission signals may be applied to the pixels PX through the emission lines EL1 to ELm.

[0074] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may display an image by emitting light of brightness corresponding to the data voltage in response to an emission signal. The emission time of the pixel PX may be controlled by the emission signal.

[0075] Figure 6 yes Figure 5 0 is a cross-sectional view of a light-emitting element and a transistor of a pixel shown in FIG.

[0076] Reference Figure 6 , the light emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL and a light emitting layer EML. The first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. The second electrode CE may be positioned on the first electrode AE. The hole control layer HCL, the electron control layer ECL and the light emitting layer EML may be placed between the first electrode AE ​​and the second electrode CE.

[0077] The transistor T and the light emitting element OLED may be positioned on the substrate SUB. The display area DA may include an emission area LEA corresponding to the pixel PX and a non-emission area NLEA adjacent to the emission area LEA. The light emitting element OLED may be positioned in the emission area LEA.

[0078] The buffer layer BFL may be positioned on the substrate SUB, and the buffer layer BFL may be an inorganic layer. The semiconductor layers S, A, and D of the transistor T may be positioned on the buffer layer BFL. The semiconductor layers S, A, and D may include polycrystalline silicon. However, it is not limited thereto, and the semiconductor layers S, A, and D may include amorphous silicon.

[0079] The semiconductor layers S, A and D may be doped with N-type dopants or P-type dopants. The semiconductor layers S, A and D may include a highly doped region and a lightly doped region. The conductivity of the highly doped region (e.g., source region and drain region) may be greater than the conductivity of the lightly doped region. The highly doped region may be substantially used as a source electrode or a drain electrode of the transistor T. The lightly doped region may substantially correspond to a channel region (or channel) of the transistor T.

[0080] The source region S, the channel region A, and the drain region D of the transistor T may be formed of the semiconductor layers S, A, and D. The channel region A may be interposed between the source region S and the drain region D.

[0081] The first insulating layer INS1 may be positioned on the buffer layer BFL to cover the semiconductor layers S, A, and D. The gate electrode G (or control electrode) of the transistor T may be positioned on the first insulating layer INS1.

[0082] According to some embodiments, in addition to Figure 6 In addition to the transistor T shown in FIG. 8 , the pixel PX may further include a plurality of transistors and capacitors.

[0083] The second insulating layer INS2 may be positioned on the first insulating layer INS1 to cover the gate electrode G. The third insulating layer INS3 may be positioned on the second insulating layer INS2. The buffer layer BFL and the first to third insulating layers INS1 to INS3 may include an inorganic layer.

[0084] The connection electrode CNE may be disposed between the transistor T and the light emitting element OLED. The connection electrode CNE may electrically connect the transistor T and the light emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 positioned on the first connection electrode CNE1.

[0085] The first connection electrode CNE1 may be positioned on the third insulating layer INS3 and may be connected to the drain region D through a first contact hole CH1 defined in the first to third insulating layers INS1 to INS3. The fourth insulating layer INS4 may be positioned on the third insulating layer INS3 to cover the first connection electrode CNE1.

[0086] The second connection electrode CNE2 may be positioned on the fourth insulating layer INS4. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4. The fifth insulating layer INS5 may be positioned on the fourth insulating layer INS4 to cover the second connection electrode CNE2. The fourth insulating layer INS4 and the fifth insulating layer INS5 may include an inorganic layer or an organic layer.

[0087] The first electrode AE ​​may be positioned on the fifth insulating layer INS5. The first electrode AE ​​may be electrically connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the fifth insulating layer INS5.

[0088] A pixel defining layer PDL exposing a portion (eg, a set or predetermined portion) of the first electrode AE ​​may be positioned on the first electrode AE ​​and the fifth insulating layer INS5. An opening PX_OP for exposing a portion (eg, a set or predetermined portion) of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0089] The hole control layer HCL may be positioned on the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may be commonly positioned in the emission area LEA and the non-emission area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0090] The light emitting layer EML may be positioned on the hole control layer HCL. The light emitting layer EML may be positioned in a region corresponding to the opening PX_OP. The light emitting layer EML may include an organic material and / or an inorganic material. The light emitting layer EML may generate one of red light, green light, and blue light.

[0091] The electron control layer ECL may be positioned on the light emitting layer EML and the hole control layer HCL. The electron control layer ECL may be commonly positioned in the emission area LEA and the non-emission area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0092] The second electrode CE may be positioned on the electronic control layer ECL. The second electrode CE may be positioned commonly in the pixel PX. That is, the second electrode CE may be positioned commonly on the light emitting layer EML of the pixel PX.

[0093] The layers from the buffer layer BFL to the fifth insulating layer INS5 may be defined as a circuit element layer DP-CL. The layer on which the light emitting element OLED is positioned may be defined as a display element layer DP-OLED.

[0094] A first voltage may be applied to the first electrode AE, and a second voltage having a level lower than the first voltage may be applied to the second electrode CE. Excitons may be formed by recombining holes and electrons injected into the light-emitting layer EML. When the excitons transition to a ground state, the light-emitting element OLED may emit light. The light-emitting element OLED may emit light to display an image.

[0095] Fig. 7A and Figure 7B yes Figure 5 An enlarged view of a flexible printed circuit board from which a data driver is removed is shown in FIG.

[0096] For example, Fig. 7A and Figure 7B A portion of the display panel DP connected to the flexible printed circuit board FPCB is also shown. Fig. 7A and Figure 7B The pixels PX connected to the data lines DL1 to DLn are omitted.

[0097] Fig. 7A 2 is a diagram illustrating a flexible printed circuit board FPCB on the left side with respect to the center of the display panel DP. Figure 7B 2 is a diagram illustrating a flexible printed circuit board FPCB on the right side with respect to the center of the display panel DP.

[0098] Reference Fig. 7A and Figure 7B , a plurality of mounting areas MA can be defined on the flexible printed circuit board FPCB. The mounting area MA can be defined as a mounting area Figure 5 The mounting areas MA may have a shape corresponding to the data drivers DDV. For example, each of the mounting areas MA may have a rectangular shape to correspond to each of the data drivers DDV having a rectangular shape.

[0099] A plurality of first pads PD1 and a plurality of second pads PD2 may be positioned on each of the flexible printed circuit boards FPCB. The first pads PD1 and the second pads PD2 may be positioned on opposite sides of each of the mounting areas MA in the first direction DR1. The first pads PD1 and the second pads PD2 may be positioned on opposite sides of each of the mounting areas MA in the second direction DR2.

[0100] The first pad PD1 and the second pad PD2 may be spaced apart from each other in the first direction DR1. The first pad PD1 may be arranged in the second direction DR2. The second pad PD2 may be arranged in the second direction DR2. The first pad PD1 may be closer to the display panel DP than the second pad PD2.

[0101] The data driver DDV may be connected to the first pad PD1 and the second pad PD2 in the mounting area MA. The first pad PD1 may be connected to the data lines DL1 to DLn. The second pad PD2 may be connected to Figure 5 The printed circuit board PCB shown in .

[0102] The plurality of pieces of image data output from the timing controller of the printed circuit board PCB may be provided to the data driver DDV through the second pad PD2. The data driver DDV may generate a data voltage by using a video signal. The data voltage may be applied to the data lines DL1 to DLn through the first pad PD1.

[0103] The display device DD may include a plurality of light emitting test parts LIP respectively positioned on the flexible printed circuit board FPCB. The light emitting test parts LIP may be connected to the first pad PD1 but not to the second pad PD2. Figure 5 When the data driver DDV shown in FIG. 1 is removed, the light emitting test part LIP may be exposed to the outside. That is, the light emitting test part LIP may be positioned under the data driver DDV, respectively (or substantially under the data driver DDV).

[0104] Before the data drivers DDV are respectively mounted on the mounting areas MA, the pixels PX may be tested using the light emitting test part LIP. The light emitting test part LIP may apply a test signal for testing an operation state of the pixel PX to the pixel PX. The test signal may be provided to the pixel PX by being applied to the data lines DL1 to DLn via the first pad PD1.

[0105] In response to the test signal, the pixel PX may be driven to generate light. In response to the test signal, it may be tested whether the pixel PX is defective by identifying a light emitting state of the pixel PX.

[0106] Each of the test pad parts TPP may be placed on the display panel DP and may be commonly connected to the light emitting test parts LIP positioned on a pair of corresponding flexible printed circuit boards FPCB. Each of the test pad parts TPP may include a plurality of test pads TP.

[0107] The test pad TP of each of the test pad parts TPP may be commonly connected to a pair of corresponding light emitting test parts LIP. The test pad TP and the light emitting test parts LIP may be connected by a test line TL. The test line TL may be connected to the light emitting test part LIP on the flexible printed circuit board FPCB, may extend to the display panel DP, and may be connected to the test pad TP.

[0108] The configurations of the light emission test parts LIP are the same as each other, and therefore, the configuration of one light emission test part LIP will be described below.

[0109] Figure 8 It is shown that the positioning Fig. 7A 2 is a diagram showing a configuration of a light emitting test section on a flexible printed circuit board on the left side shown in FIG.

[0110] For example, Figure 8 The data lines are shown simply by using a single label "DL".

[0111] Reference Fig. 7A and Figure 8 The light emitting test part LIP may include a light emitting test circuit LIC positioned on the corresponding flexible printed circuit board FPCB and a plurality of resistors R1 and R2. The light emitting test circuit LIC may be connected to the data line DL. For example, the light emitting test circuit LIC may be connected to the data line DL by being connected to the first pad PD1. The light emitting test circuit LIC may not be connected to the data line DL. Fig. 7A The second pad PD2 is shown in FIG.

[0112] The resistors R1 and R2 may be placed adjacent to opposite sides of the light emitting test circuit LIC to be connected to the light emitting test circuit LIC. The opposite sides of the light emitting test circuit LIC may be opposite to each other in the second direction DR2.

[0113] The lighting test circuit LIC may include first, second, and third lighting test circuits LIC1, LIC2, and LIC3. The resistors R1 and R2 may include a plurality of first resistors R1 adjacent to one side of the lighting test circuit LIC and a plurality of second resistors R2 adjacent to the other side of the lighting test circuit LIC.

[0114] The first light emission test circuit LIC1 may be connected to the first pixel PX1 among the pixels PX through the data line DL. The second light emission test circuit LIC2 may be connected to the second pixel PX2 among the pixels PX through the data line DL. The third light emission test circuit LIC3 may be connected to the third pixel PX3 among the pixels PX through the data line DL.

[0115] The first light emitting test circuit LIC1, the second light emitting test circuit LIC2, and the third light emitting test circuit LIC3 may be connected to the data line DL by being connected to the first pad PD1. The first light emitting test circuit LIC1, the second light emitting test circuit LIC2, and the third light emitting test circuit LIC3 may not be connected to the data line DL. Fig. 7A The second pad PD2 is shown in FIG.

[0116] The test pad TP of the test pad part TPP may include a first test pad TP1 and a plurality of second test pads TP2-1, TP2-2, and TP2-3. The first test pad TP1 and the plurality of second test pads TP2-1, TP2-2, and TP2-3 may be placed Fig. 7AThe first test pad TP1 and the plurality of second test pads TP2-1, TP2-2 and TP2-3 may be connected to the first light emitting test circuit LIC1, the second light emitting test circuit LIC2 and the third light emitting test circuit LIC3 through the test line TL.

[0117] The first test pad TP1 may be commonly connected to the first light emitting test circuit LIC1, the second light emitting test circuit LIC2, and the third light emitting test circuit LIC3. A control signal may be applied to the first light emitting test circuit LIC1, the second light emitting test circuit LIC2, and the third light emitting test circuit LIC3 through the first test pad TP1. The first light emitting test circuit LIC1, the second light emitting test circuit LIC2, and the third light emitting test circuit LIC3 may be turned on in response to the control signal received through the first test pad TP1.

[0118] The second test pad TP2-1 may be connected to the first light emitting test circuit LIC1. The second test pad TP2-2 may be connected to the second light emitting test circuit LIC2. The second test pad TP2-3 may be connected to the third light emitting test circuit LIC3.

[0119] Through the second test pads TP2-1, TP2-2, and TP2-3, the test signals may be applied to the first light emitting test circuit LIC1, the second light emitting test circuit LIC2, and the third light emitting test circuit LIC3, respectively. The first light emitting test circuit LIC1 may provide the test signal to the first pixel PX1 through the data line DL. The second light emitting test circuit LIC2 may provide the test signal to the second pixel PX2 through the data line DL. The third light emitting test circuit LIC3 may provide the test signal to the third pixel PX3 through the data line DL.

[0120] The first resistor R1 may be adjacent to one side of the first, second and third light emitting test circuits LIC1, LIC2 and LIC3, respectively. The second resistor R2 may be adjacent to the other side of the first, second and third light emitting test circuits LIC1, LIC2 and LIC3, respectively.

[0121] A pair of first resistors R1 and second resistors R2 may be positioned adjacent to opposite sides of the first light emitting test circuit LIC1 that are opposite to each other in the second direction DR2. Another pair of first resistors R1 and second resistors R2 may be positioned adjacent to opposite sides of the second light emitting test circuit LIC2 that are opposite to each other in the second direction DR2. Yet another pair of first resistors R1 and second resistors R2 may be positioned adjacent to opposite sides of the third light emitting test circuit LIC3 that are opposite to each other in the second direction DR2.

[0122] The first light emitting test circuit LIC1, the second light emitting test circuit LIC2, and the third light emitting test circuit LIC3 may include a plurality of transistors T1, T2, and T3, respectively. The first light emitting test circuit LIC1 may include a plurality of first transistors T1; the second light emitting test circuit LIC2 may include a plurality of second transistors T2; and the third light emitting test circuit LIC3 may include a plurality of third transistors T3. The first transistor T1, the second transistor T2, and the third transistor T3 may be PMOS transistors, but are not limited thereto. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may be NMOS transistors.

[0123] The configurations of the first, second, and third lighting test circuits LIC1, LIC2, and LIC3 are substantially the same. Therefore, the configurations of the first lighting test circuit LIC1 and the first and second resistors R1 and R2 connected to the first lighting test circuit LIC1 will be mainly described below.

[0124] Each of the first transistors T1 may include a gate electrode GE (or a control electrode), a first electrode SE (or a source electrode), a second electrode DE (or a drain electrode), and a semiconductor layer. The semiconductor layer may be connected to Figure 6 The semiconductor layers S, A and D shown in correspondence.

[0125] The first and second resistors R1 and R2 may be connected to the gate electrode GE and the first electrode SE of the first transistor T1. In detail, the first and second resistors R1 and R2 may be adjacent to opposite sides of the first light emission test circuit LIC1 to be commonly connected to the gate electrode GE and the first electrode SE of the first transistor T1.

[0126] The first resistor R1 may be adjacent to one side of the first light emitting test circuit LIC1 to be connected to the first transistor T1. The second resistor R2 may be adjacent to the other side of the first light emitting test circuit LIC1 to be connected to the first transistor T1.

[0127] The second electrodes DE of the first transistors T1 may be connected to the corresponding data lines DL, respectively. For example, the second electrodes DE of the first transistors T1 may be connected to the data lines DL connected to the first pixels PX1.

[0128] The first resistor R1 and the second resistor R2 may be implemented with high resistance polysilicon semiconductor, etc. For example, the first resistor R1 and the second resistor R2 may include the same material and be located at the same layer as the semiconductor layer of each of the first transistors T1.

[0129] The gate electrode and the first electrode of the second transistor T2 may also be connected to the corresponding first resistor R1 and the corresponding second resistor R2. The second electrode of the second transistor T2 may be connected to the data line DL connected to the second pixel PX2.

[0130] A gate electrode and a first electrode of the third transistor T3 may be connected to a corresponding first resistor R1 and a corresponding second resistor R2. A second electrode of the third transistor T3 may be connected to a data line DL connected to the third pixel PX3.

[0131] The gate electrode GE of the first transistor T1 may be connected to the first test pad TP1. The first electrode SE of the first transistor T1 may be commonly connected to the corresponding second test pad TP2-1 among the second test pads TP2-1, TP2-2, and TP2-3. The first transistor T1 may receive a control signal through the first test pad TP1, and may receive a test signal through the second test pad TP2-1.

[0132] The first transistor T1 may be turned on in response to a control signal received through the first test pad TP1. Thus, the turned-on first transistor T1 may provide a test signal received through the second test pad TP2-1 to the first pixel PX1. The first transistor T1 may be turned on during a light emission test of the first pixel PX1 to provide the test signal to the first pixel PX1. Thus, it may be tested whether the first pixel PX1 is lit.

[0133] The gate electrode of the second transistor T2 may be connected to the first test pad TP1, and the first electrode of the second transistor T2 may be connected to the corresponding second test pad TP2-2. The gate electrode of the third transistor T3 may be connected to the first test pad TP1, and the first electrode of the third transistor T3 may be connected to the corresponding second test pad TP2-3.

[0134] The second transistor T2 and the third transistor T3 may be turned on in response to a control signal received through the first test pad TP1. The second transistor T2 and the third transistor T3 may provide the second pixel PX2 and the third pixel PX3 with a test signal received through the second test pads TP2-2 and TP2-3. Therefore, it may be tested whether the second pixel PX2 and the third pixel PX3 are lit.

[0135] After testing the pixel PX, the first transistor T1, the second transistor T2, and the third transistor T3 may be turned off. After that, the data driver DDV may be mounted on the flexible printed circuit board FPCB, and the pixel PX may display an image in a display mode. In the display mode, the transistors T1, T2, and T3 may be turned off.

[0136] The transistors T1, T2, and T3 defined as elements of the light emitting test circuit LIC may be susceptible to static electricity. When external static electricity flows into the light emitting test circuit LIC, the transistors T1, T2, and T3 may be damaged.

[0137] Static electricity can be defined as the rapid flow of electric current. According to some embodiments of the present disclosure, when static electricity enters the light emitting test circuit LIC, the first resistor R1 and the second resistor R2 can block the rapid current flow. That is, the first resistor R1 and the second resistor R2 can be used to dissipate static electricity. Therefore, by preventing or reducing static electricity via the first resistor R1 and the second resistor R2, damage to the transistors T1, T2, and T3 of the light emitting test circuit LIC can be prevented or reduced.

[0138] Fig. 9 It is schematically shown Figure 8 Schematic diagram of a planar configuration of a first transistor and a first resistor and a second resistor shown in .

[0139] Reference Fig. 9 Each of the first transistors T1 may include a semiconductor layer AT, a gate electrode GE, a first electrode SE, and a second electrode DE. The stacked structure of the first transistors T1 may be similar to Figure 6 The stacking structure of the transistors T shown in FIG. 1 is substantially the same.

[0140] The semiconductor layer AT can be Figure 6 The semiconductor layers S, A, and D shown in FIG. 8 correspond to the semiconductor layers S, A, and D. The semiconductor layer AT of the first transistor T1 may extend in the first direction DR1 and may be arranged in the second direction DR2.

[0141] The gate electrode GE can be connected to Figure 6 The gate electrode GE of the first transistor T1 may be integrally formed and may extend in the second direction DR2. When viewed from above a plane, the gate electrode GE may extend to cross the semiconductor layer AT. An insulating layer may be interposed between the gate electrode GE and the semiconductor layer AT.

[0142] The first electrode SE and the second electrode DE may be connected to Figure 6 The first electrode SE and the second electrode DE may be formed of the same material as the first connection electrode CNE1 to be spaced apart from each other in the first direction DR1.

[0143] The first electrode SE of the first transistor T1 may be integrally formed to be connected to the semiconductor layer AT through the first contact hole CTH1. The first contact hole CTH1 may be defined in the insulating layer between the first electrode SE and the semiconductor layer AT.

[0144] The second electrodes DE of the first transistors T1 may be arranged in the second direction DR2 and may be respectively connected to the semiconductor layer AT through second contact holes CTH2. The second contact holes CTH2 may be defined in the insulating layer between the second electrodes DE and the semiconductor layer AT.

[0145] The first electrode SE may be connected to one end of the semiconductor layer AT. The second electrode DE may be connected to the other end of the semiconductor layer AT. The gate electrode GE may extend between the first electrode SE and the second electrode DE to cross the semiconductor layer AT.

[0146] The first resistor R1 and the second resistor R2 may be positioned at the same layer as the semiconductor layer AT and may be formed of the same material as the semiconductor layer AT. The first resistor R1 and the second resistor R2 may be connected to the gate electrode GE and the first electrode SE through the third contact hole CTH3. The third contact hole CTH3 may be defined in the insulating layer between the first resistor R1 and the second resistor R2 and the gate electrode GE and the insulating layer between the first resistor R1 and the second resistor R2 and the first electrode SE.

[0147] For example, the first resistor R1 and the second resistor R2 may be symmetrical to each other and have substantially the same shape as each other, but the shapes of the first resistor R1 and the second resistor R2 are not limited thereto.

[0148] Fig.10 is with Fig. 7A and Figure 7B The corresponding plan view shows that there is a Figure 8 A view of the flexible printed circuit board of the first lighting test circuit is shown in FIG. Fig.11 is a diagram showing a configuration of a display device according to a comparative example.

[0149] For example, Fig.11 is with Fig.10 The corresponding floor plan.

[0150] To simplify the drawings, Fig.10 The second light emitting test circuit LIC2 and the third light emitting test circuit LIC3 are omitted, and the flexible printed circuit board FPCB is Fig. 7A and Figure 7B In addition, for ease of illustration, the installation area MA is shown as Fig. 7A and Figure 7B The mounting area MA is large, the first test pad TP1 and the second test pad TP2-1 are shown, and the second test pads TP2-2 and TP2-3 are omitted. Fig.10 and Fig.11 The pixel PX is omitted.

[0151] Reference Fig.10As described above, the first light emission test circuit LIC1 may be connected to the first pad PD1 and may not be connected to the second pad PD2. Therefore, the first transistor T1 may be connected to the first pad PD1 and may not be connected to the second pad PD2.

[0152] The first resistor R1 and the second resistor R2 may be adjacent to opposite sides of the flexible printed circuit board FPCB than the first and second pads PD1 and PD2 and the first transistor T1. The opposite sides of the flexible printed circuit board FPCB may be opposite to each other in the second direction DR2. Therefore, the opposite sides of the flexible printed circuit board FPCB may correspond to opposite sides of the first light emitting test circuit LIC1 that are opposite to each other in the second direction DR2.

[0153] Reference Fig.11 ,and Fig.10 In contrast, the resistor R may be positioned only at the leftmost and rightmost sides of the flexible printed circuit board FPCB, respectively. In this case, during the light emission test, a portion of the display panel DP corresponding to the region where the resistor R is positioned and another portion of the display panel DP may emit light having different brightness. That is, since the resistor R is unevenly arranged on the display panel DP, a brightness difference of the display panel DP may occur.

[0154] Reference Fig.10 , the first resistor R1 and the second resistor R2 may be positioned at opposite sides of each of the flexible printed circuit boards FPCB. Fig.11 In comparison, Fig.10 In the embodiment, the first resistor R1 and the second resistor R2 may be uniformly arranged on the display panel DP. In this case, during the light emission test, a brightness difference of the display panel DP may not occur.

[0155] According to some embodiments of the present disclosure, resistors for preventing or reducing static electricity can be positioned adjacent to both sides of each of the light emitting test circuits. Since the resistors prevent or reduce static electricity, damage to transistors of the light emitting test circuits can be prevented or reduced. In addition, because the resistors are relatively evenly placed on the display panel, the brightness difference of the display panel can be reduced during the light emitting test of the pixels.

[0156] Although aspects of some embodiments of the present disclosure have been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims and their equivalents.

Claims

1. A display device, characterized in that: The display device comprises: A display panel including pixels connected to scan lines and data lines; a flexible printed circuit board connected to the display panel; a light emitting test circuit, on the flexible printed circuit board and connected to the data line; and A plurality of resistors are adjacent to opposite sides of the lighting test circuit and connected to the lighting test circuit.

2. The display device according to claim 1, characterized in that The light emitting test circuit includes a transistor including a gate electrode, a semiconductor layer, a first electrode, and a second electrode connected to the data line, and Wherein, the resistor is connected to the gate electrode and the first electrode.

3. The display device according to claim 2, characterized in that: The resistor is formed of the same material as the semiconductor layer.

4. The display device according to claim 2, characterized in that: The resistor is in the same layer as the semiconductor layer.

5. The display device according to claim 2, characterized in that: The pixel includes a plurality of pixels, the data line includes a plurality of data lines, and the transistor includes a plurality of transistors, and The resistor is adjacent to the opposite side of the light emitting test circuit and is commonly connected to gate electrodes of the plurality of transistors and first electrodes of the plurality of transistors.

6. The display device according to claim 5, characterized in that: The resistor comprises: a first resistor adjacent to one side of the light emitting test circuit and connected to the transistor; and A second resistor is adjacent to the other side of the light emitting test circuit and is connected to the transistor.

7. The display device according to claim 5, characterized in that: The display device further includes: a first test pad connected to the gate electrode of the transistor; and The second test pad is connected to the first electrode of the transistor.

8. The display device according to claim 7, characterized in that: The first test pad and the second test pad are on the display panel.

9. The display device according to claim 7, characterized in that: The transistor is configured to receive a control signal through the first test pad and to receive a test signal through the second test pad.

10. The display device according to claim 1, characterized in that: A resistor adjacent to a first side of the light emitting test circuit and a resistor adjacent to a second side of the light emitting test circuit have shapes symmetrical to each other, the second side being opposite to the first side.

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