Narrowband signal acquisition, generation and processing module

Abstract

The utility model provides a narrowband signal acquisition, generation and processing module. The narrowband signal acquisition, generation and processing module comprises a power supply module, an FSOC module, an FPGA module, a narrowband module, a clock module, a communication module, a Beidou module, an optical module and an external interface unit. The FPGA module, the FSOC module, the narrowband module and the clock module are in internal communication connection; the communication module and the external interface unit are in external communication connection; the narrowband module comprises three AD acquisition channels and two DA output channels. According to the utility model, through circuit configuration on the module, three paths of AD acquisition and two paths of DA output are realized, the output frequency is 390MHz, and the receiving frequency is 360MHz. And the circuit is realized by a narrowband transceiving chip, so that the hardware complexity of the module is reduced, the requirement of high integration is realized, a configurable scheme is provided, and the frequency points of transceiving signals can be changed according to requirements.

Description

Technical Field

[0001] The utility model belongs to the technical field of signal processing, and in particular relates to a narrowband signal acquisition, generation and processing module. Background Art

[0002] A narrowband signal is a signal with a relatively narrow frequency range. Typically, the frequency range of a narrowband signal is small compared to the center frequency of the signal. This means that on the spectrum, the frequency bandwidth occupied by a narrowband signal is relatively small. In contrast, a wideband signal has a wider frequency range and a larger bandwidth. Narrowband signals have important applications in communication systems and signal processing because they can be processed and transmitted more easily. For example, in wireless communications, narrowband signals can use spectrum resources more efficiently and are easier to detect and distinguish in a noisy environment.

[0003] Narrowband signal acquisition and generation module cards have been widely used in military, communication and other fields, mainly for the acquisition and generation of narrowband signals. With the development of chip technology, the requirements for miniaturization, localization and flexible control of narrowband signal acquisition are becoming higher and higher. Therefore, it is urgent to propose a highly integrated, localized and configurable narrowband signal acquisition and generation module. Utility Model Content

[0004] The technical problem to be solved by the utility model is to provide a narrowband signal acquisition and generation processing module to achieve high integration, flexible frequency configuration and localization under the requirements of multi-channel acquisition and signal generation.

[0005] In order to solve the above technical problems, the technical solution provided by the utility model is: a narrowband signal acquisition and generation processing module, including a power module, a FSOC module, a FPGA module, a narrowband module, a clock module, a communication module, a Beidou module, an optical module and an external interface unit; the FPGA module, the FSOC module, the narrowband module and the clock module are internally communicated and connected; the communication module and the external interface unit are externally communicated and connected; the narrowband module includes 3 AD acquisition channels and 2 DA output channels.

[0006] As an improvement, the narrowband module is a domestically produced CX9261 chip, which achieves an intermediate frequency of 400MHz output frequency and an intermediate frequency of 350MHz receiving frequency.

[0007] As an improvement, the FPGA module is a domestic FPGA chip, and its chip model is JFM7VX690T36; the FPGA module realizes data transmission with the FSOC module through GTH, LVDS, and GPIO interfaces, performs data interaction and clock control; the FPGA module implements the JESD204B protocol through the GTX interface to complete communication and control with the narrowband transceiver chip.

[0008] As an improvement, the FSOC module is a domestic SOC chip, and its chip model is FMQL45T900; the SOC chip realizes data communication with the external module through GPIO and SPI interfaces; the SOC chip is connected to the Beidou module through the RS232 interface; the SOC chip is connected to the optical module through the GTX interface; the SOC chip communicates with the external module through 1 GMAC to realize the network port management function.

[0009] As an improvement, the communication module is an optical fiber module, and the optical fiber module is connected to the SOC chip to realize data interaction of the 10G network.

[0010] As an improvement, the FPGA modules are all configured with a SPI FLASH configuration chip, the chip model is EFM25QU256; the FSOC module is configured with an EFM25QL256 configuration chip and an EMMC chip FEMDMW032G.

[0011] As an improvement, the FPGA module and the FSOC module are both configured with a DDR3 chip, the chip model is HXI15H4G160A, to achieve cache of operation data.

[0012] The advantages of the utility model compared with the prior art are:

[0013] (1) Through the circuit configuration on the module, 3-way AD acquisition and 2-way DA output are realized, with an output frequency of 390MHz and a receiving frequency of 360MHz. The circuit is implemented by a narrowband transceiver chip, which reduces the hardware complexity of the module, realizes the requirements of high integration, and provides a configurable solution to change the frequency of the transceiver signal according to needs;

[0014] (2) In the design of FPAG and FSOC modules, the domestically produced FPGA and FSOC architectures are adopted, which fully utilizes the rich interfaces and parallel data processing capabilities of FPGA, improves the module data transmission performance, and improves the flexible control capabilities;

[0015] (3) The main components in the design are all domestically produced components, which realizes the domestic design of the module and enhances the independent controllability of this type of circuit module. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The utility model is a circuit block diagram of a narrowband signal acquisition, generation and processing module.

[0017] Figure 2 The utility model is a power rail block diagram of a narrowband signal acquisition, generation and processing module.

[0018] Figure 3The utility model is a clock tree block diagram of a narrowband signal acquisition and generation processing module. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0020] In the description of the utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the utility model can be understood according to specific circumstances.

[0021] Embodiment 1:

[0022] As the instruction manual Figure 1 As shown, a narrowband signal acquisition and generation processing module includes a power module, an FSOC module, an FPGA module, a narrowband module, a clock module, a communication module, a Beidou module and an external interface unit, etc. It mainly completes the narrowband signal processing function. The downlink function is to receive data from the optical fiber interface, modulate and DA convert it into an intermediate frequency output to the radio frequency board; the downlink function receives narrowband signal data from the radio frequency board, and outputs it to the upper layer business through the optical fiber interface after AD conversion and demodulation.

[0023] A narrowband signal acquisition, generation and processing module includes a domestic FPGA chip and a domestic FSOC chip; the FPGA chip cooperates with a peripheral clock module, a configuration chip, a cache chip, and high-speed and low-speed interfaces to form an FPGA module; the FSOC chip also cooperates with its peripheral clock, configuration chip, cache chip, and high-speed and low-speed interfaces to form an FSOC module, which together provide signal acquisition and generation functions, signal preprocessing and data exchange functions, and at the same time, GPIO communication, SPI communication, timing communication, status communication, etc. realize data exchange with external devices through a VPX interface.

[0024] Specifically, the FPGA is connected to the FSOC for communication; meanwhile, the FPGA is connected to the narrowband transceiver chip for communication.

[0025] The FPGA communicates with the narrowband transceiver chip to realize the acquisition of narrowband signals and the signal generation and transmission functions. The FPGA communicates control commands with the narrowband transceiver chip through the SPI interface, and completes the reception of collected data and the transmission of generated signal data through the JESD204B protocol interface.

[0026] The FPGA and FSOC are connected through 10 low-speed interfaces GPIO and high-speed interfaces LVDS (16X) and SRIO interface (8X).

[0027] When performing the signal acquisition function, the FPGA configures the narrowband transceiver chip by sending control commands, and receives and caches the data collected by the narrowband transceiver chip for synchronous processing. According to requirements, data can be sent to the FSOC for data preprocessing through the high-speed interface with the FSOC, and reported through the network interface; data can also be sent to external devices for data processing through the high-speed interface with the optical module.

[0028] When performing the signal generation function, the FSOC communicates data with the FPGA and sends the calculated signal weights to the FPGA for it to generate related transmission data. The FPGA sends the data to the narrowband transceiver chip through the high-speed interface to achieve the final signal generation.

[0029] The FSOC chip realizes Beidou module communication through the R232 interface and completes the collection and update of module positioning information.

[0030] FPGA and FSOC chips are controlled by external devices and RF modules through GPIO interface and SPI interface, and realize timing communication and status communication.

[0031] FPGA chips are all equipped with SPI FLASH configuration chips, the chip model is EFM25QU256; FSOC chips are equipped with EFM25QL256 configuration chips, and are equipped with EMMC chips FEMDMW032G; FPGA and FSOC chips are all equipped with DDR3 chips, the chip model is HXI15H4G160A, to achieve cache of computing data.

[0032] The narrowband transceiver chip CX9261 is a broadband, high-performance, multi-channel RF transceiver chip. The programmability of the chip makes it widely used in modern communication equipment. The chip integrates low noise amplifier, up and down mixer, multi-mode filter, automatic gain control, DC offset cancellation, power intensity detection, ADC / DAC (specifically AD acquisition chip / DA acquisition chip), driver amplifier, power management, fractional frequency synthesis, logic control, extraction interpolation filtering, digital down conversion and automatic calibration, etc. It has the characteristics of universal design, wide bandwidth coverage, narrow and wideband signal compatibility, and low power consumption.

[0033] The SOC chip communicates with the optical module through the GTX interface to achieve 10G network or SRIO communication. It is used for the transmission of raw data.

[0034] As the instruction manual Figure 2 The figure is a power rail diagram of the narrowband signal acquisition and generation processing module provided by the utility model. Each chip in the narrowband signal acquisition and generation processing module is powered accordingly as shown in the figure to ensure that the narrowband signal acquisition and generation processing module can work normally.

[0035] As the instruction manual Figure 3 The figure shows a clock tree diagram of the narrowband signal acquisition and generation processing module provided by the present invention. The clock required by each chip in the narrowband signal acquisition and generation processing module is designed to ensure that the narrowband signal acquisition and generation processing module can obtain various clocks required for normal operation.

[0036] The above describes the utility model and its implementation methods, which are not restrictive. The specific implementation method is only one of the implementation methods of the utility model, and the actual structure is not limited thereto. In short, if ordinary technicians in this field are inspired by it, without departing from the purpose of the invention of the utility model, they can design a structure and embodiment similar to the technical solution without creativity, which should belong to the protection scope of the utility model.

Claims

1. A narrowband signal acquisition and generation processing module, characterized in that: It includes a power module, a FSOC module, an FPGA module, a narrowband module, a clock module, a communication module, a Beidou module, an optical module and an external interface unit; the FPGA module, the FSOC module, the narrowband module and the clock module are internally connected for communication; the communication module and the external interface unit are externally connected for communication; the narrowband module includes 3 AD acquisition channels and 2 DA output channels.

2. The narrowband signal acquisition, generation and processing module according to claim 1, characterized in that: The narrowband module is a domestically produced CX9261 chip, which achieves an intermediate frequency of 400MHz output frequency and an intermediate frequency of 350MHz receiving frequency.

3. The narrowband signal acquisition, generation and processing module according to claim 1, characterized in that: The FPGA module is a domestic FPGA chip, and its chip model is JFM7VX690T36; the FPGA module realizes data transmission with the FSOC module through GTH, LVDS, and GPIO interfaces, performs data interaction and clock control; the FPGA module implements the JESD204B protocol through the GTX interface to complete communication and control with the narrowband transceiver chip.

4. The narrowband signal acquisition, generation and processing module according to claim 1, characterized in that: The FSOC module is a domestic SOC chip, and its chip model is FMQL45T900; the SOC chip realizes data communication with external modules through GPIO and SPI interfaces; the SOC chip is connected to the Beidou module through the RS232 interface; the SOC chip is connected to the optical module through the GTX interface; the SOC chip communicates with the external module through 1 GMAC to realize the network port management function.

5. The narrowband signal acquisition, generation and processing module according to claim 1, characterized in that: The communication module is an optical fiber module, and the optical fiber module is connected to the SOC chip to realize data interaction in a 10G network.

6. The narrowband signal acquisition, generation and processing module according to claim 1, characterized in that: The FPGA modules are all configured with a SPI FLASH configuration chip, and the chip model is EFM25QU256; the FSOC module is configured with an EFM25QL256 configuration chip and an EMMC chip FEMDMW032G.

7. The narrowband signal acquisition, generation and processing module according to claim 1, characterized in that: The FPGA module and the FSOC module are both configured with a DDR3 chip, the chip model is HXI15H4G160A, to achieve cache of computing data.

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