BMS (Battery Management System) automatic address allocation system

Abstract

The utility model relates to the technical field of BMS circuits, and discloses a BMS automatic address distribution system, which comprises a plurality of BMS modules, the power supply output ends of the BMS modules are connected in parallel, each BMS module is provided with an IN communication interface and an OUT communication interface, the IN communication interface of the BMS module is connected with the OUT communication interface of another BMS module, and the OUT communication interface of the BMS module is connected with the IN communication interface of the BMS module. The BMS modules are connected in sequence, each BMS module is provided with a CAN communication group, the BMS modules are in communication connection through the CAN communication groups, and the whole BMS modules are accessed to a network; the whole circuit is simple in structure, the BMS modules are connected in series through signals and connected in parallel through CAN communication, the BMS modules can be sequentially configured with IDs, independent configuration and independent use are not needed, automatic networking can be achieved after the number of the BMS modules is increased or decreased, and the networking number is displayed through the LCD display module.

Description

Technical Field

[0001] The utility model relates to the technical field of BMS circuits, in particular to a BMS automatic address allocation system. Background Art

[0002] When multiple BMSs are used in parallel in an energy storage system, CAN bus is used for communication, which requires each BMS module to have a separate ID. However, in actual situations, the factory default ID of each independent module is the same. During networking, each module needs to be individually configured with an ID, and then networked. This places certain limitations and inconveniences on the interchangeability and universality of modules. Utility Model Content

[0003] In view of the deficiencies in the prior art, the utility model aims to provide a BMS automatic address allocation system.

[0004] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0005] A BMS automatic address allocation system includes a plurality of BMS modules, wherein the power supply output terminals of the BMS modules are connected in parallel, each of the BMS modules is provided with an IN communication interface and an OUT communication interface, the IN communication interface of the BMS module is connected to the OUT communication interface of another BMS module, so that each of the BMS modules is connected in sequence, and each of the BMS modules is provided with a CAN communication group, through which the BMS modules are connected for communication and connected to a network as a whole.

[0006] In the present invention, preferably, the BMS module further includes a main control module, the main control module includes a main controller U21, the main controller U21 is communicatively connected to the battery management system of the BMS module, and the main control module is communicatively connected to the CAN communication group.

[0007] In the utility model, preferably, the IN communication interface includes a diode D21, and the two ends of the diode D21 are respectively connected in parallel with a capacitor C32 and a resistor R88, one end of the parallel circuit is connected in series with a resistor R87, and the other end is grounded, an input signal KEY IN signal is connected between the parallel circuit and the resistor R87, and a signal KEY1 signal is connected to the other free end of the resistor R87.

[0008] In the utility model, preferably, the OUT communication interface includes a transistor Q13 and a transistor Q14, the base of the transistor Q13 is connected to a resistor R73, the emitter is grounded, the collector is connected in series with a resistor R76 and a resistor R77, the base of the transistor Q14 is also connected between the resistor R76 and the resistor R77, the emitter of the transistor Q14 is connected to the other end of the resistor R77, the collector of the transistor Q14 is connected in series with a resistor R79 and a diode D20, the free end of the resistor R77 is connected to the power supply output end of the BMS module, the free end of the resistor R73 is connected to the input KEY-OUT signal, and the diode D20 outputs the KEYO signal.

[0009] In the utility model, preferably, the CAN communication group includes an isolator U24 and a communicator U28, ports 2 and 3 of the isolator U24 are connected to ports 33 and 32 of the main controller U21 through resistors R89 and R90 respectively, ports 6 and 7 of the isolator U24 are respectively connected in series with resistors R101 and R102 and then connected to ports 1 and 4 of the communicator U28, a diode D28 and a series branch consisting of capacitors C42 and C43 are connected in parallel between ports 6 and 7 of the communicator U28, and at the same time, pin 6 is connected in series with resistor R112, and pin 7 is connected in series with resistor R113.

[0010] In the present invention, preferably, the resistor R112 and the resistor R113 are further connected in series via a resistor R147.

[0011] In the present utility model, preferably, the CAN communication group also includes a photocoupler U27, and the input end of the photocoupler U27 is connected in series with the resistor R11 and then connected to the ports 6 and 7 of the communicator U28 through the resistor R112 and the resistor R113 respectively, and the output end of the photocoupler U27 is connected to the port 29 of the main controller U21, and is also connected in series with the resistor R106 and then connected to the VCC power supply end.

[0012] In the utility model, preferably, the battery management system includes a manager U2, ports 11, 12 and 13 of the manager U2 are connected to ports 13, 16 and 17 of the main controller U21, ports 2 to 8 of the manager U2 are connected to each corresponding battery through a resistor, and ports 21 and 22 are connected to an overcurrent sampling circuit.

[0013] In the present utility model, preferably, the main control module is also connected to an LCD display module, and pin No. 39 of the main controller U21 is connected in series with a resistor R81 and then connected to the base of a transistor Q15, the collector of the transistor Q15 is connected in series with a fuse F3, and the emitter is grounded.

[0014] Compared with the prior art, the beneficial effects of the utility model are:

[0015] The overall circuit structure of the system of the utility model is simple. By connecting the signals of each BMS module in series and connecting the CAN communication in parallel, each BMS module can be configured with an ID in sequence. There is no need to configure them separately and they can be used independently. After adding or reducing BMS modules, networking can be automatically carried out, and the number of networking can be displayed through the LCD display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a schematic diagram of the external connection structure of a BMS automatic address allocation system described in the utility model.

[0017] Figure 2 The present invention is a structural block diagram of a BMS automatic address allocation system.

[0018] Figure 3 This is a circuit diagram of a main control module of a BMS automatic address allocation system described in the utility model.

[0019] Figure 4 The present invention provides a circuit diagram of an IN communication interface and an OUT communication interface of a BMS automatic address allocation system.

[0020] Figure 5 The utility model discloses a circuit diagram of a CAN communication group of a BMS automatic address allocation system.

[0021] Figure 6 The present invention provides a circuit diagram of a battery management system of a BMS automatic address allocation system. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may also be a component centered. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may also be a component centered. When a component is considered to be "set on" another component, it may be directly set on the other component or there may also be a component centered. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0025] Please also see Figures 1 to 6 A preferred embodiment of the utility model provides a BMS automatic address allocation system, including a plurality of BMS modules, the power supply output ends of the BMS modules are connected in parallel, each of the BMS modules is provided with an IN communication interface and an OUT communication interface, the IN communication interface of the BMS module is connected to the OUT communication interface of another BMS module, so that each of the BMS modules is connected in sequence, that is, the OUT communication interface of the first BMS module is connected to the IN communication interface of the second BMS module, the OUT communication interface of the second BMS module is connected to the IN communication interface of the third BMS module, and so on, the BMS modules are provided with a CAN communication group, through which the BMS modules are connected in communication and connected to the network as a whole.

[0026] Specifically, each of the BMS modules includes a main control module, and the main control module includes a main controller U21. The main controller U21 is communicatively connected to the battery management system of the BMS module, and the main control module is communicatively connected to the CAN communication group.

[0027] Specifically, the IN communication interface includes a diode D21, and the two ends of the diode D21 are also connected in parallel with a capacitor C32 and a resistor R88, one end of the parallel circuit is connected in series with a resistor R87, and the other end is grounded. The input signal KEY IN signal is connected between the parallel circuit and the resistor R87, and the signal KEY1 signal is connected to the other free end of the resistor R87. The KEY IN signal is simultaneously transmitted to pin 42 of the main controller U21. Each BMS module is provided with an IN communication interface. If the BMS module is the first BMS module, the power on / off signal is KEY1. If the BMS module is an intermediate module, the signal output by the previous BMS module is the KEYOUT signal.

[0028] Specifically, the OUT communication interface includes transistors Q13 and Q14, the base of the transistor Q13 is connected to resistor R73, the emitter is grounded, the collector is connected in series with resistors R76 and R77, the base of the transistor Q14 is also connected between resistors R76 and R77, the emitter of the transistor Q14 is connected to the other end of the resistor R77, the collector of the transistor Q14 is connected in series with resistor R79 and diode D20, the free end of the resistor R77 is connected to the power supply output end of the BMS module, the free end of the resistor R73 is connected to the input KEY-OUT signal, the KEY-OUT signal is output by pin 38 of the main controller U21, and the diode D20 outputs the KEYO signal. When the input KEY-OUT signal is high, the transistor Q13 is turned on, and then the transistor Q14 is turned on, and a high-level KEYO signal is output.

[0029] Specifically, the CAN communication group includes an isolator U24 and a communicator U28. Ports 2 and 3 of the isolator U24 are connected to ports 33 and 32 of the main controller U21 through resistors R89 and R90, respectively. Ports 6 and 7 of the isolator U24 are connected in series with resistors R101 and R102, respectively, and then connected to ports 1 and 4 of the communicator U28. A diode D28 and a series branch consisting of capacitors C42 and C43 are connected in parallel between ports 6 and 7 of the communicator U28. At the same time, pin 6 is connected in series with resistor R112, and pin 7 is connected in series with resistor R113.

[0030] Specifically, the resistor R112 and the resistor R113 are further connected in series via a resistor R147, and the resistor R147 is used to improve the anti-interference capability of the communication signal.

[0031] Specifically, the CAN communication group also includes a photocoupler U27. The input end of the photocoupler U27 is connected in series with the resistor R11 and then connected to ports 6 and 7 of the communicator U28 through the resistor R112 and the resistor R113 respectively. The CAN_IN signal at the output end of the photocoupler U27 is connected to port 29 of the main controller U21. When the CAN communication group receives data, the photocoupler U27 sends a signal to the main controller U21 to wake up the main controller U27 from sleep. At the same time, the resistor R106 is connected in series and then connected to the VCC power supply end.

[0032] Specifically, the battery management system includes a manager U2, and ports 11, 12, and 13 of the manager U2 are connected to ports 13, 16, and 17 of the main controller U21, ports 2 to 8 of the manager U2 are connected to each corresponding battery through a resistor, and ports 21 and 22 are connected to an overcurrent sampling circuit. The battery management system adopts an existing multi-string battery management system.

[0033] Specifically, the main control module is also connected to an LCD display module. The No. 39 pin of the main controller U21 is connected in series with a resistor R81 and then connected to the base of a transistor Q15. The collector of the transistor Q15 is connected in series with a fuse F3, and the emitter is grounded. The other end of the fuse F3 is connected to a DC12V signal. When the main control module is working, a high-level LCD signal is output, the transistor Q15 is turned on, the DC12V signal is grounded, and the DC12V signal is connected to the LCD display circuit. When the DC12V signal is grounded, the LCD display works.

[0034] Working principle:

[0035] The KEY signal is the on / off signal output by the wake-up switch, which is input to the IN communication interface of the first BMS module. At this time, the first BMS module is activated, and its battery management system and main control module work. The main control module works by receiving data through the CAN communication group. If the CAN_IN signal is not received within the T0 time, its own ID is modified to 1, and then data is sent through the CAN communication group at the interval of T1, and the main controller U21 outputs the KEY-OUT signal and sets it to a high level, so that the KEYO signal outputs a high level and enters the IN communication interface of the second BMS module, activating the second BMS module. The main control module corresponding to the second BMS module receives the CAN_IN signal on the bus through the CAN communication group within T0, and after receiving the existing ID (i.e. 1), it sends data through the CAN communication group after the ID+1 and sets the KEY-OUT signal to a high level signal, and so on to complete the overall BMS module ID configuration, and finally the maximum ID number stays at the maximum number of the current parallel machine. The overall circuit is simple and easy to implement.

[0036] The above description is a detailed description of the preferred feasible embodiment of the utility model, but the embodiment is not used to limit the scope of the patent application of the utility model. All equivalent changes or modified changes completed under the technical spirit suggested by the utility model should fall within the patent scope covered by the utility model.

Claims

1. A BMS automatic address allocation system, characterized in that: It comprises several BMS modules, the power supply output ends of the BMS modules are connected in parallel, each of the BMS modules is provided with an IN communication interface and an OUT communication interface, the IN communication interface of the BMS module is connected to the OUT communication interface of another BMS module, so that each of the BMS modules is connected in sequence, and the BMS modules are all provided with a CAN communication group, through which the BMS modules are connected for communication and connected to the network as a whole.

2. A BMS automatic address allocation system according to claim 1, characterized in that: The BMS module further includes a main control module, which includes a main controller U21. The main controller U21 is communicatively connected to a battery management system of the BMS module, and the main control module is communicatively connected to the CAN communication group.

3. A BMS automatic address allocation system according to claim 2, characterized in that: The IN communication interface includes a diode D21, and a capacitor C32 and a resistor R88 are respectively connected in parallel at both ends of the diode D21. A resistor R87 is connected in series at one end of the parallel circuit, and the other end is grounded. An input signal KEY IN is connected between the parallel circuit and the resistor R87, and a signal KEY1 is connected to the other free end of the resistor R87.

4. A BMS automatic address allocation system according to claim 1, characterized in that: The OUT communication interface includes a transistor Q13 and a transistor Q14, the base of the transistor Q13 is connected to a resistor R73, the emitter is grounded, the collector is connected in series with a resistor R76 and a resistor R77, the base of the transistor Q14 is also connected between the resistor R76 and the resistor R77, the emitter of the transistor Q14 is connected to the other end of the resistor R77, the collector of the transistor Q14 is connected in series with a resistor R79 and a diode D20, the free end of the resistor R77 is connected to the power supply output end of the BMS module, the free end of the resistor R73 is connected to the input KEY-OUT signal, and the diode D20 outputs the KEYO signal.

5. A BMS automatic address allocation system according to claim 2, characterized in that: The CAN communication group includes an isolator U24 and a communicator U28. Ports 2 and 3 of the isolator U24 are connected to ports 33 and 32 of the main controller U21 through resistors R89 and R90 respectively. Ports 6 and 7 of the isolator U24 are connected in series with resistors R101 and R102 respectively and then connected to ports 1 and 4 of the communicator U28. A diode D28 and a series branch consisting of capacitors C42 and C43 are connected in parallel between ports 6 and 7 of the communicator U28. At the same time, pin 6 is connected in series with resistor R112, and pin 7 is connected in series with resistor R113.

6. A BMS automatic address allocation system according to claim 5, characterized in that: The resistor R112 and the resistor R113 are further connected in series via a resistor R147.

7. A BMS automatic address allocation system according to claim 6, characterized in that: The CAN communication group also includes a photocoupler U27, the input end of the photocoupler U27 is connected in series with a resistor R11 and then connected to ports 6 and 7 of the communicator U28 through resistors R112 and R113 respectively, the output end of the photocoupler U27 is connected to port 29 of the main controller U21, and is connected in series with a resistor R106 and then connected to a VCC power supply end.

8. The BMS automatic address allocation system according to claim 2, characterized in that: The battery management system includes a manager U2, ports 11, 12 and 13 of the manager U2 are connected to ports 13, 16 and 17 of the main controller U21, ports 2 to 8 of the manager U2 are connected to each corresponding battery through a resistor, and ports 21 and 22 are connected to an overcurrent sampling circuit.

9. The BMS automatic address allocation system according to claim 2, characterized in that: The main control module is also connected to an LCD display module. Pin 39 of the main controller U21 is connected in series with a resistor R81 and then connected to the base of a transistor Q15. The collector of the transistor Q15 is connected in series with a fuse F3, and the emitter is grounded.

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