CTOLC calculation module

Abstract

The utility model provides a CTOLC calculation module. The CTOLC calculation module comprises a Loongson 3A5000 four-core processor, a bridge chip, a DDR4 memory unit, an Ethernet physical layer chip group, a CPLD chip, a CTOLC connector and a display signal conversion chip group, by carrying a Loongson 3A5000 four-core high-performance processor and onboard DDR4 industrial-grade memory particles, a high-performance computer and high-speed data storage can be realized, different display outputs can be realized through a display signal conversion chip, and a high-speed network communication function is realized by a CTOLC calculation module through the action of an Ethernet physical layer chip and a bridge chip. And multiple types of standard interfaces are provided for the outside, and the CPLD chip is used for power management, so that the stability and reliability of the power-on sequence of each chip can be effectively ensured.

Description

Technical Field

[0001] The utility model relates to the field of computer technology, and in particular to a CTOLC computing module. Background Art

[0002] With the development of equipment miniaturization and the increase in system transmission rate, there are more and more high-speed, surface mount connectors used between parallel printed circuit boards, and the demand for such connectors in related industries is also increasing. In order to meet the interconnection needs between printed circuit boards in low-power, miniaturized equipment components, AVIC Optronics has launched the CTOLC / CSOLC series of rectangular four-row surface mount high-speed connectors. This series of products is a benchmark product for high-precision, high-speed surface mount connectors, which serves as a signal connection and has a transmission rate of up to 10Gbps. It can be widely used in aviation, aerospace, ground support and ship electrical and electronic equipment. The CTOLC / CSOLC series connectors have a contact spacing of 1.27mm×1.27mm, and can be installed between parallel printed circuit boards for high-speed data transmission, and are compatible with parallel printed circuit board systems with a board spacing of 6.35mm to 12mm. Therefore, due to the advantages of CTOLC / CSOLC series connectors such as high precision and high speed, some computing modules often use CTOLC connectors to achieve external connections, but the CTOLC-based computing modules in related technologies usually use older processors such as Intel Atom processors and Intel Celeron processors, which cannot meet the needs of modern applications for high-performance computing. Therefore, it is necessary to design a universal CTOLC computing module that can achieve high-performance computing, data storage and high-speed network communication. Utility Model Content

[0003] The utility model provides a CTOLC computing module, aiming to solve the problem in the related art that the general CTOLC computing module adopts an older processor and cannot meet the high-performance computing requirements.

[0004] In order to solve the above technical problems, the utility model provides a CTOLC computing module, including: a Loongson 3A5000 quad-core processor, a bridge chip, a DDR4 memory unit, an Ethernet physical layer chipset, a CPLD chip, a CTOLC connector and a display signal conversion chipset; the bridge chip is electrically connected to the Loongson 3A5000 quad-core processor and the CTOLC connector respectively, the DDR4 memory unit is electrically connected to the Loongson 3A5000 quad-core processor, the CPLD chip is electrically connected to the Loongson 3A5000 quad-core processor, the bridge chip and the CTOLC connector respectively, and the Ethernet physical layer chipset and the display signal conversion chipset are electrically connected to the CTOLC connector and the bridge chip respectively.

[0005] Furthermore, the display signal conversion chipset includes an ADV7125 chip and a GM8285C chip.

[0006] Furthermore, the DDR4 memory unit includes a first DDR4 chip, a second DDR4 chip, a third DDR4 chip and a fourth DDR4 chip.

[0007] Furthermore, it also includes a reset control circuit, which is electrically connected to the bridge chip and the CTOLC connector respectively.

[0008] Furthermore, it also includes an SM3232 chip, and the SM3232 chip is electrically connected to the bridge chip and the CTOLC connector respectively.

[0009] Furthermore, it also includes a second memory unit and a memory, and the second memory unit and the memory are both electrically connected to the bridge chip.

[0010] Furthermore, the Ethernet physical layer chipset includes a first Ethernet physical layer chip and a second Ethernet physical layer chip.

[0011] From the above description, it can be seen that the CTOLC computing module of the present invention is equipped with a Loongson 3A5000 quad-core high-performance processor and onboard DDR4 industrial-grade memory particles, which can realize high-performance computers and high-speed data storage. Different display outputs can be achieved through the display signal conversion chip. Through the Ethernet physical layer chip and the bridge chip, the CTOLC computing module can realize high-speed network communication functions and provide multiple types of standard interfaces to the outside world. The CPLD chip performs power management, which can effectively ensure the stability and reliability of the power-on timing of each chip. Therefore, based on the CTOLC computing module of the present invention, secondary design such as computing systems, communication systems, and terminal office systems is carried out. Compared with the older processors used in related technologies, it has the advantages of high flexibility, high performance, and high stability, and can better meet the needs of high-performance computing scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural schematic diagram of a CTOLC calculation module of an embodiment of the utility model;

[0013] Figure 2 It is a structural schematic diagram of another CTOLC calculation module of an embodiment of the utility model;

[0014] Figure 3 This is a schematic diagram of the connection between a DDR4 memory unit and a Loongson 3A5000 quad-core processor according to an embodiment of the present utility model;

[0015] Figure 4 It is a structural schematic diagram of a reset control circuit of an embodiment of the utility model. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical scheme and advantages of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. It should be understood that the specific embodiments described herein are only used to explain the utility model and are not used to limit the utility model. In addition, the technical features involved in the various embodiments of the utility model described below can be combined with each other as long as they do not conflict with each other.

[0017] In the related art, there is a problem that the CTOLC computing module uses an older processor and cannot meet the high-performance computing requirements. Therefore, an embodiment of the utility model provides a CTOLC computing module.

[0018] like Figure 1 The figure shows a schematic diagram of the structure of a CTOLC computing module provided by an embodiment of the utility model, the CTOLC computing module includes: a Loongson 3A5000 quad-core processor 100, a bridge chip 200, a DDR4 memory unit 300, an Ethernet physical layer chipset 400, a CPLD chip 500, a CTOLC connector 600 and a display signal conversion chipset 700; the bridge chip 200 is electrically connected to the Loongson 3A5000 quad-core processor 100 and the CTOLC connector 600, respectively, the DDR4 memory unit 300 is electrically connected to the Loongson 3A5000 quad-core processor 100, the CPLD chip 500 is electrically connected to the Loongson 3A5000 quad-core processor 100, the bridge chip 200 and the CTOLC connector 600, respectively, and the Ethernet physical layer chipset 400 and the display signal conversion chipset 700 are electrically connected to the CTOLC connector 600 and the bridge chip 200, respectively.

[0019] Among them, the bridge chip 200 is the Loongson 7A1000 bridge chip. The Loongson 7A1000 bridge chip 200 is connected to the Loongson 3A5000 quad-core processor 100 through the HT high-speed bus interface, and the width of the HT high-speed bus interface works in 16-bit mode. The HT high-speed bus can be an HT1 high-speed bus. The 1-way PCIE x8, 5-way PCIE x4, and 4-way PCIE x1 interfaces of the Loongson 7A1000 bridge chip 200 are connected to the CTOLC connector 600. In addition, an HDA (high-resolution audio) interface, a USB2.0 interface, a SATA2.0 interface, an IIC interface, and an LPC interface are also provided to the outside. In addition, the Loongson 7A1000 bridge chip 200 is integrated with GMAC (Gigabit Ethernet Media Access Control), and Ethernet functions can be realized by simply connecting an external Ethernet physical layer (PHY) chip; the Ethernet physical layer chipset 400 of this embodiment includes a first Ethernet physical layer chip and a second Ethernet physical layer chip, and the MAC1 and MAC2 of the Loongson 7A1000 bridge chip 200 respectively lead out 1000base-T interfaces to the CTOLC connector 600 through the PHY chip, and the PHY chip can use the Yutaiwei YT8521SH; for applications with more network interface requirements, it can be connected to the network card through the PCIE bus.

[0020] Specifically, in this embodiment, the CTOLC computing module is equipped with a Loongson 3A5000 quad-core high-performance processor and onboard DDR4 industrial-grade memory particles, which can realize high-performance computers and high-speed data storage. Different display outputs can be achieved through the display signal conversion chip. Through the Ethernet physical layer chip and the bridge chip, the CTOLC computing module can realize high-speed network communication functions and provide multiple types of standard interfaces to the outside world. The CPLD chip performs power management, which can effectively ensure the stability and reliability of the power-on timing of each chip. Therefore, the CTOLC computing module based on this embodiment can be used for secondary design of computing systems, communication systems, and terminal office systems. Compared with the older processors used in related technologies, it has the advantages of high flexibility, high performance, and high stability, and can better meet the needs of high-performance computing scenarios.

[0021] like Figure 2 FIG. 1 is a schematic diagram of the structure of another CTOLC computing module provided in this embodiment. Figure 2 , the DDR4 memory unit 300 includes a first DDR4 chip, a second DDR4 chip, a third DDR4 chip and a fourth DDR4 chip.

[0022] Specifically, the Loongson 3A5000 quad-core processor 100 in this embodiment is equipped with four 16-bit data line 1GB memory chips, forming a group of 64-bit data line 4GB DDR4 cache, and the memory chips can be CXDQ3BFAM-WG from Hefei Changxin. The connection relationship between the DDR4 memory unit 300 and the Loongson 3A5000 quad-core processor 100 is as follows: Figure 3 shown.

[0023] For further information, see Figure 2 , the display signal conversion chipset 700 includes an ADV7125 chip and a GM8285C chip.

[0024] Specifically, the display controller of the Loongson 7A1000 bridge chip 200 in this embodiment takes out the frame buffer and cursor information from the video memory to output to the external display interface. The display controller of 7A1000 supports dual-channel DVO interface display, and each display supports a maximum of 1920x1080@60Hz (can also support 1600x1200@60Hz); in order to provide VGA and LVDS display outputs, the DVO interface of the 7A1000 bridge chip 200 can be converted by connecting a display signal conversion chip. The DVO0 interface of this embodiment converts the DVO signal into a VGA signal through the ADV7125 chip 710, and the DVO1 interface converts the DVO signal into a LVDS differential signal through the GM8285C chip 720.

[0025] For further information, see Figure 2 The CTOLC computing module also includes an SM3223 chip, which is electrically connected to the bridge chip 200 and the CTOLC connector 600. In addition, the CTOLC computing module also includes a DDR3 memory unit, a memory, and a baseboard management controller, which are electrically connected to the bridge chip 200, and the baseboard management controller is electrically connected to the bridge chip and the CTOLC connector.

[0026] Specifically, in this embodiment, the UART interface of the Loongson 7A1000 bridge chip 200 converts the UART interface level through the SM32323 chip. The Loongson 7A1000 bridge chip 200 also mounts DDR3 memory particles and is connected to the Flash memory through the SPI interface. The baseboard management controller (Baseboard Management Controller, BMC) is also connected to the CTOLC connector through the Ethernet physical layer chip. The BMC can be used to monitor the system's temperature, voltage and other parameters, and provide remote access and control functions, so that the administrator can remotely manage the system through a network connection to improve the system's reliability and manageability.

[0027] like Figure 4FIG. 1 is a schematic diagram of a reset control circuit provided in this embodiment. Figure 4 The CTOLC computing module also includes a reset control circuit, which is electrically connected to the bridge chip and the CTOLC connector. The reset control circuit also includes a buffer, which is electrically connected to the bridge chip.

[0028] Specifically, the reset control circuit includes a first AND gate circuit, a first reset chip, a watchdog circuit WCHDG and a watchdog enable circuit. The first AND gate circuit is electrically connected to the watchdog circuit WCHDG and the CTOLC connector 600, and is used to be electrically connected to an external reset button. The first reset chip is electrically connected to the first AND gate circuit and the bridge chip 200, and the Loongson 3A5000 quad-core processor 100 is electrically connected to the watchdog circuit WCHDG and the watchdog enable circuit. The watchdog enable circuit includes a second AND gate circuit and a second reset chip. The second AND gate circuit is electrically connected to the first reset chip and the bridge chip, and the second reset chip is electrically connected to the second AND gate circuit and the Loongson 3A5000 quad-core processor.

[0029] In this embodiment, the 12V, 5V and P5VSB power supplies of the system are generally provided by the ATX power supply through the backplane, and other power supplies required on the board are provided by the switching power supply or LDO according to the required current. When the power module on the board outputs normally, a 7A_PWROK signal will be generated to the ACPI_PWROK pin of the 7A1000 bridge chip. When any of the control signals output by the watchdog circuit, the _RSTn signal input by the CTOLC connector (which can be transmitted through the CPLD chip) and the signal input by the external reset button are activated, an ACPI_SYSRSTn signal is generated after passing through the first AND gate circuit and the first reset chip and input to the ACPI_SYSRSTn pin of the 7A1000 bridge chip. The 7A1000 bridge chip will then generate a platform reset signal ACPI_PLTRSTn, and the ACPI_PLTRSTn signal will be distributed to each chip connected to the bridge chip in the system through the buffer Buffer. In addition, the watchdog circuit can be enabled by the main processor, namely the Loongson 3A5000 quad-core processor. The Loongson 3A5000 processor controls the watchdog circuit to be enabled according to the CPU_SYSRSTn signal generated by the second reset chip. The second reset chip generates a CPU_SYSRSTn signal when any of the ACPI_SYSRSTn signal generated by the first reset chip, the ACPI_PLTRSTn signal generated by the 7A1000 bridge chip, and the CPU_PWROK signal generated by the power module is at a low level.

[0030] The CTOLC computing module provided by the embodiment of the utility model is equipped with a Loongson 3A5000 quad-core high-performance processor and onboard DDR4 industrial-grade memory particles, which can realize high-performance computers and high-speed data storage. Different display outputs can be realized through the display signal conversion chip. Through the Ethernet physical layer chip and the bridge chip, the CTOLC computing module realizes high-speed network communication functions and provides multiple types of standard interfaces to the outside. The CPLD chip performs power management, which can effectively ensure the stability and reliability of the power-on timing of each chip. Therefore, the CTOLC computing module based on this embodiment is used for secondary design such as computing systems, communication systems, and terminal office systems. Compared with the use of older processors in related technologies, it has the advantages of high flexibility, high performance, and high stability, and better meets the needs of high-performance computing scenarios. The embodiment of the utility model can also be domestically produced and self-controlled.

[0031] It should be noted that the various embodiments in the present invention are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0032] It should also be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0033] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the present invention may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in the present invention, but will conform to the widest range consistent with the principles and novel features disclosed in the present invention.

Claims

1. A CTOLC calculation module, characterized in that: include: Loongson 3A5000 quad-core processor, bridge chip, DDR4 memory unit, Ethernet physical layer chipset, CPLD chip, CTOLC connector and display signal conversion chipset; The bridge chip is electrically connected to the Loongson 3A5000 quad-core processor and the CTOLC connector respectively, the DDR4 memory unit is electrically connected to the Loongson 3A5000 quad-core processor, the CPLD chip is electrically connected to the Loongson 3A5000 quad-core processor, the bridge chip and the CTOLC connector respectively, and the Ethernet physical layer chipset and the display signal conversion chipset are electrically connected to the CTOLC connector and the bridge chip respectively.

2. The CTOLC calculation module according to claim 1, characterized in that: The display signal conversion chipset includes an ADV7125 chip and a GM8285C chip.

3. The CTOLC calculation module according to claim 1, characterized in that: The DDR4 memory unit includes a first DDR4 chip, a second DDR4 chip, a third DDR4 chip and a fourth DDR4 chip.

4. The CTOLC calculation module according to claim 1, characterized in that: It also includes a reset control circuit, which is electrically connected to the bridge chip and the CTOLC connector respectively.

5. The CTOLC calculation module according to claim 4, characterized in that: The reset control circuit includes a first AND gate circuit, a first reset chip, a watchdog circuit and a watchdog enable circuit. The first AND gate circuit is electrically connected to the watchdog circuit and the CTOLC connector, respectively, and is used to be electrically connected to an external reset button. The first reset chip is electrically connected to the first AND gate circuit and the bridge chip, respectively, and the Loongson 3A5000 quad-core processor is electrically connected to the watchdog circuit and the watchdog enable circuit, respectively.

6. The CTOLC calculation module according to claim 5, characterized in that: The watchdog enabling circuit includes a second AND gate circuit and a second reset chip. The second AND gate circuit is electrically connected to the first reset chip and the bridge chip respectively. The second reset chip is electrically connected to the second AND gate circuit and the Loongson 3A5000 quad-core processor respectively.

7. The CTOLC calculation module according to claim 4, characterized in that: The reset control circuit further includes a buffer, and the buffer is electrically connected to the bridge chip.

8. The CTOLC calculation module according to claim 1, characterized in that: It also includes an SM3232 chip, which is electrically connected to the bridge chip and the CTOLC connector respectively.

9. The CTOLC calculation module according to claim 1, characterized in that: It also includes a DDR3 memory unit, a storage device and a baseboard management controller. The DDR3 memory unit and the storage device are electrically connected to the bridge chip, and the baseboard management controller is electrically connected to the bridge chip and the CTOLC connector respectively.

10. The CTOLC calculation module according to any one of claims 1 to 9, characterized in that: The Ethernet physical layer chipset includes a first Ethernet physical layer chip and a second Ethernet physical layer chip.

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