Image processing chip test platform based on FPGA

Abstract

The utility model relates to the field of testing after chip returning, and discloses an image processing chip testing platform based on an FPGA (Field Programmable Gate Array), which comprises a UART (Universal Asynchronous Receiver / Transmitter) upper computer, the FPGA, an image processor chip and an LCD (Liquid Crystal Display) screen, the UART upper computer is electrically connected with the FPGA; the FPGA comprises a PS end and a PL end; the PL end comprises an SPI (Serial Peripheral Interface) read interface and an SPI write interface; the image processor chip comprises an SPI (Serial Peripheral Interface); the PS end comprises a register value reading circuit and a register value writing circuit; and the FPGA is electrically connected with the LCD display screen. The utility model provides a circuit design for a chip return test, which is used for accelerating data reading, transmission and analysis so as to verify the correctness and effectiveness of chip design and evaluate performance indexes and power consumption performance. And the design reliability of the chip can be detected, and potential problems of design and manufacturing, such as short circuit, open circuit and logic errors, can be found.

Description

Technical Field

[0001] The utility model relates to the field of chip testing after chip return, in particular to an image processing chip testing platform based on FPGA. Background Art

[0002] With the continuous development of the chip industry, chip re-wafer testing has become a key step to ensure product quality and reliability. This process not only verifies the correctness of the design, but also evaluates the performance and power consumption of the chip, providing an important basis for the mass production stage. After the chip is manufactured, re-wafer testing is the first key step. The main purpose of this stage of testing is to verify whether the basic functions and performance indicators of the chip meet the design requirements. Through this series of tests, it can be ensured that each chip can meet the expected working standards and prevent unqualified products from entering the market.

[0003] Electrical performance testing is an important part of wafer return testing. During this process, engineers measure the electrical characteristics of the chip under different working conditions, such as input and output voltage, current, and power consumption. These data are not only used to verify the design specifications of the chip, but also provide a basis for subsequent optimization.

[0004] Functional testing is more specific and verifies each module of the chip in detail. For example, digital logic circuits, analog circuits, communication interfaces and other functional modules will undergo rigorous testing to ensure that they can work properly according to the design specifications. This step is especially important for complex chips, because any small error may cause the entire system to fail.

[0005] Timing testing focuses on the propagation time of signals inside the chip. High-speed communications and timing-sensitive applications are particularly important. Through timing testing, it can be ensured that there will be no errors when the chip is running at high speed, ensuring the accuracy of data transmission.

[0006] Temperature testing is to test the chip under different temperature conditions to evaluate its performance stability in different environments. This is especially important for chips that need to work in different temperature ranges, such as chips in automotive electronics and industrial automation equipment.

[0007] Reliability tests include thermal stress tests, electrostatic discharge tests, and temperature cycle tests, etc. These tests simulate various extreme conditions that the chip may encounter in actual applications to ensure that it can still operate stably in harsh environments.

[0008] The communication performance test is specifically aimed at communication chips to verify their communication performance with other devices and ensure the accuracy and reliability of data transmission.

[0009] Chip return testing is a complex and comprehensive process, covering multiple aspects from basic function verification to performance evaluation, timing analysis, temperature adaptability and reliability testing. Through these rigorous tests, we ensure that each chip can meet high quality requirements and provide a solid guarantee for the reliability of the final product. Utility Model Content

[0010] To solve the existing problems, the utility model provides an image processing chip testing platform based on FPGA, the purpose of which is to provide a circuit design for chip re-testing, which is used to verify the correctness of chip design and confirm whether the chip works as expected, so as to ensure the effectiveness of the design; the second purpose is to evaluate performance indicators. In the re-testing, engineers will measure the electrical characteristics of the chip under different working conditions, such as input and output voltage, current and power consumption, etc., to verify the design specifications of the chip and provide a basis for subsequent optimization; the third purpose is to detect potential problems through comprehensive testing, and find problems in chip design and manufacturing, such as circuit short circuit, open circuit, logical error, etc., which are helpful to repair in time to improve the reliability of the chip; the fourth purpose is to evaluate the power consumption performance, obtain the actual test power consumption of the chip, and compare it with the power consumption target to determine whether it meets the power consumption requirements.

[0011] In order to achieve the above-mentioned purpose, the utility model provides the following technical solutions.

[0012] A test platform for image processing chip based on FPGA, 1. A test platform for image processing chip based on FPGA, characterized in that it comprises a UART host computer, an FPGA, an image processor chip and an LCD display screen; the UART host computer is electrically connected to the FPGA; the FPGA comprises a PS end and a PL end; the PL end comprises an SPI read interface and an SPI write interface; the image processor chip comprises an SPI interface; the PS end comprises a read register value circuit and a write register value circuit; the read register value circuit comprises a UART parallel data protocol parsing module, an SPI register write mode module, an spi_wr_mux module and an SPI parallel-to-serial module in sequence; the SPI parallel-to-serial module is electrically connected to the SPI write interface of the PL end, and the SPI write interface is electrically connected to the SPI interface of the image processor chip; the write register value circuit comprises an SPI serial-to-parallel module, an spi_rd_mux module connection, an SPI read image data value module, a data_wr_mux module and a parallel data to AXI protocol write module in sequence, and the SPI serial-to-parallel module is electrically connected to the SPI read interface of the PL end; the SPI read interface is electrically connected to the SPI interface of the image processor chip; the FPGA is electrically connected to the LCD display screen.

[0013] As a further improvement of the present invention, the PS end also includes a UART receiving serial-to-parallel module; the UART receiving serial-to-parallel module is electrically connected to the UART parallel data protocol analysis module; the UART parallel data protocol analysis module also includes an SPI register reading mode module and an SPI configuration windowing mode module, the SPI register reading mode module and the SPI configuration windowing mode module are respectively electrically connected to the spi_wr_mux module, and the spi_wr_mux module is electrically connected to the UART parallel data protocol analysis module.

[0014] As a further improvement of the present utility model, the UART parallel data protocol parsing module is electrically connected to the data_wr_mux module.

[0015] As a further improvement of the utility model, the PL end also includes an AXI protocol write interface, an AXI protocol read interface, an AXI InterConnect, an SRAM memory, a DMA read module, a Local_bus module and an image timing generation module; the parallel data to AXI protocol write module is electrically connected to the AXI protocol write interface of the PL end through an AXI_WR transmission channel to transmit image data in AXI format; the AXI InterConnect is electrically connected to the AXI protocol write interface; the AXIInterConnect is electrically connected to the Local_bus module; the AXI InterConnect is electrically connected to the SRAM memory module; the DMA read module is electrically connected to the AXI InterConnect through an AXI_RD transmission channel; the DMA read module is electrically connected to the Local_bus module; the DMA read module is electrically connected to the image timing generation module.

[0016] As a further improvement of the present utility model, the PS end also includes an AXI data reading module and an LCD screen driving module; the AXI data reading module is electrically connected to the AXI protocol reading interface through an AXI_RD transmission channel; and the UART parallel data protocol parsing module is electrically connected to the AXI data reading module.

[0017] As a further improvement of the present invention, the AXI protocol read interface is electrically connected to the AXI InterConnect; and the AXI data read module is electrically connected to the LCD liquid crystal screen drive module.

[0018] As a further improvement of the present invention, the LCD liquid crystal screen driving module is electrically connected to the LCD display screen.

[0019] As a further improvement of the utility model, the PS end also includes a UART sending parallel-to-serial module; the spi_rd_mux module is electrically connected to the UART parallel data protocol analysis module; the spi_rd_mux module is electrically connected to the SPI read register value module; the SPI read register value module is connected to the UART sending parallel-to-serial module to return the SPI read register value to the UART host computer.

[0020] As a further improvement of the present invention, the UART sending parallel-to-serial module is connected to the UART sending parallel-to-serial module through a UART_TX transmission channel to transmit data to the UART host computer.

[0021] As a further improvement of the utility model, the PS end also includes a UART sending serial-to-parallel module; the UART host computer is connected to the UART sending serial-to-parallel module through a UART_RX transmission channel to receive the image data to be processed transmitted by the serial-to-parallel module to the UART host computer.

[0022] The utility model has the following beneficial effects:

[0023] The read register value circuit sends the read target, that is, the first address of the data in the image processor chip and the length value of the memory data, through the UART host computer. The PS end of the FPGA converts the UART protocol instructions into SPI protocol instructions, and then sends them to the image processor chip through the SPI write interface of the PL end of the FPGA. The image processor chip parses the corresponding instructions; the write register value circuit transmits the data on the corresponding address to the PL end of the FPGA through the SPI interface. The PL end of the FPGA transmits the received SPI instructions to the PS end of the FPGA to parse the SPI instructions and convert them into AXI protocol instructions, and write them to the FPGA through the AXI interface. SRAM memory; this method is effective and flexible, allowing users to read any area and any size of the internal memory of the image processor chip, and by converting the instructions of the SPI protocol into the instructions of the AXI protocol, the data throughput rate can be accelerated, and the convenience of users to the target data inside the image processor chip is improved; by integrating multiple functional modules, the accelerator can efficiently process image data; through the UART receiving serial-to-parallel module, the serial image data received by the UART host computer can be converted into parallel data; through modular design, the read and write operations of the SPI register can be flexibly controlled, and the window mode can be configured, thereby realizing precise control of the image processor chip.

[0024] Preferably, through the SPI register read mode module, the SPI register write mode module and the SPI configuration window mode module, the image processor chip can be flexibly configured and controlled, and the data reading and writing operations are optimized; parallel data can be quickly parsed and processed through different paths according to the data content, thereby improving the efficiency of data processing.

[0025] Preferably, the UART parallel data protocol parsing module is electrically connected to the data_wr_mux module, and is used to issue control instructions to the data_wr_mux module.

[0026] Preferably, the PL end realizes digital circuit functions and high-speed data transmission, and the PL end has high flexibility and reconfigurability, and can be customized and optimized according to different application scenarios and requirements; through the use of the AXI protocol, the data exchange capability between the FPGA and the image processor chip is enhanced, and the data throughput and processing speed are improved; the Local_bus module adopts a parallel transmission method, which means that multiple data bits can be transmitted in a single clock cycle. This transmission method significantly improves the data transmission rate, allowing the system to process data faster; the DMA read module realizes direct data transmission between memory and peripherals or between memory and memory. Since DMA transmission does not require real-time intervention of the CPU, it can greatly reduce the burden on the CPU; through the AXI protocol interface and AXI InterConnect, high-speed and efficient data transmission and storage can be achieved, which improves the overall performance and stability of the system; the combination of SPI transmission and AXI transmission is suitable for high and low-speed transmission requirements; by simultaneously supporting communication with other devices such as UART host computer and LCD display, the flexibility, scalability and visibility of the system are improved.

[0027] Preferably, the UART parallel data protocol analysis module can read the data written into the SRAM memory and the Local_bus module to perform data protocol analysis.

[0028] Preferably, the AXI protocol read interface can read out the AXI data written into the SRAM memory and the Local_bus module, and transmit it to the LCD liquid crystal screen driver module for the LCD display screen to display images.

[0029] Preferably, the LCD display screen is used to display images based on the data signals transmitted by the LCD liquid crystal screen driving module.

[0030] Preferably, the spi_rd_mux module can selectively transmit the received data to one or more output channels through configuration and control; this multiplexing function enables the system to process data from multiple peripherals simultaneously, thereby improving communication efficiency and data processing flexibility.

[0031] Preferably, the UART sending and serial conversion module can transmit the processed data back to the UART host computer, so that the user can obtain the processing results or perform further analysis.

[0032] Preferably, by defining a well-defined UART_RX transmission channel, the orderly flow of data within and outside the system is ensured, simplifying the complexity of data management. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are only for explanation purposes and are not intended to limit the scope of the present invention in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only for illustration purposes to help understand the present invention and are not intended to specifically limit the shapes and proportional dimensions of the components of the present invention. In the drawings:

[0034] Figure 1 A logic schematic diagram of an FPGA-based image processing chip testing platform according to an embodiment;

[0035] Figure 2 This is a module connection diagram of an FPGA-based image processing chip testing platform described in an embodiment. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only embodiment.

[0038] Except for some terms defined below, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0039] UART (Universal Asynchronous Receiver / Transmitter): A widely used serial communication protocol for data transmission between devices such as computers or microcontrollers.

[0040] ‌FPGA (Field-Programmable Gate Array) Field Programmable Gate Array‌: An integrated circuit with programmable logic elements and programmable interconnects, whose logic functions can be configured by the user as needed.

[0041] ‌PS side (Processing System): In FPGA, it refers to the part that contains the processor core (such as ARM core), which is used to perform control, data processing and other tasks.

[0042] ‌PL (Programmable Logic): In FPGA, it refers to the user-programmable logic part used to implement specific hardware functions.

[0043] SPI (Serial Peripheral Interface): A synchronous serial communication protocol commonly used for communication between microcontrollers and external devices (such as sensors, memory, etc.).

[0044] ‌AXI (Advanced eXtensible Interface): An on-chip bus protocol proposed by ARM for efficiently transmitting data within FPGA or SoC (system-on-chip).

[0045] ‌SRAM (Static Random-Access Memory): A type of memory that is able to retain stored data without the need for refresh circuits.

[0046] ‌LCD display (Liquid Crystal Display): A flat display device used to display images, made of liquid crystal material.

[0047] DMA (Direct Memory Access): A technology that allows a hardware subsystem to directly access main memory without CPU intervention, thereby improving data transfer efficiency.

[0048] ‌AXI Interconnect‌: In the AXI bus system, the interconnect structure used to connect multiple AXI master devices and slave devices to achieve efficient data transmission.

[0049] ‌Local_bus module‌: A bus structure used to implement local data transmission within the FPGA.

[0050] Image timing generation module: used to generate timing signals required for image processing or display, such as frame synchronization signals, line synchronization signals, etc.

[0051] RD (Read): Read.

[0052] WR (Write): Write.

[0053] Mux (Multiplexer): Multiplexer.

[0054] In addition, the article also mentions several modules and interfaces related to specific implementations, such as "UART receive serial-to-parallel module", "UART parallel data protocol parsing module", "parallel data to AXI protocol write module", "SPI parallel-to-serial module", "data_wr_mux module", "data_wr_mux module", "AXI_RD transmission channel", etc. These modules and interfaces have clear context descriptions in the article, and all have corresponding devices and structures to implement specific data processing and transmission functions.

[0055] like Figure 1As shown, an image processing chip test platform based on FPGA includes a UART host computer, an FPGA, an image processor chip and an LCD display screen; the UART host computer is electrically connected to the FPGA; the FPGA includes a PS end and a PL end electrically connected to the PS end; the PS end or the PL end is electrically connected to the LCD display screen. The UART host computer sends the read target, that is, the first address of the data in the image processor chip and the size of the read memory, the PS end of the FPGA converts the instruction of the UART protocol into the instruction of the SPI protocol, and then sends it to the image processor chip through the SPI write interface of the PL end of the FPGA, the image processor chip parses the corresponding instruction inside, and then transmits the data on the corresponding address to the PL end of the FPGA through the SPI interface, the PL end of the FPGA transmits the received SPI instruction to the PS end of the FPGA, so as to parse the SPI instruction and convert it into the instruction of the AXI protocol, and write it to the SRAM memory of the FPGA through the AXI interface; this method is effective and flexible, and can facilitate users to read any area and any size of the internal memory of the image processor chip, and by converting the instruction of the SPI protocol into the instruction of the AXI protocol, the data throughput rate can be accelerated, and the convenience of users to the target data inside the image processor chip is improved.

[0056] In this embodiment, the image processor chip is a customized image processing accelerator chip, and may also be a general image processing chip including an SPI read / write interface.

[0057] Specifically, Figure 2As shown, the present embodiment describes an FPGA-based image processing chip test platform, including a UART host computer, an FPGA, an image processor chip and an LCD display screen; the UART host computer is electrically connected to the FPGA to realize data transmission, system control, debugging and diagnosis; the FPGA includes a PS end and a PL end; the PS end is electrically connected to the PL end; the PS end includes a UART receiving serial-to-parallel module, a UART parallel data protocol parsing module, an SPI register read mode module, an SPI register write mode module, an SPI configuration window mode module, a spi_wr_mux module, an SPI parallel-to-serial module, a data_wr_mux module, a parallel data to AXI protocol write module, an SPI read image data value module, a spi_rd_mux module, an SPI serial-to-parallel module, an SPI read register value module, an AXI data read module, an LCD liquid crystal screen driver module and a UART sending parallel-to-serial module; the PL end includes an SPI write interface, an SPI read interface, an AXI protocol write interface, an AXI protocol read interface, an AXI Interconnect, an SRAM memory, a Local_bus module, a DMA module, an image timing generation module; the AXI Interconnect includes S0, M0, S1 and M1 interfaces.

[0058] The PL terminal is electrically connected to the image processor chip; the PS terminal is electrically connected to the LCD display screen.

[0059] The UART parallel data protocol parsing module is electrically connected to the UART receiving serial-to-parallel module; the UART parallel data protocol parsing module is electrically connected to the spi_wr_mux module through the SPI register read mode module, the SPI register write mode module and the SPI configuration window mode module respectively; the spi_wr_mux module is also electrically connected to the UART parallel data protocol parsing module; the spi_wr_mux module selects and merges the received parsing instructions and control instructions, and sends a write data signal to the SPI parallel-to-serial module.

[0060] The UART host computer is connected to the UART_RX transmission channel to receive the image data to be processed transmitted by the serial-to-parallel module to the UART host computer.

[0061] The UART parallel data protocol parsing module is electrically connected to the data_wr_mux module.

[0062] The UART receiving serial-to-parallel module is divided into two data paths, wherein the first data path is the connection between the received serial UART data and the UART host computer, and the second data path is the connection between the serial UART data received by the module and the parallel data after being converted to the UART parallel data protocol analysis module.

[0063] The UART parallel data protocol parsing module is divided into 8 data paths, among which the first data path control instruction 1 is connected to the spi_wr_mux module, the second data path parsing instruction 1 is connected to the SPI register read mode module, the third data path parsing instruction 2 is connected to the SPI register write mode module, the fourth data path parsing instruction 3 is connected to the SPI configuration window mode module, the SPI register read mode module, the SPI register write mode module, and the SPI configuration window mode module are respectively connected to the spi_wr_mux module, the spi_wr_mux module is connected to the SPI parallel-to-serial module, the SPI parallel-to-serial module is connected to the SPI write interface, the fifth control instruction 2 and the sixth data path parsing instruction 4 are connected to the data_wr_mux module, the seventh data path parsing instruction 5 is connected to the spi_rd_mux module, and the eighth data path parsing instruction 6 is connected to the AXI data read module.

[0064] The PL end also includes an AXI protocol write interface, an AXI protocol read interface, an AXI InterConnect, an SRAM memory, a DMA read module, a Local_bus module and an image timing generation module; the image data in the AXI format is electrically connected to the AXI protocol write interface of the PL end through an AXI_WR transmission channel; the AXI InterConnect reads the image data from the AXI protocol write interface and stores the data in the SRAM memory; the AXI InterConnect is electrically connected to the Local_bus module for interactively transmitting data.

[0065] The PL end also includes an AXI protocol read interface; the UART parallel data protocol parsing module is electrically connected to the AXI data read module; the AXI data read module is electrically connected to the AXI protocol read interface through an AXI_RD transmission channel; the AXI protocol read interface is electrically connected to the AXI InterConnect; the AXI data read module is electrically connected to the LCD liquid crystal screen driver module.

[0066] The AXI data reading module is divided into two data paths, wherein the first data path is connected to the AXI protocol reading interface, and the second data path is connected to the LCD liquid crystal screen driver module; the LCD liquid crystal screen driver module is connected to the LCD display screen.

[0067] The data_wr_mux module is electrically connected to the parallel data to AXI protocol write module, and the spi_wr_mux module selects and merges the received parsing instructions and control instructions to convert the parallel data into image data in AXI format.

[0068] The data_wr_mux module is connected to the parallel data to AXI protocol write module; the parallel data to AXI protocol write module is connected to the AXI protocol write interface; the AXI protocol write interface and read interface are connected to the S0 interface of the AXI_INTERCONNECT module.

[0069] The SPI parallel-to-serial module is electrically connected to the SPI write interface set at the PL end; the SPI write interface is electrically connected to the SPI interface set in the image processor chip, and is used for reading, writing and windowing operations on the registers of the image processor chip and transmitting image data, so as to read the first address of the data in the image processor chip and the length value of the memory data as needed.

[0070] The SPI image data value reading module is electrically connected to the data_rd_mux module; the spi_rd_mux module is electrically connected to the SPI image data value reading module.

[0071] The SPI image data value reading module is divided into two data paths, wherein the first data path is connected to the data_wr_mux module, and the second data path is connected to the spi_rd_mux module.

[0072] The UART sending parallel-to-serial module is connected to the UART_TX transmission channel to transmit data to the UART host computer; the SPI read register value module is connected to the UART sending parallel-to-serial module; the spi_rd_mux module is electrically connected to the SPI read register value module; the spi_rd_mux module is electrically connected to the SPI serial-to-parallel module; the spi_rd_mux module is electrically connected to the UART parallel data protocol parsing module.

[0073] The SPI serial-to-parallel module is connected to the SPI read interface provided at the PL end; the SPI read interface is electrically connected to the SPI interface provided in the image processor chip.

[0074] The UART sending parallel-to-serial module is divided into two data paths, among which the first data path is the serial UART data sent connected to the UART host computer, and the second data path is connected to the SPI read register value module; the SPI read register value module is connected to the spi_rd_mux module; the spi_rd_mux module is connected to the SPI serial-to-parallel module; the SPI serial-to-parallel module is connected to the SPI read interface; the SPI read and write interfaces are connected to the SPI interface of the image processor chip.

[0075] The DMA read module is electrically connected to the AXI InterConnect through the AXI_RD transmission channel for directly reading image data; the DMA read module is electrically connected to the Local_bus module; the DMA read module is electrically connected to the image timing generation module.

[0076] The DMA read module is divided into three data paths, among which the first data path is connected to the S1 interface of the AXI_INTERCONNECT module, the second data path is connected to the image timing generation module, and the third data path is connected to the Local_bus module; the image timing generation module is connected to the image data interface of the image processor chip; the M0 interface of the AXI_INTERCONNECT module is connected to the SRAM memory; and the M1 interface of the AXI_INTERCONNECT module is connected to the Local_bus module.

[0077] The working method of an image processing chip test platform based on FPGA described in the utility model includes the following process:

[0078] When reading the register of the image processor chip, the address information of the register to be read is sent through the UART host computer. After the sending is completed, it is converted into parallel data through the UART receiving serial-to-parallel module, and the converted parallel data is transmitted to the UART parallel data protocol parsing module. The module transmits the address of the register to be read to the spi_wr_mux module through parsing instruction 1 and control instruction 1 and selects the data. The selected data is transmitted to the SPI parallel-to-serial module, and finally the address information of the read register is transmitted to the SPI interface of the image processor chip through the SPI interface, and then transmitted to the corresponding register inside the chip. After obtaining the data of the register at the address, it is sent back to the SPI interface of the PL end of the FPGA through the SPI interface, and then the read register value is converted into parallel data through the SPI serial-to-parallel module, and the converted parallel data is transmitted to the spi_rd_mux module, so as to obtain the corresponding instruction after the image processor chip is parsed inside, and the data at the corresponding address is transmitted to the PL end of the FPGA through the SPI interface. The spi_rd_mux module parses instruction 5 and selects the SPI register value reading module. After receiving the data, the module transmits it to the UART transmission and serial conversion module, and finally displays the value of the register on the UART host computer.

[0079] When writing the register of the image processor chip, the address and register value of the register to be written are sent through the UART host computer. After the sending is completed, the UART receiving serial-to-parallel module converts it into parallel data, and the converted parallel data is transmitted to the UART parallel data protocol parsing module. The module transmits the address and register value of the register to be written to the spi_wr_mux module through parsing instruction 2 and control instruction 1 and selects the data. The selected data is transmitted to the SPI parallel-to-serial module, and finally the register address and register value to be written are transmitted to the SPI interface of the image processor chip through the SPI interface. After receiving the address of the register to be written, the image processor chip writes the corresponding register value into the register;

[0080] When configuring the windowing mode of the image processor chip, a series of register addresses and register values ​​required for windowing are sent through the UART host computer. After the sending is completed, the information is converted into parallel data through the UART receiving serial-to-parallel module, and the converted parallel data is transmitted to the UART parallel data protocol parsing module. The module transmits the register address and register value required to be written to the spi_wr_mux module through parsing instruction 3 and control instruction 1 and selects the data. The selected data is transmitted to the SPI parallel-to-serial module, and finally the register address and register value to be written are transmitted to the SPI interface of the image processor chip through the SPI interface. After receiving the address of the written register, the image processor chip writes the corresponding register value into the register;

[0081] When configuring the Local_bus module on the PL side of the FPGA, first send the file size of the image data to be written and the relevant register configuration information of the DMA read module through the UART host computer. After the sending is completed, it is converted into parallel data through the UART receiving serial-to-parallel module, and the converted parallel data is transmitted to the UART parallel data protocol parsing module. The module transmits the configuration information to be written to the data_wr_mux module through parsing instruction 4 and control instruction 2 and selects the data. The selected data is transmitted to the parallel data to AXI protocol writing module, and finally the configuration information is written to the Local_bus module of the PL of the FPGA through the AXI_INTERCONNECT module;

[0082] When transmitting the original image to the image processor chip, the bin file of the image data to be written is sent through the UART host computer. After the sending is completed, it is converted into parallel data through the UART receiving serial-to-parallel module, and the converted parallel data is transmitted to the UART parallel data protocol parsing module. The module transmits the image data to be written to the data_wr_mux module through parsing instruction 4 and control instruction 2 and selects the data. The selected data is transmitted to the parallel data conversion AXI protocol writing module, and finally the image data is written to the SRAM memory of the PL of the FPGA through the AXI_INTERCONNECT module. After the image data is written to the SRAM memory, the DMA read module reads the configuration information in the Local_bus module through the M1 interface of the AXI_INTERCONNECT module, and then reads the data from the SRAM memory through the M0 interface of the AXI_INTERCONNECT module through the PL end of the FPGA. After reading, the image data is transmitted to the image timing generation module. The module generates the corresponding image data according to the image format of the image processor chip and transmits it to the image data interface of the image processor chip. The image processor chip stores the received image data in the SRAM inside the chip.

[0083] When the original image data or the image data after windowing is exported from the SRAM memory of the image processor chip, the address information of the SRAM memory to be read is sent through the UART host computer. After the sending is completed, it is converted into parallel data through the UART receiving serial-to-parallel module, and the converted parallel data is transmitted to the UART parallel data protocol parsing module. The module transmits the address of the register to be read to the spi_wr_mux module through parsing instruction 1 and control instruction 1 and selects the data. The selected data is transmitted to the SPI parallel-to-serial module, and finally the address information of the read register is transmitted to the SPI interface of the image processor chip through the SPI interface, and then transmitted to the corresponding register inside the chip. After obtaining the SRAM memory data at the address , and then the SRAM memory data read back is converted into parallel data through the SPI serial-to-parallel module, and the converted parallel data is transmitted to the spi_rd_mux module, which is selected to the SPI read image data value module through the parsing instruction 5. After receiving the data, the module passes it to the data_wr_mux module, which is selected by the control instruction 2 and then passed to the parallel data to AXI protocol write module. The module converts the data into the form of AXI protocol and passes it to the S0 interface of the AXI_INTERCONNECT module, and finally writes it to the SRAM memory of the PL side of the FPGA through the M0 interface of the AXI_INTERCONNECT module;

[0084] When the original image data exported from the SRAM memory of the image processor chip or the image data after windowing is displayed on the LCD screen, the size, resolution and display coordinate information of the image to be displayed on the LCD are sent to the UART host computer through the UART. After the sending is completed, it is converted into parallel data through the UART receiving serial-to-parallel module, and the converted parallel data is transmitted to the UART parallel data protocol parsing module. The module transmits the size, resolution and display coordinate information of the image to be displayed to the AXI data reading module through parsing instruction 6. The module reads the image data in the SRAM memory of the PL end of the FPGA through the M0 interface of the AXI_INTERCONNECT module based on this information, and transmits the read image data to the LCD liquid crystal screen driver module, which drives the image data to be transmitted to the LCD display screen for display.

[0085] The above embodiment is only one of the implementation methods that can realize the technical solution of the utility model. The scope of protection claimed by the utility model is not limited only by the present embodiment, but also includes any changes, replacements and other implementation methods that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the utility model. Although the embodiments of the utility model have been shown and described, it can be understood by ordinary technicians in this field that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principle and spirit of the utility model, and the scope of the utility model is defined by the attached claims and their equivalents.

Claims

1. An image processing chip testing platform based on FPGA, characterized in that: It includes a UART host computer, an FPGA, an image processor chip and an LCD display screen; the UART host computer is electrically connected to the FPGA; the FPGA includes a PS terminal and a PL terminal; The PL end includes an SPI read interface and an SPI write interface; the image processor chip includes an SPI interface; The PS end includes a read register value circuit and a write register value circuit; the read register value circuit includes a UART parallel data protocol parsing module, an SPI register write mode module, an spi_wr_mux module and an SPI parallel-to-serial module in sequence; the SPI parallel-to-serial module is electrically connected to the SPI write interface of the PL end, and the SPI write interface is electrically connected to the SPI interface of the image processor chip; the write register value circuit includes an SPI serial-to-parallel module, an spi_rd_mux module connection, an SPI read image data value module, a data_wr_mux module and a parallel data to AXI protocol write module in sequence, and the SPI serial-to-parallel module is electrically connected to the SPI read interface of the PL end; the SPI read interface is electrically connected to the SPI interface of the image processor chip; The FPGA is electrically connected to the LCD display screen.

2. The FPGA-based image processing chip testing platform according to claim 1, characterized in that: The PS end also includes a UART receiving serial-to-parallel module; the UART receiving serial-to-parallel module is electrically connected to the UART parallel data protocol analysis module; the UART parallel data protocol analysis module also includes an SPI register reading mode module and an SPI configuration windowing mode module, the SPI register reading mode module and the SPI configuration windowing mode module are respectively electrically connected to the spi_wr_mux module, and the spi_wr_mux module is electrically connected to the UART parallel data protocol analysis module.

3. The FPGA-based image processing chip testing platform according to claim 1, characterized in that: The UART parallel data protocol parsing module is electrically connected to the data_wr_mux module.

4. The FPGA-based image processing chip testing platform according to claim 3, characterized in that: The PL end also includes an AXI protocol write interface, an AXI protocol read interface, an AXI InterConnect, an SRAM memory, a DMA read module, a Local_bus module and an image timing generation module; the parallel data to AXI protocol write module is electrically connected to the AXI protocol write interface of the PL end through an AXI_WR transmission channel to transmit image data in AXI format; the AXI InterConnect is electrically connected to the AXI protocol write interface; the AXI InterConnect is electrically connected to the Local_bus module; the AXIInterConnect is electrically connected to the SRAM memory module; the DMA read module is electrically connected to the AXIInterConnect through an AXI_RD transmission channel; the DMA read module is electrically connected to the Local_bus module; the DMA read module is electrically connected to the image timing generation module.

5. The FPGA-based image processing chip testing platform according to claim 4, characterized in that: The PS end also includes an AXI data reading module and an LCD screen driving module; the AXI data reading module is electrically connected to the AXI protocol reading interface through an AXI_RD transmission channel; and the UART parallel data protocol parsing module is electrically connected to the AXI data reading module.

6. The FPGA-based image processing chip testing platform according to claim 5, characterized in that: The AXI protocol read interface is electrically connected to the AXI InterConnect; the AXI data read module is electrically connected to the LCD liquid crystal screen drive module.

7. The FPGA-based image processing chip testing platform according to claim 5, characterized in that: The LCD liquid crystal screen driving module is electrically connected to the LCD display screen.

8. The FPGA-based image processing chip testing platform according to claim 1, characterized in that: The PS end also includes a UART sending parallel-to-serial module; the spi_rd_mux module is electrically connected to the UART parallel data protocol analysis module; the spi_rd_mux module is electrically connected to the SPI read register value module; the SPI read register value module is connected to the UART sending parallel-to-serial module to return the SPI read register value to the UART host computer.

9. The FPGA-based image processing chip testing platform according to claim 8, characterized in that: The UART sending parallel-to-serial module is connected to the UART sending parallel-to-serial module through the UART_TX transmission channel to transmit data to the UART host computer.

10. The FPGA-based image processing chip testing platform according to claim 1, characterized in that: The PS end also includes a UART sending serial-to-parallel module; the UART host computer is connected to the UART sending serial-to-parallel module through a UART_RX transmission channel to receive the image data to be processed transmitted by the serial-to-parallel module to the UART host computer.

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