Image processing accelerator

Abstract

The utility model provides an image processing accelerator, which belongs to the technical field of image processing equipment and comprises an SPI (Serial Peripheral Interface) upper computer, an image sensor and a processor integrated on a chip, and the SPI upper computer and the image sensor are respectively and electrically connected with the processor integrated on the chip; the processor integrated on the chip comprises an image data caching module, an image windowing module, an APB configuration module, an SPI2APB protocol conversion module, an APB2SRAM protocol conversion module, an AXI2SRAM protocol conversion module, a first gating module, an SRAM memory module and a second gating module. The processor is better compatible with an external image sensor and more efficiently completes image processing by utilizing modes of real-time image acquisition, real-time image processing, windowing processing at any position, windowing processing at any size, histogram homogenization processing, color space conversion and format configuration.

Description

Technical Field

[0001] The utility model belongs to the technical field of image processing equipment, in particular to an image processing accelerator. Background Art

[0002] With the continuous development of image processing technology, the requirements for image processing speed and efficiency are getting higher and higher. Image processing accelerator technology plays a vital role in the fields of image processing and computer vision. It not only improves image quality and user experience, but also promotes the advancement of related technologies and the expansion of applications. In recent years, the rapid development of artificial intelligence technology has brought new opportunities for image processing accelerator technology. With the application of deep learning algorithms, image processing accelerators can achieve more accurate and efficient image processing functions. It processes the raw data output by the image sensor to remove noise, correct color, adjust contrast, etc., thereby generating high-quality images. Image processing accelerators play an increasingly important role in various application fields. In the existing technology, image processing usually requires multiple modules to work together, but the data transmission and protocol conversion between modules are often inefficient, resulting in low overall image processing efficiency. Utility Model Content

[0003] In order to solve the problem that the conversion of existing image processing accelerators is often inefficient, resulting in low overall image processing efficiency, the utility model provides an image processing accelerator.

[0004] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0005] The utility model proposes an image processing accelerator, which is characterized by comprising an SPI interface host computer, an image sensor and a processor integrated on a chip, wherein the SPI interface host computer and the image sensor are electrically connected to the processor respectively;

[0006] The processor integrated on the chip includes an image data cache module, an image windowing module, an APB configuration module, an SPI2APB protocol conversion module, an APB2SRAM protocol conversion module, an AXI2SRAM protocol conversion module, a first gating module, an SRAM memory module, and a second gating module;

[0007] Wherein, the output interface of the image sensor is electrically connected to the input interface of the image data cache module; the output interface of the image data cache module is electrically connected to the input interfaces of the image windowing module and the first gating module respectively;

[0008] The output interface of the image windowing module is electrically connected to the input interface of the first gating module and the AXI2SRAM protocol conversion module respectively; the output interface of the first gating module is electrically connected to the input interface of the AXI2SRAM protocol conversion module; the output interface of the second gating module is electrically connected to the input interface of the AXI2SRAM protocol conversion module;

[0009] The output interface of the SPI interface host computer is electrically connected to the input interface of the SPI2APB protocol conversion module; the output interface of the SPI2APB protocol conversion module is electrically connected to the input interface of the APB configuration module, the APB2SRAM protocol conversion module and the second gating module respectively, and the output interface of the APB2SRAM protocol conversion module is electrically connected to the input interface of the second gating module;

[0010] The output interface of the APB configuration module is electrically connected to the input interfaces of the image windowing module, the image data buffering module and the first gating module respectively;

[0011] The output interface of the AXI2SRAM protocol conversion module is electrically connected to the input interface of the SRAM memory module.

[0012] Preferably, the image data cache module includes an image data cache control submodule and an image data cache write submodule;

[0013] The output interface of the data cache control submodule is electrically connected to the input interface of the image windowing module and the first gating module respectively; the input interface of the data cache control submodule is electrically connected to the output interface of the image sensor and the SPI2APB protocol conversion module respectively;

[0014] The input interface of the image data cache writing submodule is electrically connected to the output interfaces of the APB configuration module and the data cache control submodule respectively.

[0015] Preferably, the data cache control submodule includes an image data asynchronous cache unit, an image data synchronous cache unit and a histogram parameter calculation unit;

[0016] The input interface of the image data asynchronous cache unit is electrically connected to the output interface of the image sensor and the SPI2APB protocol conversion module respectively, and the output interface of the image data asynchronous cache unit is electrically connected to the input interface of the image data synchronous cache unit and the histogram parameter calculation unit respectively;

[0017] The output interface of the image data asynchronous cache unit is electrically connected to the input interface of the image windowing module;

[0018] The output interface of the histogram parameter calculation unit is electrically connected to the input interface of the first gating module and the image data cache writing submodule.

[0019] Preferably, the image windowing module includes a windowing control submodule, a histogram normalization submodule, a color space conversion submodule, a grayscale image writing submodule, a color image writing submodule and a first gating submodule;

[0020] Wherein, the input interfaces of the windowing control submodule, the histogram normalization submodule, the color space conversion submodule, the grayscale image writing submodule, the color image writing submodule and the first gating submodule are all electrically connected to the output interface of the APB configuration module;

[0021] The output interface of the windowing control submodule is electrically connected to the input interface of the AXI2SRAM protocol conversion module and the histogram normalization submodule respectively;

[0022] The input interface of the histogram normalization submodule is also electrically connected to the output interface of the image data cache module, and the output interface of the histogram normalization submodule is electrically connected to the input interface of the color space conversion submodule;

[0023] The output interface of the color space conversion submodule is electrically connected to the input interfaces of the grayscale image writing submodule and the color image writing submodule respectively;

[0024] The output interfaces of the grayscale image writing submodule and the color image writing submodule are both electrically connected to the input interface of the first gating submodule; the output interface of the first gating submodule is electrically connected to the input interface of the first gating module.

[0025] Preferably, the window control submodule includes a trigger control unit, an image data parameter calculation unit, a grayscale image reading unit, a color image reading unit and a third gating unit;

[0026] The input interfaces of the trigger control unit and the third gating unit are both electrically connected to the output interface of the APB configuration module, and the output interface of the trigger control unit is electrically connected to the input interfaces of the image data parameter calculation unit, the grayscale image reading unit, and the color image reading unit, respectively;

[0027] The output interface of the image data parameter calculation unit is electrically connected to the input interfaces of the grayscale image reading unit and the color image reading unit respectively;

[0028] The output interfaces of the grayscale image reading unit and the color image reading unit are both electrically connected to the input interface of the histogram normalization submodule;

[0029] The output interface of the third gating unit is electrically connected to the input interface of the AXI2SRAM protocol conversion module.

[0030] Preferably, the grayscale image reading unit and the color image reading unit both include a multi-way selection subunit and a synchronous reading and writing subunit;

[0031] The input interfaces of the multi-way selection subunit and the synchronous read-write subunit are electrically connected to the output interfaces of the trigger control unit, the image data parameter calculation unit and the third selection unit, respectively, and the output interfaces of the multi-way selection subunit and the synchronous read-write subunit are electrically connected to the input interface of the histogram normalization submodule.

[0032] Preferably, the SPI2APB protocol conversion module includes an SPI protocol parsing unit and an SPI data channel to APB data channel unit;

[0033] The input interface of the SPI protocol analysis unit is electrically connected to the output interface of the SPI interface host computer;

[0034] The output interface of the SPI protocol parsing unit is electrically connected to the input interfaces of the SPI data channel to APB data channel unit, the APB2SRAM protocol conversion module, the image data cache module and the second gating module respectively;

[0035] The output interface of the SPI data channel to APB data channel unit is electrically connected to the input interface of the APB configuration module.

[0036] Preferably, the APB configuration module includes an image data cache configuration unit, an image window configuration unit, a first gating configuration unit and a protocol parsing unit;

[0037] The input interface of the protocol analysis unit is electrically connected to the output interface of the SPI2APB protocol conversion module, and the output interface of the protocol analysis unit is electrically connected to the input interfaces of the image data cache configuration unit, the image windowing configuration unit and the first gating configuration unit respectively;

[0038] The output interface of the image data cache configuration unit is electrically connected to the input interface of the image data cache module; the output interface of the image windowing configuration unit is electrically connected to the input interface of the image windowing module; the output interface of the first selection configuration unit is electrically connected to the input interface of the first selection module.

[0039] Preferably, the APB2SRAM protocol conversion module includes an APB protocol parsing unit and an APB data channel to SRAM data channel unit;

[0040] The input interface of the APB protocol analysis unit is connected to the output path of the SPI2APB protocol conversion module; the output interface of the APB protocol analysis unit is electrically connected to the input interface of the APB data channel to SRAM data channel unit;

[0041] The output interface of the APB data channel to SRAM data channel unit is electrically connected to the input interface of the second gating module.

[0042] Preferably, the AXI2SRAM protocol conversion module includes an AXI write channel data parsing unit, an AXI read channel data parsing unit and an AXI read-write data channel to SRAM data channel unit; wherein the input interface of the AXI write channel data parsing unit is connected to the output path of the first gating module, and the input interface of the AXI read channel data parsing unit is connected to the output path of the image windowing module;

[0043] The input interface of the AXI read-write data channel to SRAM data channel unit is electrically connected to the output interfaces of the AXI write channel data parsing unit and the AXI read channel data parsing unit respectively, and the output interface of the AXI read-write data channel to SRAM data channel unit is connected to the input path of the SRAM memory module.

[0044] Compared with the prior art, the utility model has the following beneficial technical effects:

[0045] The utility model proposes an image processing accelerator. The accelerator integrates an SPI interface host computer, an image sensor and a processor into one, realizes a compact layout of hardware resources, reduces system complexity, improves the reliability and stability of the overall equipment, and simplifies external connections, making the installation and debugging of the equipment more convenient. The internal modules of the processor have clear division of labor and work in coordination. The image data cache module effectively alleviates the pressure of data processing and ensures the smooth transmission of image data; the image windowing module provides a flexible image area selection function to meet the diverse image processing needs, the APB configuration module, the SPI2APB protocol conversion module, and the APB2SRAM The protocol conversion module and AXI2SRAM protocol conversion module ensure smooth and efficient data communication between different modules. The introduction of the first selection module and the second selection module further enhances the flexibility of the data processing path, enabling the system to flexibly switch the data processing flow according to actual needs, thereby improving resource utilization and processing efficiency. The SRAM memory module, as the core storage unit for data processing, has large capacity and high-speed access characteristics, providing sufficient data storage space for image processing, ensuring the accuracy and real-time nature of the processing results. This image processing accelerator achieves a dual improvement in image processing efficiency and flexibility through highly integrated, modular design and flexible data processing paths.

[0046] Furthermore, the image data cache module in this accelerator can accurately schedule data flow to the image windowing module or the first selection module according to system instructions, effectively improving the flexibility and efficiency of data processing. The data cache control submodule receives data input from the image sensor and the SPI2APB protocol conversion module, ensuring timely reception and caching of data. The image data cache write submodule focuses on data writing operations, receives data from the APB configuration module and the data cache control submodule, and efficiently writes it into the cache, providing reliable data support for subsequent image processing, enhancing the functionality and flexibility of the image data cache module, and improving the efficiency and accuracy of the overall image processing. At the same time, data is transmitted via the AXI bus, which improves data processing efficiency and reduces system latency.

[0047] Furthermore, the data cache control submodule in the accelerator can realize fast data writing, clock domain conversion and image histogram parameter calculation, thereby improving the system data throughput, parallelizing the calculation of brightness distribution in the image and ensuring data consistency.

[0048] Furthermore, the image windowing module in this accelerator controls the window size, window position, histogram normalization calculation and image display mode after windowing in an externally configurable manner, thereby improving the flexibility of image data windowing, the flexibility of image display mode and the improvement of image quality.

[0049] Furthermore, the AXI2SRAM protocol conversion module in the accelerator improves the accuracy and efficiency of data storage by converting the AXI protocol to the SRAM memory interface protocol.

[0050] Furthermore, the APB2SRAM protocol conversion module in the accelerator improves the accuracy and efficiency of data storage by converting the APB protocol to the SRAM memory interface protocol.

[0051] Furthermore, the APB configuration module in the accelerator quickly configures the register configuration of each module in the image accelerator through the APB protocol, thereby improving the mode configuration consistency of the entire chip module, simplifying the complexity of the design and the timeliness of the register configuration.

[0052] Furthermore, the SPI2APB protocol conversion module in the accelerator improves the data consistency and timeliness of configuration registers through the external low-speed interface by converting the SPI protocol to the APB protocol.

[0053] Furthermore, the image windowing control submodule in the accelerator effectively improves the flexibility of windowing and the efficiency of data reading and writing through configurable windowing size and windowing control mode and read and write operations of windowing data. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 This is one of the system connection diagrams of an image processing accelerator proposed by the utility model;

[0055] Figure 2 This is the second system connection diagram of an image processing accelerator proposed by the utility model. DETAILED DESCRIPTION

[0056] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0057] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0058] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0059] In the present invention, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] The embodiments of the present utility model are described in detail below with reference to the accompanying drawings.

[0061] The utility model proposes an image processing accelerator. The accelerator utilizes image processing technology to realize the collection of image data to be processed, color space conversion of image data, format conversion of image data, histogram equalization processing of image data and window processing of image, which greatly improves the efficiency of image feature extraction, image target positioning and recognition.

[0062] like Figure 1 and Figure 2 As shown, the image data cache module (Data_cache) is used to safely transmit image data between different clock domains. Since there may be multiple clock domains in the image processing system, the asynchronous FIFO can ensure that data will not be lost or erroneous when transmitted between different clock domains;

[0063] Image data cache control submodule (Data_cache_ctrl): used to cache image data in the same clock domain to achieve smooth data flow and buffering, handle data flow emergencies, and ensure the stability and reliability of the image processing system.

[0064] Image data cache write submodule (Data_cache_wr): Use simple dual-port RAM to store and calculate the histogram parameters of image data. A histogram is a chart that statistics the distribution of pixel intensity in an image. It is very important for image processing and computer vision applications. By calculating the histogram, statistical information such as image contrast and brightness can be obtained. Among them, a simple dual-port RAM is a memory with two independent data ports.

[0065] Image data asynchronous buffer unit (Async_Fifo): used to extract the region of interest from the original image, reducing processing time and resource consumption because only a part of the image is processed instead of the entire image.

[0066] Image data synchronization cache unit (Sync_Fifo): responsible for controlling the operation of the image windowing module, including setting parameters such as the windowing position, size and shape, to ensure that the windowing operation can be carried out according to the predetermined requirements.

[0067] Histogram parameter calculation unit (Histogram): The process of scaling the pixel intensity values ​​of the histogram to a specific range (such as 0 to 1). Comparing the histograms of different images, because the normalized histograms have the same scale.

[0068] Image Windowing Module (Windowed): It is used to extract the region of interest (ROI) from the original image, which helps to reduce processing time and resource consumption because only a part of the image is processed instead of the entire image.

[0069] Windowed control submodule (Windowed_ctrl): controls the operation of the image windowing module, including setting parameters such as the windowing position, size, and shape, to ensure that the windowing operation can be performed according to the predetermined requirements.

[0070] Histogram normalization submodule: The process of scaling the pixel intensity values ​​of the histogram to a specific range (such as 0 to 1). Comparing the histograms of different images, because the normalized histograms have the same scale.

[0071] Color space conversion submodule (color_space_conv): Converts image data from one color space to another, such as from RGB color space to YUV color space or HSV color space. Color space conversion is very important for color correction, enhancement and segmentation in image processing. RGB color space is a color space based on mixing the three basic colors of red, green and blue. YUV color space is a color space used for digital television. HSV color space is a color space model based on hue, saturation and brightness.

[0072] Trigger control unit (trig_ctrl): used to control the trigger mechanism of the image processing system, ensure that the image processing operation starts at the correct time and conditions, synchronize the capture and processing of image data, and improve the accuracy and reliability of the system.

[0073] Image data parameter calculation unit (param_ctrl): Calculates various parameters of image data, such as mean, variance, contrast, brightness, etc. These parameters are very important for operations such as feature extraction, classification, and recognition in image processing and computer vision applications.

[0074] Grayscale image reading unit (gray_rd): reads grayscale image data from the storage medium. Grayscale images are images that only contain brightness information and are usually used in applications such as edge detection and texture analysis in image processing.

[0075] Color image reading unit (rgb_rd): used to read color image data from the storage medium. Color images contain color information and are usually used for operations such as color correction, segmentation and recognition in image processing.

[0076] Grayscale Image Writing Submodule (Windowed_gray_wr): Writes the processed grayscale image data to cache or external storage. This usually happens after the image processing operation is completed and the result needs to be saved for subsequent use or analysis;

[0077] Color image writing submodule (Windowed_rgb_wr): Writes the processed color image data to cache or external storage. This ensures that the processed color image can be saved and used for subsequent applications.

[0078] SPI2APB protocol conversion module (SPI2APB): connects devices using the SPI interface to the APB bus to achieve communication with other devices in the system.

[0079] APB configuration module (APB_config): used to configure device parameters on the APB bus, such as device address, clock frequency, etc., to ensure that the devices on the APB bus can communicate and operate according to predetermined requirements.

[0080] APB2SRAM protocol conversion module (APB2SRAM): Converts the APB protocol to the SRAM (Static Random-Access Memory) interface protocol, which helps write data on the APB bus to the SRAM memory, or read data from the SRAM to the APB bus.

[0081] AXI2SRAM protocol conversion module (AXI2SRAM): Converts the AXI (Advanced eXtensible Interface) protocol to the SRAM interface protocol. This helps connect devices using the AXI interface to the SRAM memory, thereby achieving fast data read and write operations.

[0082] The utility model proposes an image processing accelerator, comprising an SPI interface host computer, an image sensor and a processor integrated on a chip, wherein the SPI interface host computer and the image sensor are electrically connected to the processor respectively;

[0083] The processor integrated on the chip includes an image data cache module, an image windowing module, an APB configuration module, an SPI2APB protocol conversion module, an APB2SRAM protocol conversion module, an AXI2SRAM protocol conversion module, a first strobe module (axi_wr_mux), an SRAM memory module, and a second strobe module (sram_rd_mux);

[0084] The output interface of the image sensor is electrically connected to the input interface of the image data cache module; the output interface of the image data cache module is electrically connected to the input interfaces of the image windowing module and the first gating module respectively;

[0085] The output interface of the image windowing module is electrically connected to the input interface of the first gating module, and the output interface of the image windowing module is electrically connected to the input interface of the AXI2SRAM protocol conversion module through the AXI_RD bus; the output interface of the first gating module is electrically connected to the input interface of the AXI2SRAM protocol conversion module through the AXI_WR bus; the output interface of the second gating module is electrically connected to the input interface of the AXI2SRAM protocol conversion module through the SRAM_RD bus;

[0086] The output interface of the SPI interface host computer is electrically connected to the input interface of the SPI2APB protocol conversion module; the output interface of the SPI2APB protocol conversion module is electrically connected to the APB configuration module, the APB2SRAM protocol conversion module and the input interface of the second gating module respectively; and the output interface of the SPI2APB protocol conversion module is electrically connected to the input interface of the APB2SRAM protocol conversion module through the APB_RD bus, and the output interface of the APB2SRAM protocol conversion module is electrically connected to the input interface of the second gating module through the SRAM_RD bus;

[0087] The output interface of the APB configuration module is electrically connected to the input interfaces of the image windowing module, the image data buffer module and the first gating module respectively;

[0088] The output interface of the AXI2SRAM protocol conversion module is electrically connected to the input interface of the SRAM memory module through the SRAM_WR bus.

[0089] The image data cache module is divided into two data paths, wherein the first data path is the data input interface electrically connected to the output interface of the external image sensor; the second data path is the image data cache module electrically connected to the axi_wr_mux, the axi_wr_mux is connected to the write interface of the AXI2SRAM protocol conversion module, and the write interface of the AXI2SRAM protocol conversion module is connected to the write interface of the SRAM memory module, forming a complete image data cache route to improve the image processing capability;

[0090] The read data path of the image windowing module is divided into two data paths, among which the first data path is the data histogram normalization parameter channel electrically connected to the image data cache module; the second data path is the data read channel electrically connected to the read interface of the AXI2SRAM protocol conversion module, the read interface of the AXI2SRAM protocol conversion module is electrically connected to sram_rd_mux, and sram_rd_mux is electrically connected to the read interface of the SRAM memory module, forming a complete read data processing route of the image windowing module; the write data interface of the image windowing module is electrically connected to axi_wr_mux, axi_wr_mux is electrically connected to the write interface of the AXI2SRAM protocol conversion module, and the write interface of the AXI2SRAM protocol conversion module is electrically connected to the write interface of the SRAM memory module. The SPI2APB protocol conversion module is electrically connected to the external SPI interface host computer, forming a complete image windowing module write data processing route; the SPI2APB protocol conversion module is divided into three data paths, among which the first data path is the SPI2APB protocol conversion module electrically connected to the APB configuration module, and the APB configuration module is electrically connected to the sram_rd_mux module, the image data cache module and the image windowing module respectively; the third data path is the SPI2APB protocol conversion module electrically connected to the APB2SRAM protocol conversion module, the APB2SRAM protocol conversion module is electrically connected to the sram_rd_mux, and the sram_rd_mux is electrically connected to the SRAM memory module, forming a complete read data processing route.

[0091] The image data cache module performs statistical calculations on the image histogram. The image histogram is used to represent the brightness distribution in the image, that is, it records the 8-bit data of each channel, from 0 to 255. It uses 1*256 RAM, the data is 1 bit, and the address is 8 bits, corresponding to the 8-bit data of each channel of the original image. That is, when the 8-bit data of the original image is received, 1 is written in the address of the RAM where the 8-bit data is, and the existence of the histogram of this 8-bit data is recorded. The purpose of recording the histogram is to calculate the parameters required for histogram normalization. The minimum value of the data bit width conversion of the histogram normalization parameter is the histogram traversed from low to high, that is, the data traversed from address 0 to 255 in the RAM is 1. Similarly, the maximum value of the data bit width conversion is the histogram traversed from high to low, that is, the data traversed from 255 to 0 in the RAM is 1. The calculated histogram normalization parameters are used for histogram normalization in subsequent modules.

[0092] The image data cache module includes an image data cache control submodule and an image data cache write submodule;

[0093] The output interface of the data cache control submodule is electrically connected to the input interface of the image windowing module, and the output interface of the data cache control submodule is electrically connected to the input interface of the first gating module through the AXI_WR bus; the input interface of the data cache control submodule is electrically connected to the output interface of the image sensor and the SPI2APB protocol conversion module respectively;

[0094] The input interface of the image data cache writing submodule is electrically connected to the output interfaces of the APB configuration module and the data cache control submodule respectively.

[0095] The data cache control submodule includes an image data asynchronous cache unit, an image data synchronous cache unit and a histogram parameter calculation unit;

[0096] The input interface of the image data asynchronous cache unit is electrically connected to the output interface of the image sensor and the SPI2APB protocol conversion module respectively, and the output interface of the image data asynchronous cache unit is electrically connected to the input interface of the image data synchronous cache unit and the histogram parameter calculation unit respectively;

[0097] The output interface of the image data asynchronous cache unit is electrically connected to the input interface of the image windowing module;

[0098] The output interface of the histogram parameter calculation unit is electrically connected to the input interface of the image data cache writing submodule, and the output interface of the histogram parameter calculation unit is electrically connected to the input interface of the first gating module through an AXI_WR bus.

[0099] The windowing module completes the windowed trigger control. The windowed trigger is divided into external trigger, which detects the rising edge of the external pin signal; internal trigger, which is triggered by configuring the internal register as a high trigger; timer trigger, which configures the timing parameters and triggers periodically. The trigger mode is configured by the internal register mode. The windowing module completes the parameter calculation of image data extraction. The parameter calculation of image data extraction means that when the windowed data is extracted, the windowed image size has exceeded the data of the original image and needs to be filled with blanks. Usually, it is processed by zero padding. At this time, it is necessary to calculate the horizontal zero-padding pixels and the vertical zero-padding pixels, as well as the horizontal zero-padding and vertical zero-padding flags. The windowing module completes the image data extraction. Image data extraction is divided into Gray and RGB. When the original image data is stored, the Gray image is stored in 8-bit mode and the RGB image is stored in 24-bit mode. When extracting image data, it must also be performed in the same way as the original image data.

[0100] The image windowing SDFEEED module includes a windowing control submodule, a histogram normalization submodule, a color space conversion submodule, a grayscale image writing submodule, a color image writing submodule and a first gating submodule;

[0101] Among them, the input interfaces of the window control submodule, the histogram normalization submodule, the color space conversion submodule, the grayscale image writing submodule, the color image writing submodule and the first gating submodule are all electrically connected to the output interface of the APB configuration module;

[0102] The output interface of the window control submodule is electrically connected to the input interface of the AXI2SRAM protocol conversion module and the histogram normalization submodule respectively;

[0103] The input interface of the histogram normalization submodule is also electrically connected to the output interface of the image data buffer module, and the output interface of the histogram normalization submodule is electrically connected to the input interface of the color space conversion submodule;

[0104] The output interface of the color space conversion submodule is electrically connected to the input interfaces of the grayscale image writing submodule and the color image writing submodule respectively;

[0105] The output interfaces of the grayscale image writing submodule and the color image writing submodule are both electrically connected to the input interface of the first gating submodule; the output interface of the first gating submodule is electrically connected to the input interface of the first gating module.

[0106] The window control submodule includes a trigger control unit, an image data parameter calculation unit, a grayscale image reading unit, a color image reading unit and a third gating unit;

[0107] The input interfaces of the trigger control unit and the third gating unit are electrically connected to the output interface of the APB configuration module, and the output interface of the trigger control unit is electrically connected to the input interfaces of the image data parameter calculation unit, the grayscale image reading unit and the color image reading unit respectively;

[0108] The output interface of the image data parameter calculation unit is electrically connected to the input interfaces of the grayscale image reading unit and the color image reading unit respectively;

[0109] The output interfaces of the grayscale image reading unit and the color image reading unit are both electrically connected to the input interface of the histogram normalization submodule;

[0110] The output interface of the third gating unit is electrically connected to the input interface of the AXI2SRAM protocol conversion module through an AXI_RD bus.

[0111] Preferably, the grayscale image reading unit and the color image reading unit both include a multi-way selection subunit and a synchronous reading and writing subunit;

[0112] The input interfaces of the multi-way selection subunit and the synchronous read-write subunit are electrically connected to the output interfaces of the trigger control unit, the image data parameter calculation unit and the third selection unit respectively, and the output interfaces of the multi-way selection subunit and the synchronous read-write subunit are electrically connected to the input interface of the histogram normalization submodule.

[0113] The SPI2APB protocol conversion module completes the SPI to APB bridge, converting the serial bus into an APB bus bridge. As the SPI slave interface, it uses a serial-to-parallel shifter to parse and extract the command byte, address byte, and data byte of the SPI bus according to the standard communication protocol of the SPI bus, and then converts them into the APB communication protocol as the output of the APB master interface.

[0114] The SPI2APB protocol conversion module includes an SPI protocol parsing unit and an SPI data channel to APB data channel unit;

[0115] The input interface of the SPI protocol analysis unit is electrically connected to the output interface of the SPI interface host computer;

[0116] The output interface of the SPI protocol analysis unit is electrically connected to the SPI data channel to APB data channel unit, the APB2SRAM protocol conversion module, the image data cache module and the input interface of the second selection module respectively;

[0117] The output interface of the SPI data channel to APB data channel unit is electrically connected to the input interface of the APB configuration module.

[0118] Preferably, the APB configuration module includes an image data cache configuration unit, an image window configuration unit, a first gating configuration unit and a protocol parsing unit;

[0119] The input interface of the protocol analysis unit is electrically connected to the output interface of the SPI2APB protocol conversion module, and the output interface of the protocol analysis unit is electrically connected to the input interfaces of the image data cache configuration unit, the image windowing configuration unit and the first gating configuration unit respectively;

[0120] The output interface of the image data cache configuration unit is electrically connected to the input interface of the image data cache module; the output interface of the image windowing configuration unit is electrically connected to the input interface of the image windowing module; the output interface of the first selection configuration unit is electrically connected to the input interface of the first selection module.

[0121] The APB2SRAM protocol conversion module includes an APB protocol parsing unit and an APB data channel to SRAM data channel unit;

[0122] The input interface of the APB protocol analysis unit is connected to the output path of the SPI2APB protocol conversion module; the output interface of the APB protocol analysis unit is electrically connected to the input interface of the APB data channel to SRAM data channel unit;

[0123] The output interface of the APB data channel to SRAM data channel unit is electrically connected to the input interface of the second selection module.

[0124] The AXI2SRAM protocol conversion module is a bridge that converts the AXI4 bus read and write protocol into the SRAM read and write controller, which means that the SRAM can be read and written through the AXI bus. The APB2SRAM protocol conversion module is a bridge that converts the APB bus read protocol into the SRAM read controller, which also reads the SRAM through the APB bus. The AXI2SRAM protocol conversion module includes an AXI write channel data parsing unit, an AXI read channel data parsing unit, and an AXI read-write data channel to SRAM data channel unit; wherein, the input interface of the AXI write channel data parsing unit is connected to the output path of the first selection module, and the input interface of the AXI read channel data parsing unit is connected to the output path of the image windowing module;

[0125] The input interface of the AXI read / write data channel to SRAM data channel unit is electrically connected to the output interfaces of the AXI write channel data parsing unit and the AXI read channel data parsing unit respectively, and the output interface of the AXI read / write data channel to SRAM data channel unit is connected to the input path of the SRAM memory module.

[0126] The image data cache module is divided into two data paths, wherein the first data path is the input interface of the image data cache module electrically connected to the external image sensor; the second data path is the image data cache module electrically connected to the axi_wr_mux module, the axi_wr_mux module is electrically connected to the write interface of the AXI2SRAM protocol conversion module, and the write interface of the AXI2SRAM protocol conversion module is electrically connected to the write interface of the SRAM memory module, thus forming a complete write processing route for the image data cache;

[0127] The read data path of the image windowing module is divided into two data paths, among which the first data path is the electrical connection between the histogram normalization parameter interface in the image windowing module and the image data cache module; the second data path is the electrical connection between the read interface of the data in the image windowing module and the read interface of the AXI2SRAM protocol conversion module, the read interface of the AXI2SRAM protocol conversion module is electrically connected to the sram_rd_mux module, and the sram_rd_mux module is connected to the read interface of the SRAM memory module, forming a complete read data processing route for the image windowing module; the write data interface of the image windowing module is electrically connected to the axi_wr_mux module, the axi_wr_mux module is electrically connected to the write interface of the AXI2SRAM protocol conversion module, and the write interface of the AXI2SRAM protocol conversion module is electrically connected to the write interface of the SRAM memory module. The SPI2APB protocol conversion module is electrically connected to the SPI2APB port, forming a complete image windowing module write data processing route; the SPI2APB protocol conversion module is divided into three data paths, among which the first data path is the SPI2APB protocol conversion module electrically connected to the external SPI interface host computer; the second data path is the SPI2APB protocol conversion module electrically connected to the APB configuration module, and the APB configuration module is electrically connected to the sram_rd_mux module, the image data cache module and the image windowing module respectively, for module configuration; the third data path is the SPI2APB protocol conversion module electrically connected to the APB2SRAM protocol conversion module, the APB2SRAM protocol conversion module is electrically connected to the sram_rd_mux module, and the sram_rd_mux module is electrically connected to the SRAM memory module, forming a complete read data processing route.

[0128] The working process of an image processing accelerator proposed by the utility model includes the following:

[0129] When configuring registers, the corresponding register configuration information is sent by the host computer through the SPI interface. After the information is sent, it is converted into the APB protocol by the SPI2APB protocol conversion module, and then the corresponding information is given to the APB configuration module. The configuration module sends the configuration to each corresponding module according to the corresponding register information to complete the register configuration of the corresponding module.

[0130] When storing the original image data, the SPI interface host computer first sends the size of the original image, the input image type of the original image, and the starting address of the original image stored in the memory. After the SPI interface host computer transmits the corresponding instruction information to the SPI2APB module, the SPI2APB module performs data protocol conversion and transmits the converted configuration information to APB_config. APB_config transmits the corresponding configuration information to Data_cache_ctrl, Data_cache_wr, and axi_wr_mux respectively. After Data_cache_ctrl, Data_cache_wr, and axi_wr_mux receive the configuration information, they are transmitted through the external image transmission The sensor transmits the image data to the image data cache control submodule, which receives the image data into Async_fifo for clock domain conversion, and transmits the converted data to Sync_Fifo for caching, and also transmits it to Histogram to extract the parameters for image histogram statistics calculation. Sync_Fifo transmits the cached data to Data_cache_wr, which converts the image data into AXI protocol interface data, and then passes it to the AXI2SRAM protocol conversion module after being selected by axi_wr_mux, converting the data into the SRAM interface protocol. After the conversion is completed, it is written into the SRAM memory to complete the storage of the original image data.

[0131] When the original image is windowed, the size of the windowed image, the starting coordinates of the windowed image, the trigger mode of the windowing, the output image type after the windowing, and the starting address of the image stored in the memory after the windowing are first sent through the SPI interface host computer. After the SPI interface host computer sends the corresponding instruction information to the SPI2APB module, the SPI2APB module performs data protocol conversion and transmits the converted configuration information to APB_config and sram_rd_mux. APB_config transmits the corresponding configuration information to Windowed_ctrl, trig_ctrl, axi_rd_mux, color_space_conv, normalization, Windowed_gray_wr, Windowed_rgb_wr and axi_wr_mux respectively. After Windowed_ctrl, trig_ctrl, axi_rd_mux, color_space_conv, normalization, Windowed_gray_wr, Windowed_rgb_wr and axi_wr_mux receive the configuration information,trig_ctrl first triggers the corresponding read channel. After the axi_rd_mux module is enabled, the read address information is transmitted to the read channel of AXI2SRAM. The read channel of AXI2SRAM converts the information into SRAM interface read information, and then transmits it to sram_rd_mux. After sram_rd_mux is enabled, the data is transmitted to the SRAM memory module. The SRAM memory module returns the data on the corresponding address to sram_rd_mux, and then returns it to the axi_rd_mux module, and finally returns it to gray_rd or rgb_rd. After receiving the returned data, gray_rd or rgb_rd gets the parameters through param_ctrl for further processing. After the processing is completed, the data is cached in Sync_Fifo, and then read out and transmitted to normalization, nor When malization gets the image data, it reads the histogram normalization parameters from Histogram to perform image normalization processing. After the processing is completed, it is converted into the image mode required for output through color_space_conv. The data is transmitted to Windowed_gray_wr or Windowed_rgb_wr through the image mode selection. Windowed_gray_wr or Windowed_rgb_wr recombines the data into the data format of axi full bandwidth, and then transmits it to axi_wr_mux. After axi_wr_mux is selected, it is transmitted to the write channel of the AXI2SRAM module and converted into the write protocol of the SRAM interface. The data is written into the SRAM memory module. The above process is cycled to complete the data processing of the entire window size, and the processed data is stored in the corresponding address of the SRAM memory module. ,

[0132] When the original image data or the windowed image data is exported from the SRAM memory module, the corresponding address information of the read data is sent through the SPI interface host computer. After the sending is completed, it is converted into the APB protocol through the SPI2APB protocol conversion module, and then the corresponding information is given to the APB2SRAM protocol conversion module. After sram_rd_mux obtains the selected configuration signal, the read information is given to the SRAM memory module. The SRAM memory module returns the image data at the corresponding position to the SPI interface host computer for display or storage. The above process is cycled to complete the reading of the entire original image or windowed image data size, and all the read data are stored through the host computer;

[0133] The above shows and describes the basic principles and main features of the utility model and the advantages of the utility model. For those skilled in the art, it is obvious that the utility model is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic features of the utility model. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the utility model is defined by the attached claims rather than the above description, and it is intended to include all changes within the meaning and scope of the equivalent elements of the claims. Any figure mark in the claims should not be regarded as limiting the claims involved.

[0134] In addition, it should be understood that although this specification is described in accordance with the implementation methods, not every implementation method contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should take the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art. The above content is only to illustrate the technical idea of ​​the utility model, and cannot be used to limit the protection scope of the utility model. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the utility model shall fall within the protection scope of the claims of the utility model.

Claims

1. An image processing accelerator, characterized in that: It includes an SPI interface host computer, an image sensor and a processor integrated on a chip, wherein the SPI interface host computer and the image sensor are electrically connected to the processor respectively; The processor integrated on the chip includes an image data cache module, an image windowing module, an APB configuration module, an SPI2APB protocol conversion module, an APB2SRAM protocol conversion module, an AXI2SRAM protocol conversion module, a first gating module, an SRAM memory module, and a second gating module; Wherein, the output interface of the image sensor is electrically connected to the input interface of the image data cache module; the output interface of the image data cache module is electrically connected to the input interfaces of the image windowing module and the first gating module respectively; The output interface of the image windowing module is electrically connected to the input interface of the first gating module and the AXI2SRAM protocol conversion module respectively; the output interface of the first gating module is electrically connected to the input interface of the AXI2SRAM protocol conversion module; the output interface of the second gating module is electrically connected to the input interface of the AXI2SRAM protocol conversion module; The output interface of the SPI interface host computer is electrically connected to the input interface of the SPI2APB protocol conversion module; the output interface of the SPI2APB protocol conversion module is electrically connected to the input interface of the APB configuration module, the APB2SRAM protocol conversion module and the second gating module respectively, and the output interface of the APB2SRAM protocol conversion module is electrically connected to the input interface of the second gating module; The output interface of the APB configuration module is electrically connected to the input interfaces of the image windowing module, the image data buffering module and the first gating module respectively; The output interface of the AXI2SRAM protocol conversion module is electrically connected to the input interface of the SRAM memory module.

2. An image processing accelerator according to claim 1, characterized in that: The image data cache module includes an image data cache control submodule and an image data cache write submodule; The output interface of the data cache control submodule is electrically connected to the input interface of the image windowing module and the first gating module respectively; the input interface of the data cache control submodule is electrically connected to the output interface of the image sensor and the SPI2APB protocol conversion module respectively; The input interface of the image data cache writing submodule is electrically connected to the output interfaces of the APB configuration module and the data cache control submodule respectively.

3. An image processing accelerator according to claim 2, characterized in that: The data cache control submodule includes an image data asynchronous cache unit, an image data synchronous cache unit and a histogram parameter calculation unit; The input interface of the image data asynchronous cache unit is electrically connected to the output interface of the image sensor and the SPI2APB protocol conversion module respectively, and the output interface of the image data asynchronous cache unit is electrically connected to the input interface of the image data synchronous cache unit and the histogram parameter calculation unit respectively; The output interface of the image data asynchronous cache unit is electrically connected to the input interface of the image windowing module; The output interface of the histogram parameter calculation unit is electrically connected to the input interface of the first gating module and the image data cache writing submodule.

4. The image processing accelerator according to claim 1, characterized in that: The image windowing module includes a windowing control submodule, a histogram normalization submodule, a color space conversion submodule, a grayscale image writing submodule, a color image writing submodule and a first gating submodule; Wherein, the input interfaces of the windowing control submodule, the histogram normalization submodule, the color space conversion submodule, the grayscale image writing submodule, the color image writing submodule and the first gating submodule are all electrically connected to the output interface of the APB configuration module; The output interface of the windowing control submodule is electrically connected to the input interface of the AXI2SRAM protocol conversion module and the histogram normalization submodule respectively; The input interface of the histogram normalization submodule is also electrically connected to the output interface of the image data cache module, and the output interface of the histogram normalization submodule is electrically connected to the input interface of the color space conversion submodule; The output interface of the color space conversion submodule is electrically connected to the input interfaces of the grayscale image writing submodule and the color image writing submodule respectively; The output interfaces of the grayscale image writing submodule and the color image writing submodule are both electrically connected to the input interface of the first gating submodule; the output interface of the first gating submodule is electrically connected to the input interface of the first gating module.

5. An image processing accelerator according to claim 4, characterized in that: The window control submodule includes a trigger control unit, an image data parameter calculation unit, a grayscale image reading unit, a color image reading unit and a third gating unit; The input interfaces of the trigger control unit and the third gating unit are both electrically connected to the output interface of the APB configuration module, and the output interface of the trigger control unit is electrically connected to the input interfaces of the image data parameter calculation unit, the grayscale image reading unit, and the color image reading unit, respectively; The output interface of the image data parameter calculation unit is electrically connected to the input interfaces of the grayscale image reading unit and the color image reading unit respectively; The output interfaces of the grayscale image reading unit and the color image reading unit are both electrically connected to the input interface of the histogram normalization submodule; The output interface of the third gating unit is electrically connected to the input interface of the AXI2SRAM protocol conversion module.

6. An image processing accelerator according to claim 5, characterized in that: The grayscale image reading unit and the color image reading unit both include a multi-way selection subunit and a synchronous reading and writing subunit; The input interfaces of the multi-way selection subunit and the synchronous read-write subunit are electrically connected to the output interfaces of the trigger control unit, the image data parameter calculation unit and the third selection unit, respectively, and the output interfaces of the multi-way selection subunit and the synchronous read-write subunit are electrically connected to the input interface of the histogram normalization submodule.

7. The image processing accelerator according to claim 1, characterized in that: The SPI2APB protocol conversion module includes an SPI protocol parsing unit and an SPI data channel to APB data channel unit; The input interface of the SPI protocol analysis unit is electrically connected to the output interface of the SPI interface host computer; The output interface of the SPI protocol parsing unit is electrically connected to the input interfaces of the SPI data channel to APB data channel unit, the APB2SRAM protocol conversion module, the image data cache module and the second gating module respectively; The output interface of the SPI data channel to APB data channel unit is electrically connected to the input interface of the APB configuration module.

8. The image processing accelerator according to claim 1, characterized in that: The APB configuration module includes an image data cache configuration unit, an image window configuration unit, a first gating configuration unit and a protocol parsing unit; The input interface of the protocol analysis unit is electrically connected to the output interface of the SPI2APB protocol conversion module, and the output interface of the protocol analysis unit is electrically connected to the input interfaces of the image data cache configuration unit, the image windowing configuration unit and the first gating configuration unit respectively; The output interface of the image data cache configuration unit is electrically connected to the input interface of the image data cache module; the output interface of the image windowing configuration unit is electrically connected to the input interface of the image windowing module; the output interface of the first selection configuration unit is electrically connected to the input interface of the first selection module.

9. The image processing accelerator according to claim 1, characterized in that: The APB2SRAM protocol conversion module includes an APB protocol parsing unit and an APB data channel to SRAM data channel unit; The input interface of the APB protocol analysis unit is connected to the output path of the SPI2APB protocol conversion module; The output interface of the APB protocol parsing unit is electrically connected to the input interface of the APB data channel to SRAM data channel unit; The output interface of the APB data channel to SRAM data channel unit is electrically connected to the input interface of the second gating module.

10. The image processing accelerator according to claim 1, characterized in that: The AXI2SRAM protocol conversion module includes an AXI write channel data parsing unit, an AXI read channel data parsing unit and an AXI read-write data channel to SRAM data channel unit; wherein the input interface of the AXI write channel data parsing unit is connected to the output path of the first gating module, and the input interface of the AXI read channel data parsing unit is connected to the output path of the image windowing module; The input interface of the AXI read-write data channel to SRAM data channel unit is electrically connected to the output interfaces of the AXI write channel data parsing unit and the AXI read channel data parsing unit respectively, and the output interface of the AXI read-write data channel to SRAM data channel unit is connected to the input path of the SRAM memory module.

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