Universal control system board card

Abstract

The utility model relates to the technical field of universal control systems, and particularly discloses a universal control system board card, which comprises an ARM (advanced RISC machines) processor and FPGA (field programmable gate array) chips in communication connection with the ARM processor. The FPGA chip comprises a PL end and a PS end, the PL end is connected with the corresponding logic control interface, and the PS end is connected with the corresponding processing interface; the logic control interface comprises a bus expansion interface, an I / O interface and a 1553B interface which are connected with the FPGA chip; the processing interface comprises a plurality of storage modules and a plurality of communication interfaces which are connected with the FPGA chip; and the ARM processor is connected with the USB interface. A bus expansion interface, an I / O interface, a 1553B interface and a plurality of communication interfaces are integrated on an FPGA chip in the universal control system board card, and the universal control system board card is further provided with a plurality of storage modules to increase the memory capacity of a memory, so that the universal control system board card can be applied to calculation, control, acquisition and storage in various scenes.

Description

Technical Field

[0001] The utility model relates to the technical field of universal control systems, in particular to a universal control system board. Background Art

[0002] Universal control system boards are hardware components designed for a variety of control system applications. They can be integrated into various automation and control systems to achieve control functions. Currently, the control module in the universal control system board uses SoC technology, which integrates a general processing unit (usually an ARM processor) with programmable logic (FPGA) on a single chip, known as the ZYNQ universal control module.

[0003] At present, the types and number of peripheral interfaces of the existing ZYNQ universal control module, the speed of the externally supported network interface, and the memory capacity of the memory carried by the ZYNQ universal control module can no longer meet the needs of actual applications. Therefore, it is necessary to design a ZYNQ universal control module with large memory capacity, high external network interface speed, and a large number of peripheral interfaces, so that the universal control system board can be applied to calculation, control, acquisition, and storage in various scenarios. Utility Model Content

[0004] In order to overcome the above-mentioned technical problems existing in the prior art, an embodiment of the utility model provides a universal control system board, which increases the number and types of external support interfaces of the universal control system board by connecting a logic control interface, a processing interface and multiple storage modules on the FPGA chip in the universal control system board, and also increases the memory capacity of the universal control system board.

[0005] In order to achieve the above-mentioned purpose, an embodiment of the utility model provides a universal control system board, which includes an ARM processor and an FPGA chip that is communicatively connected to each other; the FPGA chip includes a PL end and a PS end, the PL end is connected to a corresponding logic control interface, and the PS end is connected to a corresponding processing interface; the logic control interface includes a bus expansion interface, an I / O interface and a 1553B interface connected to the FPGA chip; the processing interface includes multiple storage modules and multiple communication interfaces connected to the FPGA chip; the ARM processor is connected to a USB interface.

[0006] Preferably, the bus extension interface includes a first drive buffer and a first RS422 interface, an SPI interface, an RS485 interface and a CAN interface respectively connected to the first drive buffer, one end of the first drive buffer is connected to the FPGA chip, and the other end is connected to the first RS422 interface, the SPI interface, the RS485 interface and the CAN interface.

[0007] Preferably, a first analog switch is connected between the first drive buffer and the first RS422 interface, a second analog switch is connected between the first drive buffer and the SPI interface, and a third analog switch is connected between the first drive buffer and the RS485 interface.

[0008] Preferably, the PL end is also connected to the ADC module, the FlexRay bus and the JTAG debugging interface respectively; the 1553B interface is connected to the PL end through the corresponding protocol chip; and the I / O interface is connected to the PL end through the second driver buffer.

[0009] Preferably, the multiple storage modules include FLASH, DDR3 memory chips and eMMC memory; the eMMC memory is connected to the PS end through a fourth analog switch; the multiple communication interfaces include a first network interface, a second network interface, a second RS422 interface and an I2C interface; the second RS422 interface is connected to the PS end through a corresponding conversion chip; the I2C interface is connected to the PS end through a third drive buffer; a fifth analog switch is connected between the I2C interface and the third drive buffer.

[0010] Preferably, the capacity of the eMMC memory is 64GB, and the capacity of the DDR3 memory chip is 1GB and the speed is 1600Mbps.

[0011] Preferably, the first network interface and the second network interface are both RJ45 interfaces / optical fiber interfaces, and the first network interface and the second network interface are both connected to the PS end through corresponding Ethernet physical layers.

[0012] Preferably, the USB interface is connected to the ARM processor through a corresponding USB physical layer, and the first power module of the ARM processor is connected to an external DC power supply through a first DCDC module.

[0013] Preferably, the second power supply module of the FPGA chip is connected to the external DC power supply through a second DCDC module.

[0014] Preferably, the model of the FPGA chip is: FMQL45T900 or FMQL20S400.

[0015] Through the technical solution provided by the utility model, the utility model has at least the following technical effects:

[0016] By connecting a bus expansion interface, an I / O interface, a 1553B interface, multiple communication interfaces and multiple storage modules on the FPGA chip in the universal control system board, the number and types of external support interfaces of the universal control system board are increased, and the memory capacity of the universal control system board is also increased, so that the universal control system board can be applied to calculation, control, acquisition and storage in various scenarios.

[0017] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present utility model and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present utility model, but do not constitute a limitation on the embodiments of the present utility model. In the accompanying drawings:

[0019] Figure 1 It is a structural schematic diagram of a universal control system board provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0020] The specific implementation of the embodiment of the utility model is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the utility model, and is not used to limit the embodiment of the utility model.

[0021] The terms "system" and "network" in the embodiments of the present invention can be used interchangeably. "Multiple" refers to two or more than two. In view of this, in the embodiments of the present invention, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, it should be understood that in the description of the embodiments of the present invention, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0022] See also Figure 1An embodiment of the utility model provides a universal control system board, which includes an ARM processor and an FPGA chip that is communicatively connected to each other; the FPGA chip includes a PL terminal and a PS terminal, the PL terminal is connected to a corresponding logic control interface, and the PS terminal is connected to a corresponding processing interface; the logic control interface includes a bus expansion interface, an I / O interface and a 1553B interface connected to the FPGA chip; the processing interface includes multiple storage modules and multiple communication interfaces connected to the FPGA chip; the ARM processor is connected to a USB interface.

[0023] In the embodiment of the utility model, the general control system board can be adapted to VxWorks6.9, domestic Ruihua, Yihui and other operating systems. The main control of the general control system board adopts a domestic multi-core PSOC processor. The general control system board includes an ARM processor and an FPGA chip. The ARM processor and the FPGA chip are communicated with each other. For the FPGA chip, the FPGA chip adopts a domestic chip, for example, a chip with model FMQL45T900 or FMQL20S400 produced by Fudan Microelectronics, and the main frequency of the FPGA chip is 800MHz, and the number of cores is 4. The FPGA chip includes a programmable logic end (PL end) and a processing system end (PS end). A logic control interface is connected to the PL end of the FPGA chip, and a processing interface is connected to the PS end of the FPGA chip.

[0024] Specifically, the logic control interface connected to the PL end of the FPGA chip includes a bus expansion interface, an I / O interface and a 1553B interface, and the bus expansion interface includes a first drive buffer and a first RS422 interface, an SPI interface, an RS485 interface and a CAN interface respectively connected to the first drive buffer. A first analog switch is connected between the first drive buffer and the first RS422 interface for loopback self-test, and the first RS422 interface is configured as an interface with 8 independent RS422 channels; a second analog switch is connected between the SPI interface and the first drive buffer for the convenience of loopback self-test, and the SPI interface is configured as an SPI interface with 2 independent channels; a third analog switch is also connected between the RS485 interface and the first drive buffer for the convenience of loopback self-test, and the RS485 interface is configured as an interface with a single RS485 communication channel; the CAN interface is configured as an interface with two independent CAN channels. Furthermore, in order to achieve efficient and reliable 1553B communication, the 1553B interface can be connected to the PL end of the FPGA chip through the corresponding 1553B interface protocol chip, and the 1553B interface is configured as an interface with one MIL-STD-1553B communication channel or bus; for the I / O interface, it can be connected to the PL end of the FPGA chip through the second driver buffer, and the I / O interface is configured to have 120 input / output ports, that is, the I / O interface can process 120 input or output signals at the same time to meet the needs of large-scale data acquisition and control. Furthermore, the PL end of the FPGA chip can also be connected to the ADC module, FlexRay bus and JTAG debugging interface respectively, where the ADC module is configured as an analog-to-digital converter (ADC) with 16 independent analog input channels.

[0025] Specifically, the processing interface connected to the PS end of the FPGA chip includes multiple storage modules and multiple communication interfaces; wherein the multiple storage modules include FLASH memory, DDR3 memory module and eMMC memory, the memory capacity of the DDR3 memory chip is 1GB, the rate of the DDR3 memory chip is 1600Mbps, the eMMC memory can be connected to the PS end of the FPGA chip through a fourth analog switch, and the memory capacity of the eMMC memory is 64GB, and the FLASH memory, DDR3 memory module and eMMC memory provided in this embodiment are connected to the PS end of the FPGA chip to increase the memory capacity of the general control system board. For multiple communication interfaces, the multiple communication interfaces include a first network interface, a second network interface, a second RS422 interface and an I2C interface; wherein, the first network interface and the second network interface are both RJ45 interfaces / optical fiber interfaces, that is, the first network interface and the second network interface can both be connected to the Ethernet through the RJ45 interface, and the Ethernet configuration is 1000M Ethernet, and can also be connected to the optical fiber network through the optical fiber interface, and the first network interface can be connected to the PS end of the FPGA chip through the corresponding Ethernet physical layer (ETH PHY), and the second network interface can also be connected to the PS end through the corresponding ETH PHY; the second RS422 interface can be connected to the PS end of the FPGA chip through the corresponding RS422 conversion chip, the second RS422 interface is configured to have an interface using the RS422 communication standard, and the RS422 interface can be used for debugging and communication; the I2C interface is connected to the PS end of the FPGA chip through the third driver buffer, and a fifth analog switch is connected between the I2C interface and the third driver buffer to facilitate loopback self-test, and the I2C interface is configured to have an interface with 2 independent I2C channels. Furthermore, the power module that supplies power to the FPGA chip may be connected to an external DC power supply through a corresponding DC / DC converter, and the external DC power supply may be a +5V DC power supply.

[0026] In an embodiment of the utility model, the ARM processor in the general control system board can also be connected to the USB interface, and the USB interface is connected to the ARM processor through the corresponding USB physical layer, and the configuration of the USB physical layer is the physical layer of the USB 2.0 version (USB 2.0 PHY), and the configuration of the USB interface is a single USB interface; the power module that supplies power to the ARM processor is also connected to the external DC power supply through the corresponding DC / DC converter, and the DC / DC converter can also be communicated with the USB interface, and this external DC power supply is the same external power supply as the external DC power supply connected to the power module of the FPGA chip.

[0027] Preferably, the dimensions of the universal control system board provided in this embodiment are 160 mm in length and 100 mm in width, and the power consumption of the universal control system board is less than or equal to 8W.

[0028] Through the universal control system board provided in this embodiment, the RS422 interface, SPI interface, RS485 interface, CAN interface, I / O interface, 1553B interface, ADC module, FlexRay bus and JTAG debugging interface and other logical control interfaces are connected at the PL end of the FPGA chip, so that the universal control system board is suitable for control applications in multiple scenarios; further, a 64GB eMMC memory, a 1GB DDR3 memory and a FLASH memory are connected at the PS end of the FPGA chip to expand the memory capacity of the universal control system board; and the first network interface, the second network interface, the second RS422 interface and the I2C interface and other communication interfaces are also connected at the PS end, so that the universal control system board can be applicable to multiple communication interfaces; by increasing the number and types of externally supported interfaces of the universal control system board, the universal control system board supports online upgrades in various forms such as network ports, serial ports, USB ports, etc. The universal control system board provided in this embodiment can also be applicable to calculation, control, acquisition, storage and other applications in various scenarios.

[0029] The optional implementation modes of the embodiments of the utility model are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the utility model are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the utility model, the technical scheme of the embodiments of the utility model can be subjected to various simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the utility model.

[0030] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the utility model will not further describe various possible combinations.

[0031] In addition, various implementations of the embodiments of the present utility model can also be arbitrarily combined, as long as they do not violate the concept of the embodiments of the present utility model, they should also be regarded as the contents disclosed in the embodiments of the present utility model.

Claims

1. A universal control system board, characterized in that: The universal control system board includes an ARM processor and an FPGA chip that is communicatively connected to each other; The FPGA chip includes a PL terminal and a PS terminal, the PL terminal is connected to a corresponding logic control interface, and the PS terminal is connected to a corresponding processing interface; The logic control interface includes a bus expansion interface, an I / O interface and a 1553B interface connected to the FPGA chip; The processing interface includes a plurality of storage modules and a plurality of communication interfaces connected to the FPGA chip; The ARM processor is connected to the USB interface.

2. The universal control system board according to claim 1, characterized in that: The bus extension interface includes a first drive buffer and a first RS422 interface, an SPI interface, an RS485 interface and a CAN interface respectively connected to the first drive buffer; one end of the first drive buffer is connected to the FPGA chip, and the other end is connected to the first RS422 interface, the SPI interface, the RS485 interface and the CAN interface.

3. The universal control system board according to claim 2, characterized in that: A first analog switch is connected between the first drive buffer and the first RS422 interface, a second analog switch is connected between the first drive buffer and the SPI interface, and a third analog switch is connected between the first drive buffer and the RS485 interface.

4. The universal control system board according to claim 1, characterized in that: The PL side is also connected to the ADC module, FlexRay bus, and JTAG debug interface; The 1553B interface is connected to the PL terminal via a corresponding protocol chip; The I / O interface is connected to the PL terminal through a second driving buffer.

5. The universal control system board according to claim 1, characterized in that: The multiple storage modules include FLASH, DDR3 memory chip and eMMC memory; The eMMC memory is connected to the PS terminal via a fourth analog switch; The multiple communication interfaces include a first network interface, a second network interface, a second RS422 interface and an I2C interface; The second RS422 interface is connected to the PS terminal via a corresponding conversion chip; The I2C interface is connected to the PS terminal via a third driver buffer; A fifth analog switch is connected between the I2C interface and the third driving buffer.

6. The universal control system board according to claim 5, characterized in that: The capacity of the eMMC memory is 64GB, and the capacity of the DDR3 memory chip is 1GB and the speed is 1600Mbps.

7. The universal control system board according to claim 5, characterized in that: The first network interface and the second network interface are both RJ45 interfaces / optical fiber interfaces, and the first network interface and the second network interface are both connected to the PS end through corresponding Ethernet physical layers.

8. The universal control system board according to claim 1, characterized in that: The USB interface is connected to the ARM processor via a corresponding USB physical layer, and the first power module of the ARM processor is connected to an external direct current power supply via a first DCDC module.

9. The universal control system board according to claim 8, characterized in that: The second power supply module of the FPGA chip is connected to the external DC power supply through a second DCDC module.

10. The universal control system board according to claim 1, characterized in that: The model of the FPGA chip is: FMQL45T900 or FMQL20S400.

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