Data driver and display device

Abstract

The utility model relates to a data driver and a display device. The display device includes: a display panel including a plurality of pixels and a plurality of data lines connected to the plurality of pixels; and a data driver providing a plurality of data voltages to the plurality of data lines, respectively. The data driver includes: a plurality of channels in which each of the plurality of channels outputs an nth data voltage in an nth horizontal period and outputs an (n + 1) th data voltage in an (n + 1) th horizontal period, where n is a natural number other than zero; a common line; a plurality of data switches selectively connecting the plurality of channels to the plurality of data lines, respectively; a plurality of common switches, each of the plurality of common switches selectively connecting a corresponding one of the plurality of channels to the common line; and a voltage sensor sensing a common voltage of the common line.

Description

Technical Field

[0001] Embodiments relate to a display device, and more particularly, to a display device, a data driver included in the display device, and a method for driving the display device. Background Art

[0002] The display device may include a data driver configured to provide a data voltage to the data line. The data driver may include a channel configured to output the data voltage. The channel may output the data voltage to the data line for each horizontal period.

[0003] When the voltage level of the data voltage output from the channel changes, power consumption for outputting the data voltage may increase. Therefore, when the channel alternately outputs a data voltage having a high voltage level and a data voltage having a low voltage level to the data line for each horizontal period, power consumption of the data driver may increase. Utility Model Content

[0004] The embodiment provides a display device in which power consumption is reduced.

[0005] The embodiment provides a data driver in which power consumption is reduced.

[0006] The embodiment provides a method for driving a display device to reduce power consumption.

[0007] A display device according to an embodiment includes: a display panel including a plurality of pixels and a plurality of data lines connected to the plurality of pixels; and a data driver providing a plurality of data voltages to the plurality of data lines, respectively. In such an embodiment, the data driver includes: a plurality of channels, wherein each of the plurality of channels outputs an nth data voltage (where n is a natural number other than zero) in an nth horizontal period, and outputs an n+1th data voltage in an n+1th horizontal period; a common line; a plurality of data switches selectively connecting the plurality of channels to the plurality of data lines, respectively; a plurality of common switches, wherein each of the plurality of common switches selectively connects a corresponding one of the plurality of channels to the common line; and a voltage sensor sensing a common voltage of the common line.

[0008] In an embodiment, the data driver may further include: a voltage comparator comparing the common voltage with the nth data voltage and the (n+1)th data voltage.

[0009] In an embodiment, when the common voltage is between an nth data voltage of a channel among a plurality of channels and an (n+1)th data voltage of the channel, the channel may be connected to a common line through a common switch corresponding to the channel among a plurality of common switches.

[0010] In an embodiment, the data driver may further include: a capacitor connected between the common line and the ground.

[0011] In an embodiment, the data driver may further include: a plurality of capacitors connected to a ground; and a plurality of capacitor switches, wherein each of the plurality of capacitor switches selectively connects a corresponding one of the plurality of capacitors to a common line.

[0012] In an embodiment, the capacitances of the capacitors may be equal to each other.

[0013] In an embodiment, the capacitances of the capacitors may be different from each other.

[0014] In an embodiment, the common voltage may be increased or decreased by selective operation of a plurality of capacitor switches.

[0015] In an embodiment, when the common voltage is less than the minimum reference voltage, the common voltage may be increased.

[0016] In an embodiment, when the common voltage is greater than the maximum reference voltage, the common voltage may be decreased.

[0017] In an embodiment, each of the plurality of data lines may extend in a first direction, and the common line may extend in a second direction crossing the first direction.

[0018] In an embodiment, the display device may further include a scan driver providing a plurality of scan signals to the pixels, and a controller controlling the data driver and the scan driver.

[0019] According to an embodiment, a data driver that provides multiple data voltages to multiple data lines respectively includes: multiple channels, wherein each of the multiple channels outputs an nth data voltage (wherein n is a natural number other than zero) in an nth horizontal period and outputs an n+1th data voltage in an n+1th horizontal period; a common line; multiple data switches that selectively connect the multiple channels to the multiple data lines, respectively; multiple common switches, wherein each of the multiple common switches selectively connects a corresponding one of the multiple channels to the common line; and a voltage sensor that senses a common voltage of the common line.

[0020] In an embodiment, the data driver may further include: a voltage comparator comparing the common voltage with the nth data voltage and the (n+1)th data voltage.

[0021] In an embodiment, when the common voltage is between an nth data voltage of a channel among a plurality of channels and an (n+1)th data voltage of the channel, the channel may be connected to a common line through a common switch corresponding to the channel among a plurality of common switches.

[0022] In an embodiment, the data driver may further include: a plurality of capacitors connected to a ground; and a plurality of capacitor switches, wherein each of the plurality of capacitor switches selectively connects a corresponding one of the plurality of capacitors to a common line.

[0023] A method for driving a display device according to an embodiment includes: outputting an nth data voltage from a channel to a data line; latching an n+1th data voltage to the channel, wherein n is a natural number other than zero; sensing a common voltage of a common line; comparing the common voltage with the nth data voltage and the n+1th data voltage; connecting the channel to the common line when the common voltage is between the nth data voltage and the n+1th data voltage; and outputting the n+1th data voltage from the channel to the data line.

[0024] In an embodiment, the method may further include increasing or decreasing the common voltage after connecting the channel to the common line and before outputting the (n+1)th data voltage.

[0025] In an embodiment, increasing or decreasing the common voltage may include increasing the common voltage when the common voltage is less than a minimum reference voltage.

[0026] In an embodiment, increasing or decreasing the common voltage may include decreasing the common voltage when the common voltage is greater than a maximum reference voltage.

[0027] In a display device and a data driver included in the display device according to an embodiment of the present disclosure, a voltage sensor can sense a common voltage of a common line, and channels can share charges through the common line, so that data voltages of the channels can be precharged and power consumption of the data driver can be reduced.

[0028] In a method for driving a display device according to an embodiment of the present disclosure, a common voltage of a common line can be sensed, and by comparing the common voltage with an nth data voltage and an n+1th data voltage, channels can share charges through the common line, so that the data voltages of the channels can be precharged and the power consumption of the data driver can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is a block diagram illustrating a data driver according to an embodiment of the present disclosure.

[0032] Figure 3 Is used to describe Figure 21 and 2. A timing diagram of an n-th horizontal period and an (n+1)-th horizontal period of a data driver shown in FIG.

[0033] Figures 4 to 9 Is used to describe Figure 2 A view of the operations of the data drive.

[0034] Fig.10 is a block diagram illustrating a data driver according to an embodiment of the present disclosure.

[0035] Fig.11 is a flowchart illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0036] Fig.12 is a flowchart illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0037] Fig.13 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0039] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or intervening elements can exist between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0040] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the first element, component, region, layer or portion discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings herein.

[0041] The term used herein is only used to describe the purpose of specific embodiments, and is not intended to be limited. As used herein, "one", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. Therefore, in the claim, mentioning "one" element (after mentioning "the" element) includes one element and a plurality of these elements. For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in association. It will be further understood that when used in this specification, the term "comprising" and / or "including" indicates the existence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their groups.

[0042] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element relative to another element as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are intended to cover different orientations of the device. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the accompanying drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below" or "below" can cover both upper and lower orientations.

[0043] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0045] The embodiments described herein should not be construed as being limited to the specific shapes of the regions illustrated herein, but should include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may generally have rough and / or nonlinear features. In addition, illustrated sharp corners may be rounded. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions illustrated in the accompanying drawings are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the present invention.

[0046] Hereinafter, a display device, a data driver, and a method for driving the display device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0047] Figure 1 is a block diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0048] refer to Figure 1 , an embodiment of the display device 100 may include a display panel 110 , a scan driver 120 , a data driver 130 , and a controller 140 .

[0049] The display panel 110 may include pixels PX, data lines DL, and scan lines SL. According to an embodiment, the pixel PX may include a first pixel emitting light having a first color, a second pixel emitting light having a second color, and a third pixel emitting light having a third color. In an embodiment, for example, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0050] According to an embodiment, the pixel PX may include an organic light emitting diode. According to another embodiment, the pixel PX may include an inorganic light emitting diode, a micro light emitting diode, a quantum dot light emitting diode, or the like.

[0051] The scan lines SL may be connected to the pixels PX. The scan lines SL may be arranged in a first direction DR1. Each of the scan lines SL may extend in a second direction DR2. The second direction DR2 may cross the first direction DR1. According to an embodiment, the second direction DR2 may be perpendicular to the first direction DR1.

[0052] The data lines DL may be connected to the pixels PX. The data lines DL may be arranged in the second direction DR2. Each of the data lines DL may extend in the first direction DR1. The data lines DL may cross the scan lines SL.

[0053] The scan driver 120 may provide a scan signal SS to the scan line SL. The scan driver 120 may sequentially generate the scan signals SS respectively corresponding to the pixel rows based on the first control signal CNT1. The first control signal CNT1 may include a scan clock signal and / or a scan start signal, etc.

[0054] The data driver 130 may provide a data voltage VDAT to the data line DL. The data driver 130 may generate data voltages VDAT corresponding to the pixel columns respectively based on the second image data IMD2 and the second control signal CNT2. According to an embodiment, the second image data IMD2 may include grayscale values ​​corresponding to the pixels PX respectively. The second control signal CNT2 may include a data clock signal, a horizontal start signal and / or a load signal, etc.

[0055] The controller 140 may control the operation (or driving) of the scan driver 120 and the operation (or driving) of the data driver 130. The controller 140 may generate a first control signal CNT1, a second control signal CNT2, and a second image data IMD2 based on the first image data IMD1 and the control signal CNT. According to an embodiment, the first image data IMD1 may include grayscale (or grayscale) values ​​corresponding to the pixels PX, respectively. The controller 140 may convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, and / or a data enable signal, etc.

[0056] Figure 2 is a block diagram illustrating the data driver 130 according to an embodiment of the present disclosure.

[0057] refer to Figure 2 In an embodiment, the data driver 130 may include first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1 and CHm (wherein m is a natural number greater than or equal to 6), a common line CML, a capacitor CP, first to mth data switches SD1, SD2, SD3, SD4, ..., SDm-1 and SDm, first to mth common switches SCM1, SCM2, SCM3, SCM4 ..., SCMm-1 and SCMm, a voltage sensor 132 and a voltage comparator 134.

[0058] Each of the first to m-th channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm may output a data voltage VDAT in a horizontal period. In an embodiment, for example, each of the first to m-th channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm may output an n-th data voltage VDAT[n] (where n is a natural number other than zero) in an n-th horizontal period, and output an n+1-th data voltage VDAT[n+1] in an n+1-th horizontal period. The first to m-th channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm may be arranged in the second direction DR2.

[0059] The common line CML may be disposed between the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm and the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm. The common line CML may extend in the second direction DR2.

[0060] The capacitor CP may be connected between the common line CML and the ground. The capacitor CP may be directly connected to the common line CML. The capacitor CP may store a common voltage VCOM of the common line CML.

[0061] The first to mth data switches SD1, SD2, SD3, SD4, ..., SDm-1, and SDm may selectively connect the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm, respectively. The first data switch SD1 may selectively connect the first channel CH1 to the first data line DL1, the second data switch SD2 may selectively connect the second channel CH2 to the second data line DL2, the third data switch SD3 may selectively connect the third channel CH3 to the third data line DL3, the fourth data switch SD4 may selectively connect the fourth channel CH4 to the fourth data line DL4, the m-1th data switch SDm-1 may selectively connect the m-1th channel CHm-1 to the m-1th data line DLm-1, and the m-th data switch SDm may selectively connect the m-th channel CHm to the m-th data line DLm. The first data switch SD1 may be connected between the first node N1 of the first channel CH1 and the first data line DL1, the second data switch SD2 may be connected between the second node N2 of the second channel CH2 and the second data line DL2, the third data switch SD3 may be connected between the third node N3 of the third channel CH3 and the third data line DL3, the fourth data switch SD4 may be connected between the fourth node N4 of the fourth channel CH4 and the fourth data line DL4, the m-1th data switch SDm-1 may be connected between the m-1th node Nm-1 of the m-1th channel CHm-1 and the m-1th data line DLm-1, and the m-th data switch SDm may be connected between the m-th node Nm of the m-1th channel CHm and the m-1th data line DLm.

[0062] The first to m-th common switches SCM1, SCM2, SCM3, SCM4, ..., SCMm-1, and SCMm may selectively connect the first to m-th channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm to the common line CML. The first common switch SCM1 may selectively connect the first channel CH1 to the common line CML, the second common switch SCM2 may selectively connect the second channel CH2 to the common line CML, the third common switch SCM3 may selectively connect the third channel CH3 to the common line CML, the fourth common switch SCM4 may selectively connect the fourth channel CH4 to the common line CML, the m-1-th common switch SCMm-1 may selectively connect the m-1-th channel CHm-1 to the common line CML, and the m-th common switch SCMm may selectively connect the m-th channel CHm to the common line CML. The first common switch SCM1 may be connected between the first node N1 and the common line CML, the second common switch SCM2 may be connected between the second node N2 and the common line CML, the third common switch SCM3 may be connected between the third node N3 and the common line CML, the fourth common switch SCM4 may be connected between the fourth node N4 and the common line CML, the m-1th common switch SCMm-1 may be connected between the m-1th node Nm-1 and the common line CML, and the mth common switch SCMm may be connected between the mth node Nm and the common line CML.

[0063] The voltage sensor 132 may sense the common voltage VCOM of the common line CML in response to the voltage sensing signal VSS. The voltage sensor 132 may provide the common voltage VCOM to the voltage comparator 134.

[0064] The voltage comparator 134 may compare the common voltage VCOM with the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] in response to the voltage comparison signal VCS. The voltage comparator 134 may compare the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] of each of the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm with the common voltage VCOM.

[0065] In the following, reference will be made to Figures 3 to 9 To describe Figure 2 The operation of the data driver 130 is as follows.

[0066] Figure 3 Is used to describe Figure 2 1 and 2. A timing diagram of an n-th horizontal period HP[n] and an (n+1)-th horizontal period HP[n+1] of the data driver 130 is shown in FIG. Figures 4 to 9 Is used to describe Figure 2FIG. 1 is a view of the operation of the data driver 130 .

[0067] For ease of illustration and description, reference will be made to Figures 3 to 9 Provided Figure 2 The description of the operation of the data driver 130 will focus on the first to fourth channels CH1, CH2, CH3 and CH4 and the first to fourth data switches SD1, SD2, SD3 and SD4 and the first to fourth common switches SCM1, SCM2, SCM3 and SCM4 connected to the first to fourth channels CH1, CH2, CH3 and CH4. Figures 3 to 9 Description Figure 2 In the operation of the data driver 130, it will be understood that the first channel CH1 outputs an nth data voltage VDAT[n] of about 5 volts (V) in the nth horizontal period HP[n], and outputs an n+1th data voltage VDAT[n+1] of about 0 V in the n+1th horizontal period HP[n+1], and the second channel CH2 outputs an nth data voltage VDAT[n] of about 5 V in the nth horizontal period HP[n], and outputs an n+1th data voltage VDAT[n] of about 5 V in the n+1th horizontal period HP[n+1]. VDAT[n+1], the third channel CH3 outputs the nth data voltage VDAT[n] of approximately 0V in the nth horizontal period HP[n], and outputs the n+1th data voltage VDAT[n+1] of approximately 5V in the n+1th horizontal period HP[n+1], and the fourth channel CH4 outputs the nth data voltage VDAT[n] of approximately 0V in the nth horizontal period HP[n], and outputs the n+1th data voltage VDAT[n+1] of approximately 0V in the n+1th horizontal period HP[n+1].

[0068] refer to Figure 2 and Figure 3 , the horizontal period HP may include a first period P1, a second period P2, a third period P3, a fourth period P4 and a fifth period P5.

[0069] The first to fourth data switches SD1, SD2, SD3 and SD4 may be turned on in the first period P1 and turned off in the second to fifth periods P2, P3, P4 and P5. The latch signal LS may have a turn-on voltage level in the second period P2 and a turn-off voltage level in the first and third to fifth periods P1, P3, P4 and P5. The voltage sensing signal VSS may have a turn-on voltage level in the third period P3 and a turn-off voltage level in the first, second, fourth and fifth periods P1, P2, P4 and P5. The voltage comparison signal VCS may have a turn-on voltage level in the fourth period P4 and a turn-off voltage level in the first to third and fifth periods P1, P2, P3 and P5. The first to fourth common switches SCM1, SCM2, SCM3 and SCM4 may be selectively turned on in the fifth period P5 and turned off in the first to fourth periods P1, P2, P3 and P4.

[0070] refer to Figure 3 and Figure 4 , in the first period P1 of the nth horizontal period HP[n], the first to fourth channels CH1, CH2, CH3, and CH4 may output the nth data voltage VDAT[n]. The first to fourth data switches SD1, SD2, SD3, and SD4 may be turned on, and the first to fourth channels CH1, CH2, CH3, and CH4 may be connected to the first to fourth data lines DL1, DL2, DL3, and DL4, respectively. Therefore, the nth data voltage VDAT[n] outputted from the first to fourth channels CH1, CH2, CH3, and CH4 may be transmitted to the first to fourth data lines DL1, DL2, DL3, and DL4, respectively.

[0071] refer to Figure 3 and Figure 5 , in the second period P2 of the nth horizontal period HP[n], the first to fourth data switches SD1, SD2, SD3, and SD4 may be turned off, and the latch signal LS may have a turn-on voltage level. In response to the latch signal LS having the turn-on voltage level, the n+1th data voltage VDAT[n+1] may be latched to the first to fourth channels CH1, CH2, CH3, and CH4.

[0072] refer to Figure 3 and Figure 6 In the third period P3 of the nth horizontal period HP[n], the voltage sensing signal VSS may have a turn-on voltage level. In response to the voltage sensing signal VSS having the turn-on voltage level, the voltage sensor 132 may sense the common voltage VCOM of the common line CML.

[0073] refer to Figure 3 and Figure 7, in the fourth period P4 of the nth horizontal period HP[n], the voltage comparison signal VCS may have an on voltage level. In response to the voltage comparison signal VCS having the on voltage level, the voltage comparator 134 may compare the common voltage VCOM with the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1]. The voltage comparator 134 may compare the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] of each of the first to fourth channels CH1, CH2, CH3, and CH4 with the common voltage VCOM.

[0074] refer to Figure 3 and Figure 8 , a channel of the common voltage VCOM between the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] among the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1 and CHm can be connected to the common line CML through a common switch corresponding to the channel. In an embodiment, for example, Figure 3 As shown in , when the common voltage VCOM is approximately 3V, the common voltage VCOM may be between the nth data voltage VDAT[n] (approximately 5V) and the n+1th data voltage VDAT[n+1] (approximately 0V) of the first channel CH1, and may be between the nth data voltage VDAT[n] (approximately 0V) and the n+1th data voltage VDAT[n+1] (approximately 5V) of the third channel CH3. Therefore, the first common switch SCM1 and the third common switch SCM3 may be turned on, and the second common switch SCM2 and the fourth common switch SCM4 may be turned off. The first channel CH1 and the third channel CH3 may be connected to the common line CML through the first common switch SCM1 and the third common switch SCM3, respectively. Therefore, the first channel CH1 and the third channel CH3 may share charge through the common line CML. In addition, since the common line CML is connected to the first channel CH1 and the third channel CH3, the voltage level of the common voltage VCOM may change. In an embodiment, for example, as Figure 3 As shown in , the voltage of the first node N1 of the first channel CH1, the voltage of the third node N3 of the third channel CH3, and the common voltage VCOM may be changed to about 2V.

[0075] refer to Figure 3 and Fig. 9, in the first period P1 of the n+1th horizontal period HP[n+1], the first to fourth channels CH1, CH2, CH3, and CH4 may output the n+1th data voltage VDAT[n+1]. The first to fourth data switches SD1, SD2, SD3, and SD4 may be turned on, and the first to fourth channels CH1, CH2, CH3, and CH4 may be connected to the first to fourth data lines DL1, DL2, DL3, and DL4, respectively. Therefore, the n+1th data voltage VDAT[n+1] outputted from the first to fourth channels CH1, CH2, CH3, and CH4 may be transmitted to the first to fourth data lines DL1, DL2, DL3, and DL4, respectively.

[0076] Since the first channel CH1 and the third channel CH3 share charges in the fifth period P5 of the nth horizontal period HP[n], the first channel CH1 and the third channel CH3 can precharge the n+1th data voltage VDAT[n+1] output in the first period P1 of the n+1th horizontal period HP[n+1]. Therefore, in the first period P1 of the n+1th horizontal period HP[n+1], the variation in the n+1th data voltage VDAT[n+1] output from the first channel CH1 and the third channel CH3 can be reduced, and the power consumption of the data driver 130 can be reduced.

[0077] Fig.10 is a block diagram illustrating a data driver 130 - 1 according to an embodiment of the present disclosure.

[0078] refer to Fig.10 In an embodiment, the data driver 130-1 may include first to m-th channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm, a common line CML, first to third capacitors CP1, CP2, and CP3, first to m-th data switches SD1, SD2, SD3, SD4, ..., SDm-1, and SDm, first to m-th common switches SCM1, SCM2, SCM3, SCM4, ..., SCMm-1, and SCMm, first to third capacitor switches SCP1, SCP2, and SCP3, a voltage sensor 132, and a voltage comparator 134. In reference to Fig.10 When describing the data driver 130-1, the reference numerals will be omitted. Figure 2 Components of the described data driver 130 are substantially the same as or similar to any repeated detailed descriptions of the components.

[0079] In an embodiment, the first to third capacitors CP1, CP2, and CP3 may be connected to the ground. The first to third capacitors CP1, CP2, and CP3 may store a common voltage VCOM of the common line CML.

[0080] According to an embodiment, the capacitances of the first to third capacitors CP1, CP2, and CP3 may be equal to each other. According to another embodiment, the capacitances of the first to third capacitors CP1, CP2, and CP3 may be different from each other.

[0081] The first to third capacitor switches SCP1, SCP2, and SCP3 may selectively connect the first to third capacitors CP1, CP2, and CP3 to the common line CML. The first capacitor switch SCP1 may selectively connect the first capacitor CP1 to the common line CML, the second capacitor switch SCP2 may selectively connect the second capacitor CP2 to the common line CML, and the third capacitor switch SCP3 may selectively connect the third capacitor CP3 to the common line CML.

[0082] The common voltage VCOM of the common line CML can be increased or decreased by the selective operation of the first to third capacitor switches SCP1, SCP2 and SCP3. When the amount of charge charged to the common line CML is constant, the common voltage VCOM can be increased when the equivalent capacitance of the common line CML is reduced, and the common voltage VCOM can be reduced when the equivalent capacitance of the common line CML is increased. Therefore, in such an embodiment, the common voltage VCOM can be increased or decreased by controlling the equivalent capacitance of the common line CML through the selective operation of the first to third capacitor switches SCP1, SCP2 and SCP3.

[0083] According to an embodiment, when the common voltage VCOM is less than the minimum reference voltage, the common voltage VCOM can be increased by controlling the first to third capacitor switches SCP1, SCP2 and SCP3. The minimum reference voltage may be a lower limit of the common voltage VCOM. In an embodiment, for example, when the first capacitor switch SCP1 and the second capacitor switch SCP2 are turned on and the third capacitor switch SCP3 is turned off, when the common voltage VCOM is less than the minimum reference voltage, the equivalent capacitance of the common line CML can be reduced by turning off the first capacitor switch SCP1 or the second capacitor switch SCP2, so that the common voltage VCOM can be increased.

[0084] According to an embodiment, when the common voltage VCOM is greater than the maximum reference voltage, the common voltage VCOM may be reduced by controlling the first to third capacitor switches SCP1, SCP2, and SCP3. The maximum reference voltage may be an upper limit of the common voltage VCOM. In an embodiment, for example, when the first capacitor switch SCP1 and the second capacitor switch SCP2 are turned on and the third capacitor switch SCP3 is turned off, when the common voltage VCOM is greater than the maximum reference voltage, the equivalent capacitance of the common line CML may be increased by turning on the third capacitor switch SCP3, so that the common voltage VCOM may be reduced.

[0085] although Fig.10 , an embodiment in which the data driver 130-1 includes three capacitors CP1, CP2, and CP3 selectively connected to the common line CML is shown, but the present disclosure is not limited thereto. According to another embodiment, the data driver 130-1 may include two capacitors or four or more capacitors selectively connected to the common line CML.

[0086] Fig.11 is a flowchart illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0087] refer to Figure 4 and Fig.11 According to an embodiment of the method for driving a display device, an nth data voltage VDAT[n] may be output from the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm (step S110). The first to mth data switches SD1, SD2, SD3, SD4, ..., SDm-1, and SDm may be turned on, and the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm may be connected to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm, respectively. Therefore, the nth data voltage VDAT[n] output from the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm may be transmitted to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm, respectively.

[0088] refer to Figure 5 and Fig.11 , the n+1th data voltage VDAT[n+1] may be latched to the first to mth channels CH1, CH2, CH3, CH4, . . . , CHm-1, and CHm (step S120).

[0089] refer to Figure 6 and Fig.11 , the common voltage VCOM of the common line CML may be sensed (step S130 ). In response to the voltage sensing signal VSS having the turn-on voltage level, the voltage sensor 132 may sense the common voltage VCOM of the common line CML.

[0090] refer to Figure 7 and Fig.11, the common voltage VCOM may be compared with the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] (step S140). In response to the voltage comparison signal VCS having a turn-on voltage level, the voltage comparator 134 may compare the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] of each of the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm with the common voltage VCOM.

[0091] refer to Figure 8 and Fig.11 , when the common voltage VCOM is between the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] of the channel, the channel can be connected to the common line CML (step S150). Among the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1 and CHm, the channel whose common voltage VCOM is between the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] can be connected to the common line CML through the common switch corresponding to the channel. In an embodiment, for example, as Figure 8 As shown in FIG. 1 , when the common voltage VCOM is between the nth data voltage VDAT[n] and the n+1th data voltage VDAT[n+1] of each of the first channel CH1 and the third channel CH3, the first channel CH1 and the third channel CH3 may be connected to the common line CML through the first common switch SCM1 and the third common switch SCM3, respectively. Therefore, the first channel CH1 and the third channel CH3 may share charges through the common line CML.

[0092] refer to Fig. 9 and Fig.11 , the n+1th data voltage VDAT[n+1] may be output from the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm (step S160). The first to mth data switches SD1, SD2, SD3, SD4, ..., SDm-1, and SDm may be turned on, and the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm may be connected to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm, respectively. Therefore, the n+1th data voltage VDAT[n+1] output from the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm may be transmitted to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm, respectively.

[0093] Fig.12 is a flowchart illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0094] In the description Fig.12 In the embodiment of the method for driving a display device shown in FIG. 1 , the above reference numerals will be omitted. Fig.11 Any repeated detailed description of the processes of the described embodiments of the method for driving a display device is substantially the same as or similar to the processes.

[0095] refer to Fig.10 and Fig.12 In an embodiment of the method for driving a display device, after a channel is connected to a common line CML, when a common voltage VCOM is between an nth data voltage VDAT[n] and an n+1th data voltage VDAT[n+1] of the channel (step S150), and before the n+1th data voltage VDAT[n+1] is output from the first to mth channels CH1, CH2, CH3, CH4, ..., CHm-1, and CHm to the first to mth data lines DL1, DL2, DL3, DL4, ..., DLm-1, and DLm (step S160), the common voltage VCOM may be increased or decreased (step S170). The common voltage VCOM of the common line CML may be increased or decreased by selective operation of the first to third capacitor switches SCP1, SCP2, and SCP3.

[0096] According to an embodiment, when the common voltage VCOM is less than the minimum reference voltage, the common voltage VCOM may be increased by controlling the first to third capacitor switches SCP1 , SCP2 , and SCP3 .

[0097] According to an embodiment, when the common voltage VCOM is greater than the maximum reference voltage, the common voltage VCOM may be reduced by controlling the first to third capacitor switches SCP1 , SCP2 , and SCP3 .

[0098] Fig.13 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure.

[0099] refer to Fig.13 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may correspond to Figure 1 The electronic device 1000 may further include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc., or capable of communicating with other systems.

[0100] The processor 1010 may perform a specific calculation or task. According to an embodiment, the processor 1010 may be a microprocessor or a central processing unit (CPU), etc. The processor 1010 may be connected to other components through an address bus, a control bus, or a data bus, etc. According to an embodiment, the processor 1010 may also be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. According to an embodiment, the processor 1010 may provide the first image data ( Figure 1 IMD1) and control signal ( Figure 1 CNT in ).

[0101] The memory device 1020 may store data required for the operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include: a non-volatile memory device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM); and / or a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM.

[0102] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), or a CD-ROM, etc. The I / O device 1040 may include: an input device such as a keyboard, a keypad, a touch pad, a touch screen, or a mouse; and an output device such as a speaker or a printer. The power supply 1050 can provide the power required for the operation of the electronic device 1000. The display device 1060 can be connected to other components through a bus or other communication links.

[0103] In the data driver included in the display device 1060 according to an embodiment, the voltage sensor may sense the common voltage of the common line, and the channels may share charges through the common line, so that the data voltages of the channels may be precharged and power consumption of the data driver may be reduced.

[0104] The display device according to the embodiment may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart pad, a portable media player (PMP), a personal digital assistant (PDA), an MP3 player, or the like.

[0105] The utility model should not be interpreted as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the utility model to those skilled in the art.

[0106] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: A display panel including a plurality of pixels and a plurality of data lines connected to the plurality of pixels; as well as a data driver for providing a plurality of data voltages to the plurality of data lines respectively; Wherein, the data driver comprises: a plurality of channels, wherein each of the plurality of channels outputs an nth data voltage in an nth horizontal period and outputs an n+1th data voltage in an n+1th horizontal period, wherein n is a natural number other than zero; Public lines; a plurality of data switches, selectively connecting the plurality of channels to the plurality of data lines respectively; a plurality of common switches, wherein each of the plurality of common switches selectively connects a corresponding one of the plurality of channels to the common line; and A voltage sensor senses a common voltage of the common line.

2. The display device according to claim 1, wherein: The data driver further comprises: A voltage comparator compares the common voltage with the nth data voltage and the (n+1)th data voltage.

3. The display device according to claim 2, wherein: When the common voltage is between the nth data voltage of a channel among the plurality of channels and the (n+1)th data voltage of the channel, the channel is connected to the common line through a common switch corresponding to the channel among the plurality of common switches.

4. The display device according to claim 1, wherein: The data driver further comprises: A capacitor is connected between the common line and ground.

5. The display device according to claim 1, wherein: The data driver further comprises: a plurality of capacitors connected to ground; and A plurality of capacitor switches, wherein each of the plurality of capacitor switches selectively connects a corresponding one of the plurality of capacitors to the common line.

6. The display device according to claim 5, wherein: The common voltage is increased or decreased by selective operation of the plurality of capacitor switches.

7. The display device according to claim 1, wherein: When the common voltage is less than a minimum reference voltage, the common voltage is increased.

8. The display device according to claim 1, wherein: When the common voltage is greater than a maximum reference voltage, the common voltage is reduced.

9. The display device according to any one of claims 1 to 8, wherein: Each of the plurality of data lines extends in a first direction, and The common line extends in a second direction intersecting the first direction.

10. A data driver, providing a plurality of data voltages to a plurality of data lines respectively, the data driver comprising: a plurality of channels, wherein each of the plurality of channels outputs an nth data voltage in an nth horizontal period and outputs an n+1th data voltage in an n+1th horizontal period, wherein n is a natural number other than zero; Public lines; a plurality of data switches, selectively connecting the plurality of channels to the plurality of data lines respectively; a plurality of common switches, wherein each of the plurality of common switches selectively connects a corresponding one of the plurality of channels to the common line; and A voltage sensor senses a common voltage of the common line.

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