Receiving card for LED display screen

Abstract

The utility model discloses a receiving card for an LED (light-emitting diode) display screen, which is characterized in that a core board switching interface module is arranged in the receiving card and is respectively and electrically connected with a power supply module and an Ethernet signal receiving and transmitting module, so that power can be transmitted to the Ethernet signal receiving and transmitting module through the core board switching interface module; external video signals can be transmitted to the Ethernet signal receiving and transmitting module, and the original external video signals are converted into digital signals used in the FPGA main control module through the Ethernet signal receiving and transmitting module; and the core board adapter module is also electrically connected with the FPGA main control module, so that a signal processed by the FPGA main control module can be transmitted back to form a complete signal loop, and the functions of the receiving board are expanded. The FPGA main control module adopts an FPGA chip circuit with the chip model of EG4S20BG256, a large number of logic resources, a DSP block and a built-in memory are configured, complex calculation and signal processing tasks can be achieved, the receiving card does not need to be additionally provided with a storage module, a configuration circuit and the like, the integration degree of the receiving card is higher, and the receiving card is convenient to use. The product design difficulty and the internal space of the control system occupied by the receiving card are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of LED display control, in particular to a receiving card for an LED display screen. Background Art

[0002] LED display is a device used to display various information such as text, images, videos, and video signals. It is increasingly widely used due to its high brightness, long life, and wide viewing angle. The control system of LED display usually includes a sending card, a receiving card, and a power module for powering the sending card and the receiving card.

[0003] At present, the existing receiving card for LED display screen is usually composed of power module, single-chip microcomputer module, Ethernet signal transceiver module, FPGA main control module, storage module, LED output module, etc.; the receiving card receives the display information from the sending card through the Ethernet signal transceiver module, and then receives the signal from the Ethernet signal transceiver module through the FPGA main control module, and processes it according to the preset logic; the storage module is mainly used to store the information of the display content, such as images, video data, etc., the single-chip microcomputer module is responsible for receiving instructions from users or other devices, and then passing them to the FPGA main control module for execution; finally, the signal processed by the FPGA main control module will be passed to the LED output module, so that the image or video content can be displayed on the display screen. However, the above method requires the additional setting of single-chip microcomputer module, storage module and LED output module, which makes the circuit structure of the receiving card complicated, increases the difficulty of product design, and occupies more internal space of the control system and is not conducive to saving production costs.

[0004] Therefore, how to overcome the above-mentioned defects has become an important issue to be solved urgently by those skilled in the art. Utility Model Content

[0005] The utility model overcomes the shortcomings of the above-mentioned technology and provides a receiving card for an LED display screen.

[0006] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0007] A receiving card for an LED display screen comprises a receiving card, wherein the receiving card comprises: a power module, an FPGA main control module, an Ethernet signal transceiver module, and a core board transfer interface module for receiving an external video signal and forwarding it to the Ethernet signal transceiver module, wherein the power module supplies power to the Ethernet signal transceiver module via the core board transfer interface module, the FPGA main control module is electrically connected to the core board transfer interface module, the Ethernet signal transceiver module, and the power module respectively, and the core board transfer interface module is electrically connected to the power module and the Ethernet signal transceiver module respectively; the core board transfer interface module is provided with a plurality of LED light screen data transmission pins, the FPGA main control module outputs LED light screen data via the LED light screen data transmission pins on the core board transfer interface module, and the FPGA main control module is an FPGA chip circuit using a chip model of EG4S20BG256.

[0008] Preferably, the power supply module includes: a first power supply circuit connected to the external power supply output end for outputting a first level voltage, a second power supply circuit connected to the external power supply output end for outputting a second level voltage, and an indicator light circuit for displaying the power supply status; the first power supply circuit and the second power supply circuit both include: a synchronous step-down DC-DC regulator with model SY8089A1AAC and its peripheral circuits; the indicator light circuit is provided with a first indicator light circuit for indicating the working status of the FPGA main control module and a second indicator light circuit for indicating the working status of the first power supply circuit, the first indicator light circuit includes a first indicator light and a first resistor R40 connected in series between the ground end and the FPGA main control module, and the second indicator light circuit includes a second indicator light and a second resistor R39 connected in series between the ground end and the voltage output end of the first power supply circuit.

[0009] Preferably, the FPGA chip circuit includes: four groups of BANKs, a CONF IG pin integrated module, a power pin integrated module, a flash memory circuit, a JTAG interface circuit, a first crystal oscillator circuit, and a first filter circuit. The four groups of BANKs are BANK0, BANK1, BANK2, and BANK3, respectively. The BANK0, BANK1, BANK2, and BANK3 are all electrically connected to the core board transfer interface module. The BANK2 in the FPGA chip circuit is provided with a first control end connected to the first indicator light circuit; the CONF IG pin integrated module is electrically connected to the flash memory circuit and the JTAG interface circuit, respectively, the power pin integrated module is electrically connected to the first filter circuit, and the BANK3 in the FPGA chip circuit is electrically connected to the first crystal oscillator circuit.

[0010] Preferably, the flash memory circuit includes: a flash memory chip of model W25Q64S IG and its peripheral circuits electrically connected to the CONF IG pin integrated module, the first crystal oscillator circuit adopts a 25M active crystal oscillator, the first filter circuit includes: a first filter sub-circuit electrically connected to the first power supply circuit, and a second filter sub-circuit electrically connected to the second power supply circuit, the first filter sub-circuit includes a plurality of capacitors connected in parallel between the first-level voltage output terminal and the ground terminal, and the second filter sub-circuit includes a plurality of capacitors connected in parallel between the second-level voltage output terminal and the ground terminal.

[0011] Preferably, the Ethernet signal transceiver module includes two groups of Ethernet signal transceiver circuits, namely a first Ethernet signal transceiver circuit and a second Ethernet signal transceiver circuit. The first Ethernet signal transceiver circuit includes: a first PHY chip circuit with a chip model of YT8521 SC, a first network transformer with a model of H5120NL connected to the first PHY chip circuit, the first PHY chip circuit is electrically connected to the FPGA chip circuit, and the first network transformer is electrically connected to the core board interface module; the second Ethernet signal transceiver circuit includes: a second PHY chip circuit with a chip model of YT8521 SC, a second network transformer with a model of HNL connected to the second PHY chip circuit, the second PHY chip circuit is electrically connected to the FPGA chip circuit, and the second network transformer is electrically connected to the core board interface module.

[0012] Preferably, the first Ethernet signal transceiver circuit also includes: a second crystal oscillator circuit, a second filter circuit, the second Ethernet signal transceiver circuit also includes: a third crystal oscillator circuit, a third filter circuit, the second crystal oscillator circuit and the third crystal oscillator circuit both use a crystal oscillator of model XRCGB25M000F31 M00R0, the PHY chips of the first PHY chip circuit and the second PHY chip circuit are provided with a DVDD33 power pin, an AVDD33 power pin, a DVDD_RGMII power pin, a DVDDL power pin, and an AVDDL power pin, and the second filter circuit and the third filter circuit both include: a third filter sub-circuit for outputting DVDD33 power, a fourth filter sub-circuit for outputting AVDD33 power, a fifth filter sub-circuit for outputting DVDD_RGMII power, a sixth filter sub-circuit for outputting DVDDL power, and a seventh filter sub-circuit 3145 for outputting AVDDL power.

[0013] Preferably, the core board transfer interface module includes: a first board-to-board connector and a second board-to-board connector, the first board-to-board connector is provided with a power supply voltage input terminal connected to the power supply module, the first board-to-board connector and the second board-to-board connector are both provided with a plurality of LED light screen data transmission pins, and the second board-to-board connector is also provided with a plurality of network signal pins electrically connected to the Ethernet signal transceiver module; the external video signal is transmitted to the Ethernet signal transceiver module through the plurality of network signal pins, and is converted into a digital signal used inside the FPGA main control module by the Ethernet signal transceiver module, and then the processed external video signal is transmitted back to the core board transfer interface module through the FPGA main control module.

[0014] Compared with the prior art, the beneficial effects of the utility model are:

[0015] 1. In this case, a core board transfer interface module is set inside the receiving card, and is electrically connected to the power module and the Ethernet signal transceiver module respectively. On the one hand, power can be supplied to the Ethernet signal transceiver module through the core board transfer interface module, and on the other hand, the external video signal can be transmitted to the Ethernet signal transceiver module, and the original external video signal is converted into a digital signal used inside the FPGA main control module through the Ethernet signal transceiver module. In addition, the core board transfer interface module is also electrically connected to the FPGA main control module to facilitate the transmission of the signal processed by the FPGA main control module to form a complete signal loop, so as to expand the function of the receiving board of this case; and the FPGA main control module of this case adopts an FPGA chip circuit with a chip model of EG4S20BG256, which is equipped with a large number of logic resources, DSP blocks and built-in memory, and can realize complex calculation and signal processing tasks. The receiving card using the FPGA main control module does not need to set up additional storage modules and configuration circuits and single-chip circuits, so that the receiving card is more integrated, so as to simplify the circuit structure of the receiving card, reduce the difficulty of product design and reduce the internal space occupied by the receiving card in the control system, which is conducive to saving production costs. In addition, on this basis, the present application is provided with a core board to interface module, which forms a loop with the FPGA main control module and is provided with an LED light screen data transmission pin, so that the core board to interface module has an LED output function, thereby eliminating the need to set up an additional LED output module, further simplifying the design of the entire receiving card, reducing the number of modules, reducing the complexity of the system, and also improving the stability and reliability of the system, thereby improving the competitiveness of the product.

[0016] 2. This case achieves a high degree of integration by integrating key components such as CONFI G pin module, power pin module, flash memory circuit, JTAG interface circuit, crystal oscillator circuit and filter circuit, which not only simplifies the circuit structure, but also improves the stability and reliability of the overall circuit. In addition, the design of the four groups of BANK in the FPGA chip circuit, namely BANK0, BANK1, BANK2, and BANK3, makes the circuit more scalable and flexible, so that the BANK can be electrically connected to the core board transfer interface module, and it is convenient to interact with other functional modules or external devices for data, and can meet various complex application requirements. The connection between the first control end of the BANK2 and the power module is set so that the FPGA chip circuit can directly control the on and off state of the indicator light. The setting of the connection between the CONFIG pin integrated module and the flash memory circuit and the JTAG interface circuit makes the configuration and debugging of the FPGA chip circuit easier, so that users can program and debug the FPGA through the JTAG interface, and the flash memory circuit provides reliable configuration data storage, without the need to set up an additional JTAG interface and storage module, and the receiving card structure is more compact. The first crystal oscillator circuit is set to provide a stable clock signal for the FPGA chip to ensure the normal operation of the chip. The first filter circuit is set to effectively filter out noise and interference in the power supply and signal, further improving the stability and reliability of the FPGA chip circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural diagram of the receiving card in this case.

[0018] Figure 2 This is the circuit diagram of the power module in this case.

[0019] Figure 3 This is the circuit diagram of the four BANKs in the FPGA master control module of this case.

[0020] Figure 4 This is the circuit diagram after removing four groups of BANKs from the FPGA main control module in this case.

[0021] Figure 5 It is a circuit diagram of the first Ethernet signal transceiver circuit in this case.

[0022] Figure 6 It is a circuit diagram of the second Ethernet signal transceiver circuit in this case.

[0023] Figure 7 This is the circuit diagram of the core board to interface module in this case. DETAILED DESCRIPTION

[0024] The following examples further illustrate the features of the present invention and other related features to facilitate understanding by those skilled in the art:

[0025] like Figure 1 As shown, a receiving card for an LED display screen includes a receiving card 100, and the receiving card 100 includes: a power module 1, an FPGA main control module 2, an Ethernet signal transceiver module 3, and a core board transfer interface module 4 for receiving an external video signal and forwarding it to the Ethernet signal transceiver module 3, the power module 1 supplies power to the Ethernet signal transceiver module 3 through the core board transfer interface module 4, the FPGA main control module 2 is electrically connected to the core board transfer interface module 4, the Ethernet signal transceiver module 3, and the power module 1, respectively, and the core board transfer interface module 4 is electrically connected to the power module 1 and the Ethernet signal transceiver module 3, respectively; wherein, the core board transfer interface module 4 is provided with a plurality of LED light screen data transmission pins, the FPGA main control module 2 outputs the LED light screen data through the LED light screen data transmission pins on the core board transfer interface module 4, and the FPGA main control module 2 is an FPGA chip circuit using a chip model of EG4S20BG256. Specifically, the plurality of LED light screen data output terminals are as follows: Figure 7 The R1, G1, B1, R2, G2, B2, OE_R, OE_G, OE_B, LATD and other pins in the board-to-board connector. Among them, the model EG4S20BG256 is an FPGA master control chip with the characteristics of low power consumption, large capacity, integration, support for multiple communication protocols, and strong programmability.

[0026] As described above, in this case, a core board transfer interface module 4 is set inside the receiving card 100, and is electrically connected to the power supply module 1 and the Ethernet signal transceiver module 3 respectively. On the one hand, power can be transmitted to the Ethernet signal transceiver module 3 through the core board transfer interface module 4, and on the other hand, the external video signal can be transmitted to the Ethernet signal transceiver module 3, and the original external video signal is converted into a digital signal used inside the FPGA main control module 2 through the Ethernet signal transceiver module 3. In addition, the core board transfer interface module 4 is also electrically connected to the FPGA main control module 2 so as to transmit the signal processed by the FPGA main control module 2 back, forming a Into a complete signal loop, so that the function of the receiving board of this case can be expanded; and the FPGA main control module 2 of this case adopts an FPGA chip circuit with a chip model of EG4S20BG256, which is equipped with a large number of logic resources, DSP blocks and built-in memory, and can realize complex calculations and signal processing tasks. The receiving card using the FPGA main control module 2 does not need to set up additional storage modules and configuration circuits and single-chip circuits, so that the integration of the receiving card is higher, so as to simplify the circuit structure of the receiving card, reduce the difficulty of product design and reduce the internal space occupied by the receiving card in the control system, which is conducive to saving production costs. In addition, on this basis, this application is equipped with a core board transfer interface module 4, which forms a loop with the FPGA main control module 2 and is provided with an LED light screen data transmission pin, so that the core board transfer interface module 4 has an LED output function, so that there is no need to set up an LED output module, further simplifying the design of the entire receiving card, reducing the number of modules, reducing the complexity of the system, and also improving the stability and reliability of the system, thereby improving the competitiveness of the product.

[0027] like Figure 2 As shown, in a specific implementation, the power supply module 1 includes: a first power supply circuit 11 connected to the output end of an external power supply for outputting a first level voltage, a second power supply circuit 12 connected to the output end of an external power supply for outputting a second level voltage, and an indicator light circuit 13 for displaying a power supply status; the first power supply circuit 11 and the second power supply circuit 12 both include: a synchronous step-down DC-DC regulator of model SY8089A1AAC and its peripheral circuits; the indicator light circuit 13 is provided with a first indicator light circuit 131 for indicating the working status of the FPGA main control module 2, and a second indicator light circuit 132 for indicating the working status of the first power supply circuit 11, the first indicator light circuit 131 includes a first indicator light 1311 and a first resistor R40 connected in series between the ground end and the FPGA main control module 2, and the second indicator light circuit 132 includes a second indicator light 1321 and a second resistor R39 connected in series between the ground end and the voltage output end of the first power supply circuit 11.

[0028] As described above, this case can output different levels of power supply voltage to the components of each module of the receiving card by setting the first power supply circuit 11 and the second power supply circuit 12, such as the first level voltage 3.3V and the second level voltage 1.2V. The setting of the two power supply circuits is a synchronous step-down DC-DC regulator with model SY8089A1AAC. Compared with ordinary regulators, it has higher conversion efficiency and less energy loss, which can improve the energy efficiency of the entire power supply module; and this regulator has a wider input voltage range: so that the power supply module can adapt to different external power supply environments, improving the applicability and flexibility of the receiving card. The setting of the indicator light circuit 13 enables the power supply module to intuitively display the power supply status and the working status of the FPGA main control module 2 and the first power supply circuit 11. The design of the series connection resistor in the indicator light circuit can protect the first indicator light and the second indicator light.

[0029] like Figure 3 and Figure 4 As shown, during the specific implementation, the FPGA chip circuit includes: four groups of BANK, CONF IG pin integrated module 21, power pin integrated module 22, flash memory circuit 23, JTAG interface circuit 24, first crystal oscillator circuit 25, and first filter circuit 26. The four groups of BANK are BANK0, BANK1, BANK2, and BANK3 respectively. The BANK0, BANK1, BANK2, and BANK3 are all electrically connected to the core board transfer interface module 4. The BANK2 in the FPGA chip circuit is provided with a first control terminal T1 connected to the first indicator light circuit 131; the CONF IG pin integrated module 21 is electrically connected to the flash memory circuit 23 and the JTAG interface circuit 24 respectively, the power pin integrated module 22 is electrically connected to the first filter circuit 26, and the BANK3 in the FPGA chip circuit is electrically connected to the first crystal oscillator circuit 25.

[0030] As mentioned above, this case achieves a high degree of integration by integrating key components such as CONF IG pin module, power pin module, flash memory circuit, JTAG interface circuit, crystal oscillator circuit and filter circuit, which not only simplifies the circuit structure, but also improves the stability and reliability of the overall circuit. In addition, the design of the four groups of BANKBANK0, BANK1, BANK2, and BANK3 in the FPGA chip circuit makes the circuit more scalable and flexible, so that the BANK is electrically connected to the core board transfer interface module, which is convenient for data interaction with other functional modules or external devices, and can meet various complex application requirements. The connection between the first control terminal T1 of the BANK2 and the power module is set so that the FPGA chip circuit can directly control the on and off state of the indicator light. The setting of the connection between the CONF IG pin integrated module and the flash memory circuit and the JTAG interface circuit makes the configuration and debugging of the FPGA chip circuit easier, so that users can program and debug the FPGA through the JTAG interface, and the flash memory circuit provides reliable configuration data storage, without the need to set up an additional JTAG interface and storage module, and the receiving card structure is more compact. The first crystal oscillator circuit is set to provide a stable clock signal for the FPGA chip to ensure the normal operation of the chip. The first filter circuit is set to effectively filter out noise and interference in the power supply and signal, further improving the stability and reliability of the FPGA chip circuit.

[0031] like Figure 4 As shown, in a specific implementation, the flash memory circuit includes: a flash memory chip U6 of model W25Q64S IG electrically connected to the CONF IG pin integrated module 21 and its peripheral circuits, the first crystal oscillator circuit 25 adopts a 25M active crystal oscillator, the first filter circuit 26 includes: a first filter sub-circuit 261 electrically connected to the power output end of the first power supply circuit 11, and a second filter sub-circuit 262 electrically connected to the power output end of the second power supply circuit 12, the first filter sub-circuit 261 includes a plurality of capacitors connected in parallel between the first-level voltage output end and the ground end, and the second filter sub-circuit 262 includes a plurality of capacitors connected in parallel between the second-level voltage output end and the ground end.

[0032] As described above, the flash memory circuit adopts the setting of the flash memory chip U6 of W25Q64S IG, which has the advantages of fast erasing, strong durability, and small size, so that the receiving card in this case has a data storage function, and the electrical connection between the flash memory chip U6 and the CONF IG pin integrated module enables the FPGA chip to directly access and control the flash memory chip, realizing efficient data storage and reading. The first crystal oscillator circuit adopts a 25M active crystal oscillator, which provides a stable clock signal for the FPGA chip and ensures the synchronous transmission and processing of data. The first filter circuit includes a first filter subcircuit and a second filter subcircuit electrically connected to the first power supply circuit and the second power supply circuit respectively, which can effectively filter out noise and interference in the power supply and provide a stable power supply environment for the FPGA chip and the flash memory circuit. The multiple capacitors connected in parallel in the filter subcircuit can further improve the filtering effect, reduce the voltage fluctuation, and ensure the stable operation of the circuit.

[0033] like Figure 5 and Figure 6 As shown, in a specific implementation, the Ethernet signal transceiver module 3 includes two groups of Ethernet signal transceiver circuits, namely a first Ethernet signal transceiver circuit 301 and a second Ethernet signal transceiver circuit 302. The first Ethernet signal transceiver circuit 301 includes: a first PHY chip circuit 311 with a chip model of YT8521 SC, and a first network transformer 312 with a model of H5120NL connected to the first PHY chip circuit 311. The first PHY chip circuit 311 is electrically connected to the FPGA chip circuit, and the first network transformer 312 is electrically connected to the core board transfer interface module 4.

[0034] The second Ethernet signal transceiver circuit 302 includes: a second PHY chip circuit 321 with a chip model of YT8521 SC, and a second network transformer 322 with a model of H5120NL connected to the second PHY chip circuit 321, the second PHY chip circuit 321 is electrically connected to the FPGA chip circuit, and the second network transformer 322 is electrically connected to the core board transfer interface module 4.

[0035] The first Ethernet signal transceiver circuit 301 further includes: a second crystal oscillator circuit 313, a second filter circuit 314, and the second Ethernet signal transceiver circuit 302 further includes: a third crystal oscillator circuit 323, a third filter circuit 324, the second crystal oscillator circuit 313 and the third crystal oscillator circuit 323 both use a crystal oscillator of model XRCGB25M000F31 M00R0, the PHY chips of the first PHY chip circuit 311 and the second PHY chip circuit 321 are both provided with a DVDD33 power pin, an AVDD33 power pin, a DVDD_RGMII power pin, a DVDDL power pin, and an AVDDL power pin, and the second filter circuit 314 and the third filter circuit 324 both include: a third filter sub-circuit 3141 for outputting DVDD33 power, a fourth filter sub-circuit 3142 for outputting AVDD33 power, a fifth filter sub-circuit 3143 for outputting DVDD_RGMII power, a sixth filter sub-circuit 3144 for outputting DVDDL power, and a seventh filter sub-circuit 3145 for outputting AVDDL power.

[0036] As mentioned above, the PHY chip circuit with the chip model YT8521 SC ensures the efficient transceiver of Ethernet signals. The setting of the network transformer H5120NL can play the role of isolation, coupling and filtering in Ethernet communication, can effectively reduce the attenuation and interference in the signal transmission process, and improve the signal quality. The Ethernet signal transceiver module also integrates the setting of the crystal oscillator circuit and the filter circuit, providing a stable clock signal and power supply environment for the module. The crystal oscillator with the model XRCGB25M000F3M00R0 is used to further improve the accuracy and stability of the clock signal, and provide a guarantee for the synchronous transmission of data. The filter circuit filters the power supply through multiple filter sub-circuits, effectively removes the noise and interference in the power supply, and provides a pure and stable power supply for the PHY chip. The PHY chip is provided with multiple power pins, and is powered by the corresponding filter sub-circuit, making the power management more flexible and efficient, and because each power pin has a dedicated filter sub-circuit for filtering, the stability and reliability of the power supply are ensured, and the performance of the Ethernet signal transceiver module is further improved.

[0037] like Figure 7As shown, during the specific implementation, the core board transfer interface module 4 includes: a first board-to-board connector JH1 and a second board-to-board connector JH2, the first board-to-board connector JH1 is provided with a power supply voltage input terminal T2 connected to the power supply module 1, the first board-to-board connector JH1 and the second board-to-board connector JH2 are both provided with the first board-to-board connector JH1 and the second board-to-board connector JH2 are both provided with multiple LED light screen data transmission pins, and the second board-to-board connector JH2 is also provided with multiple network signal pins electrically connected to the Ethernet signal transceiver module 3, such as LAN1_D1_N, LAN1_D2_N, LAN1_D1_P, LAN1_D2_P, etc.; the external video signal is transmitted to the Ethernet signal transceiver module 3 through the multiple network signal pins, and is converted into a digital signal used inside the FPGA main control module 2 through the Ethernet signal transceiver module 3, and then the processed external video signal is transmitted back to the core board transfer interface module 4 through the FPGA main control module 2.

[0038] As described above, the first board-to-board connector JH1 of the core board transfer interface module 4 is provided with a setting of a power supply voltage input terminal T2 connected to the power module 1, which realizes a direct power supply connection between the power module and the core board transfer interface module, simplifies the complexity of power distribution and management, and improves the power supply efficiency of the entire system. The first board-to-board connector JH1 and the second board-to-board connector JH2 are both provided with a plurality of LED light screen data transmission pins, so that the LED light screen data can be quickly and accurately transmitted to the external LED display screen by the LED light screen data transmission pins. The second board-to-board connector JH2 is also provided with a plurality of network signal pins electrically connected to the Ethernet signal transceiver module 3, so that the external video signal can be transmitted to the Ethernet signal transceiver module through these pins, so as to transmit the processed video signal to the FPGA main control module 2. Finally, the external video signal processed by the FPGA main control module can be transmitted back to the core board transfer interface module 4, and then output to the LED display screen through the core board transfer interface module.

[0039] As mentioned above, this case protects a receiving card for an LED display screen, and all technical solutions that are identical or similar to this case should be deemed to fall within the protection scope of this case.

Claims

1. A receiving card for an LED display screen, comprising a receiving card (100), characterized in that: The receiving card (100) comprises: a power module (1), an FPGA main control module (2), an Ethernet signal transceiver module (3), and a core board transfer interface module (4) for receiving an external video signal and forwarding it to the Ethernet signal transceiver module (3); the power module (1) supplies power to the Ethernet signal transceiver module (3) via the core board transfer interface module (4); the FPGA main control module (2) is electrically connected to the core board transfer interface module (4), the Ethernet signal transceiver module (3), and the power module (1), respectively; the core board transfer interface module (4) is electrically connected to the power module (1) and the Ethernet signal transceiver module (3), respectively; the core board transfer interface module (4) is provided with a plurality of LED light screen data transmission pins; the FPGA main control module (2) outputs LED light screen data via the LED light screen data transmission pins on the core board transfer interface module (4); the FPGA main control module (2) is an FPGA chip circuit using a chip model of EG4S20BG256.

2. A receiving card for an LED display screen according to claim 1, characterized in that: The power module (1) comprises: a first power supply circuit (11) connected to an external power supply output end for outputting a first level voltage, a second power supply circuit (12) connected to an external power supply output end for outputting a second level voltage, and an indicator light circuit (13) for displaying a power supply status; the first power supply circuit (11) and the second power supply circuit (12) both comprise: a synchronous step-down DC-DC regulator of model SY8089A1AAC and its peripheral circuits; the indicator light circuit (13) is provided with a first indicator light circuit (131) for indicating the working status of the FPGA main control module (2) and a second indicator light circuit (132) for indicating the working status of the first power supply circuit (11); the first indicator light circuit (131) comprises a first indicator light (1311) and a first resistor R40 connected in series between a ground terminal and the FPGA main control module (2); and the second indicator light circuit (132) comprises a second indicator light (1321) and a second resistor R39 connected in series between a ground terminal and a voltage output terminal of the first power supply circuit (11).

3. A receiving card for an LED display screen according to claim 2, characterized in that: The FPGA chip circuit comprises: four groups of BANKs, a CONFIG pin integrated module (21), a power pin integrated module (22), a flash memory circuit (23), a JTAG interface circuit (24), a first crystal oscillator circuit (25), and a first filter circuit (26); the four groups of BANKs are BANK0, BANK1, BANK2, and BANK3 respectively; BANK0, BANK1, BANK2, and BANK3 are all electrically connected to a core board transfer interface module (4); BANK2 in the FPGA chip circuit is provided with a first control terminal (T1) connected to a first indicator light circuit (131); the CONFIG pin integrated module (21) is electrically connected to the flash memory circuit (23) and the JTAG interface circuit (24) respectively; the power pin integrated module (22) is electrically connected to the first filter circuit (26); and BANK3 in the FPGA chip circuit is electrically connected to the first crystal oscillator circuit (25).

4. A receiving card for an LED display screen according to claim 3, characterized in that: The flash memory circuit comprises: a flash memory chip U6 of model W25Q64SIG electrically connected to a CONFIG pin integrated module (21) and its peripheral circuits; the first crystal oscillator circuit (25) adopts a 25M active crystal oscillator; the first filter circuit (26) comprises: a first filter subcircuit (261) electrically connected to a first power supply circuit (11) and a second filter subcircuit (262) electrically connected to a second power supply circuit (12); the first filter subcircuit (261) comprises a plurality of capacitors connected in parallel between a first voltage output terminal and a ground terminal; the second filter subcircuit (262) comprises a plurality of capacitors connected in parallel between a second voltage output terminal and a ground terminal.

5. A receiving card for an LED display screen according to claim 1, characterized in that: The Ethernet signal transceiver module (3) comprises two groups of Ethernet signal transceiver circuits, namely a first Ethernet signal transceiver circuit (301) and a second Ethernet signal transceiver circuit (302). The first Ethernet signal transceiver circuit (301) comprises: a first PHY chip circuit (311) with a chip model of YT8521 SC, a first network transformer (312) with a model of H5120NL connected to the first PHY chip circuit (311), the first PHY chip circuit (311) is electrically connected to the FPGA chip circuit, and the first network transformer (312) is electrically connected to the core board transfer interface module (4); the second Ethernet signal transceiver circuit (302) comprises: a second PHY chip circuit (321) with a chip model of YT8521 SC, a second network transformer (322) with a model of H5120NL connected to the second PHY chip circuit (321), the second PHY chip circuit (321) is electrically connected to the FPGA chip circuit, and the second network transformer (322) is electrically connected to the core board transfer interface module (4).

6. A receiving card for an LED display screen according to claim 5, characterized in that: The first Ethernet signal transceiver circuit (301) further includes: a second crystal oscillator circuit (313) and a second filter circuit (314); the second Ethernet signal transceiver circuit (302) further includes: a third crystal oscillator circuit (323) and a third filter circuit (324); the second crystal oscillator circuit (313) and the third crystal oscillator circuit (323) both use a crystal oscillator of model XRCGB25M000F31 The PHY chips of the first PHY chip circuit (311) and the second PHY chip circuit (321) are provided with a DVDD33 power pin, an AVDD33 power pin, a DVDD_RGMII power pin, a DVDDL power pin, and an AVDDL power pin. The second filter circuit (314) and the third filter circuit (324) both include: a third filter subcircuit (3141) for outputting DVDD33 power, a fourth filter subcircuit (3142) for outputting AVDD33 power, a fifth filter subcircuit (3143) for outputting DVDD_RGMII power, a sixth filter subcircuit (3144) for outputting DVDDL power, and a seventh filter subcircuit (3145) for outputting AVDDL power.

7. A receiving card for an LED display screen according to claim 1, characterized in that: The core board transfer interface module (4) comprises: a first board-to-board connector (JH1) and a second board-to-board connector (42); the first board-to-board connector (JH1) is provided with a power supply voltage input terminal (T2) connected to the power supply module (1); the first board-to-board connector (JH1) and the second board-to-board connector (42) are both provided with a plurality of LED light screen data transmission pins; the second board-to-board connector (42) is also provided with a plurality of network signal pins electrically connected to the Ethernet signal transceiver module (3); the external video signal is transmitted to the Ethernet signal transceiver module (3) through the plurality of network signal pins, and is converted into a digital signal used inside the FPGA main control module (2) by the Ethernet signal transceiver module (3); and the processed external video signal is then transmitted back to the core board transfer interface module (4) through the FPGA main control module (2).

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