Multi-chip module packaging structure
By setting a housing cavity on the heat dissipation cover of the multi-chip module package structure and increasing the size of the heat dissipation metal layer, the problem of poor coverage of the heat dissipation metal layer during high-temperature welding is solved, and a more efficient heat dissipation effect is achieved.
Patent Information
- Application Number
- CN202421919210.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-08-09
AI Technical Summary
During high-temperature welding of existing multi-chip module packaging structures, due to the poor coverage of the heat-dissipation metal layer, the heat-dissipation metal layers between the chips are pulled to each other, which cannot meet the heat-dissipation needs.
A multi-chip module packaging structure is designed, by providing a receiving cavity on one side of the heat dissipation cover facing the substrate, it is used to maintain the high-temperature melted heat dissipation metal layer at each chip according to the tension, and increase the size of the heat dissipation metal layer to project it on the outside of the chip, thereby reducing the pulling between the heat dissipation metal layers.
It effectively avoids the pulling of the heat-dissipating metal layers between the multi-chip modules during high-temperature welding, increases the coverage of the heat-dissipating metal layers, and meets the heat-dissipation needs of the packaging structure.
Smart Images
Figure CN222914790U_ABST
Abstract
Description
Technical Field
[0001] The disclosed embodiments belong to the field of semiconductor packaging technology, and specifically relate to a multi-chip module packaging structure. Background Art
[0002] With the development of the market, the chip package size is getting larger and larger, the number of chips is increasing, and the heat dissipation demand is also getting higher and higher. However, the reality is that due to the large package size and the large number of chips, the heat dissipation metal layers between the chips pull each other during high-temperature welding, resulting in poor coverage of the heat dissipation metal layer, which cannot meet the heat dissipation requirements.
[0003] In view of the above problems, it is necessary to propose a multi-chip module packaging structure that is reasonably designed and can effectively improve the above problems. Utility Model Content
[0004] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a multi-chip module packaging structure.
[0005] The present disclosure provides a multi-chip module packaging structure, including:
[0006] substrate;
[0007] A plurality of chips are arranged on the substrate;
[0008] A heat dissipation metal layer is arranged on a side of the chip facing away from the substrate, and an orthographic projection of the heat dissipation metal layer on the corresponding chip falls on the outside of the chip;
[0009] A heat dissipation cover, which is disposed on a side of the heat dissipation metal layer away from the substrate;
[0010] The gold-plated layer is sandwiched between the heat dissipation cover and the heat dissipation metal layer; wherein,
[0011] The heat dissipation cover is provided with a receiving cavity on one side facing the substrate and corresponding to the position of each chip, and the receiving cavity is used to maintain the heat dissipation metal layer melted at high temperature at each chip according to tension.
[0012] Optionally, the accommodating cavity is a groove that is recessed toward a side of the heat dissipation cover away from the substrate.
[0013] Optionally, the depth of the groove ranges from 10um to 50um, and the width of the groove ranges from 10um to 200um.
[0014] Optionally, the heat dissipation cover is provided with a plurality of the accommodating cavities distributed in a matrix.
[0015] Optionally, the gold plating layer is disposed on the heat dissipation cover, and the gold plating layer corresponds to each of the chips and the regions between adjacent two chips.
[0016] Optionally, the outer edge region of the gold plating layer extends beyond the edge region of the corresponding chip by 0.1 mm to 2 mm.
[0017] Optionally, a preset spacing is provided between adjacent two of the heat dissipation metal layers.
[0018] Optionally, the range of the preset spacing is 0.1 mm to 2.0 mm.
[0019] Optionally, the outer edge region of the heat dissipation metal layer extends beyond the edge region of the corresponding chip by 0.1 mm to 2.0 mm.
[0020] The embodiment of the present disclosure provides a multi-chip module packaging structure. By providing accommodation cavities on the side of the heat dissipation cover facing the substrate and corresponding to the positions of each chip, the accommodation cavities are used to maintain the high-temperature molten heat dissipation metal layers at each chip according to the tension, which can avoid the mutual pulling between the molten heat dissipation metal layers during high-temperature welding of the multi-chip module and increase the coverage rate of the heat dissipation metal layers; the orthographic projection of the heat dissipation metal layer on the corresponding chip falls outside the chip. By increasing the size of the heat dissipation metal layer, when the multi-chip module is subjected to high-temperature welding, due to the sufficient amount of the heat dissipation metal layer, the void abnormality caused by the mutual pulling between the molten heat dissipation metal layers between the chips is weakened, and the coverage rate of the heat dissipation metal layer is further increased to meet the heat dissipation requirements of the packaging structure. Description of the Drawings
[0021] Figure 1 is a schematic structural diagram of a multi-chip module packaging structure in an embodiment of the present disclosure;
[0022] Figure 2 is a schematic plan view of the accommodation cavity on the heat dissipation cover in another embodiment of the present disclosure;
[0023] Figure 3 is a schematic diagram of the positional relationship between the gold plating layer and each chip in another embodiment of the present disclosure. Detailed Embodiments
[0024] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the following further describes the embodiments of the present disclosure in detail with reference to the drawings and specific embodiments.
[0025] Such as Figure 1 and Figure 2As shown in the figure, an embodiment of the present disclosure provides a multi-chip module packaging structure 100, which includes a substrate 110, multiple chips 120, a heat dissipation metal layer 130, a heat dissipation cover 140, and a gold plating layer 150.
[0026] Multiple chips 120 are arranged on the substrate 110. Specifically, multiple chips 120 are laid flat on the substrate 110 to form a multi-chip module. Among them, the number and type of chips 120 are not specifically limited in this embodiment and can be selected according to actual needs.
[0027] The heat dissipation metal layer 130 is arranged on the side of the chips 120 facing away from the substrate 110, and a heat dissipation metal layer 130 is correspondingly arranged at each chip 120.
[0028] As Figure 1 shown, the orthographic projection of the heat dissipation metal layer 130 on the corresponding chip 120 falls outside the chip 120. That is to say, the size of the heat dissipation metal layer 130 is larger than that of the corresponding chip 120, increasing the coverage area of the heat dissipation metal layer 130.
[0029] It should be noted that in this embodiment, the heat dissipation metal layer 130 is a thermal interface material layer, that is to say, the heat dissipation metal layer 130 uses a thermal interface material. The thermal interface material has high thermal conductivity and increases the heat dissipation capacity. Further preferably, in this embodiment, the heat dissipation metal layer 130 is described by taking an indium sheet as an example. The indium sheet is a thermal interface material with high thermal conductivity, which can increase the heat dissipation of the packaging structure.
[0030] The heat dissipation cover 140 is covered on the side of the heat dissipation metal layer 130 facing away from the substrate 110, playing a role in dissipating heat for the entire packaging structure.
[0031] The gold plating layer 150 is sandwiched between the heat dissipation cover 140 and the heat dissipation metal layer 130; among them, as Figure 2 shown, the heat dissipation cover 140 is provided with accommodation cavities 160 on the side facing the substrate and corresponding to the positions of each chip 120. The accommodation cavities 160 are used to maintain the high-temperature molten heat dissipation metal layer 130 at each chip 120 according to the tension. Among them, the gold plating layer 150 is also arranged in the accommodation cavities 160.
[0032] Specifically, after the multi-chip module packaging structure 100 is mounted, it is placed in a high-temperature reflow furnace (the reflow temperature is 180 °C to 240 °C, and the vacuum pressure is 3 kPa to 10 kPa). In the high-temperature case, the heat dissipation metal layer 130 melts into liquid metal. Due to the existence of the accommodation cavities 160, the heat dissipation metal layer 130 melted into liquid is located at the accommodation cavities 160 according to the tension, and then the heat dissipation metal layer 130 melted into liquid is maintained at each chip 120, reducing the disorderly flow of the heat dissipation metal layer 130 in liquid state and reducing the mutual pulling between the heat dissipation metal layers 130 in liquid state.
[0033] In the multi-chip module packaging structure according to the embodiments of the present disclosure, accommodation cavities are provided on one side of the heat dissipation cover facing the substrate and corresponding to the positions of each chip. The accommodation cavities are used to maintain the high-temperature molten heat dissipation metal layer at each chip according to the tension, which can avoid the mutual pulling between the molten heat dissipation metal layers during high-temperature welding of the multi-chip module and increase the coverage rate of the heat dissipation metal layer; the orthographic projection of the heat dissipation metal layer on the corresponding chip falls outside the chip. By increasing the size of the heat dissipation metal layer, when the multi-chip module is subjected to high-temperature welding, due to the sufficient amount of the heat dissipation metal layer, the void abnormality caused by the mutual pulling between the molten heat dissipation metal layers between the chips is weakened, and the coverage rate of the heat dissipation metal layer is further increased to meet the heat dissipation requirements of the packaging structure.
[0034] Exemplarily, as Figure 2 shown, the accommodation cavity 160 is a groove recessed toward the side of the heat dissipation cover 140 away from the substrate 110. That is to say, the molten heat dissipation metal layer 130 can fill the groove and maintain the molten heat dissipation metal layer 130 at each chip 120 according to the tension.
[0035] It should be noted that the structure of the accommodation cavity 160 is not limited to the groove, and other accommodation structures are also possible. The present embodiment does not make specific limitations and can be selected according to actual needs.
[0036] Exemplarily, in the present embodiment, the depth range of the groove is 10um to 50um, and the width range of the groove is 10um to 200um. The present embodiment does not make specific limitations on the size range of the groove and can be selected according to actual needs.
[0037] Specifically, in the present embodiment, the cross-sectional shape of the groove is square. Of course, the cross-sectional shape of the groove is not specifically limited and can be selected according to actual needs. For example, the cross-sectional shape of the groove can also be rectangular, circular or triangular, etc.
[0038] Exemplarily, as Figure 2 shown, the heat dissipation cover 140 is provided with a plurality of accommodation cavities 160 distributed in a matrix. That is to say, a plurality of square grooves are distributed in a matrix on one side of the heat dissipation cover 140 facing the substrate 110. It should be noted that the number of the accommodation cavities 160 is not specifically limited and can be selected according to actual needs.
[0039] Exemplarily, as Figure 3 shown, the gold plating layer 150 is provided on the heat dissipation cover, and the gold plating layer 150 corresponds to the positions of each chip 120 and the regions between two adjacent chips 120.
[0040] Specifically, in the prior art, the gold plating layer 150 is only provided at the position corresponding to the chip 120. As Figure 3As shown, in this embodiment, the coverage area of the gold plating layer 150 is increased, and the gold plating layer 150 is provided at the position corresponding to the chip 120 and in the area between two adjacent chips.
[0041] In this embodiment, a gold plating layer is provided at the position corresponding to each chip and in the area between two adjacent chips, and the area of the gold plating layer is increased to further improve the heat dissipation of the entire packaging structure and meet the heat dissipation requirements of the packaging structure.
[0042] Exemplarily, as Figure 3 shown, the outer edge area of the gold plating layer 150 extends beyond the edge area of the corresponding chip 120 by 0.1 mm to 2 mm. That is to say, the area of the gold plating layer 150 should cover the area of the corresponding chip 120, so as to better dissipate heat from the chip 120 and thus improve the heat dissipation performance of the packaging structure.
[0043] It should be noted that the distance by which the outer edge area of the gold plating layer 150 extends beyond the edge area of the corresponding chip 120 is not specifically limited and can be selected according to actual needs.
[0044] Exemplarily, as Figure 1 shown, there is a preset spacing between two adjacent heat dissipation metal layers 130. Further, the range of the preset spacing is 0.1 mm to 2.0 mm, which can further increase the coverage rate of the heat dissipation metal layer 130. Among them, the size of the preset spacing is not specifically limited in this embodiment and can be selected according to actual needs.
[0045] Exemplarily, as Figure 1 shown, the outer edge area of the heat dissipation metal layer 130 extends beyond the edge area of the corresponding chip 120 by 0.1 mm to 2.0 mm. That is to say, the chip 120 should be located within the corresponding heat dissipation metal layer 130 to further improve the heat dissipation performance of the chip 120.
[0046] It should be noted that the distance by which the outer edge area of the heat dissipation metal layer 130 extends beyond the edge area of the corresponding chip 120 is not specifically limited and can be selected according to actual needs.
[0047] In this embodiment, by increasing the coverage area of the heat dissipation metal layer, when the packaging structure is mounted and then undergoes high-temperature reflow, the heat dissipation metal layer melts into a liquid metal. Due to the large coverage area of the heat dissipation metal layer, there is enough molten heat dissipation metal layer, thereby weakening the void abnormality caused by the mutual pulling of the heat dissipation metal layers between chips, improving the void problem of the heat dissipation metal layer, increasing the coverage rate of the heat dissipation metal layer, and meeting the heat dissipation requirements of the packaging structure.
[0048] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the embodiments of the present disclosure.
Claims
1. A multi-chip module packaging structure, characterized in that: include: substrate; A plurality of chips are arranged on the substrate; A heat dissipation metal layer is arranged on a side of the chip facing away from the substrate, and an orthographic projection of the heat dissipation metal layer on the corresponding chip falls on the outside of the chip; A heat dissipation cover, which is disposed on a side of the heat dissipation metal layer away from the substrate; The gold-plated layer is sandwiched between the heat dissipation cover and the heat dissipation metal layer; wherein, The heat dissipation cover is provided with a receiving cavity on one side facing the substrate and corresponding to the position of each chip, and the receiving cavity is used to maintain the heat dissipation metal layer melted at high temperature at each chip according to tension.
2. The multi-chip module packaging structure according to claim 1, characterized in that: The accommodating cavity is a groove which is recessed toward a side of the heat dissipation cover away from the substrate.
3. The multi-chip module packaging structure according to claim 2, characterized in that: The depth of the groove ranges from 10um to 50um, and the width of the groove ranges from 10um to 200um.
4. The multi-chip module packaging structure according to any one of claims 1 to 3, characterized in that: The heat dissipation cover is provided with a plurality of the accommodating cavities distributed in a matrix.
5. The multi-chip module packaging structure according to any one of claims 1 to 3, characterized in that: The gold-plated layer is arranged on the heat dissipation cover, and the gold-plated layer corresponds to each chip and the area between two adjacent chips.
6. The multi-chip module packaging structure according to claim 5, characterized in that: The outer edge area of the gold-plated layer exceeds the corresponding edge area of the chip by 0.1 mm to 2 mm.
7. The multi-chip module packaging structure according to any one of claims 1 to 3, characterized in that: There is a preset distance between two adjacent heat dissipation metal layers.
8. The multi-chip module packaging structure according to claim 7, characterized in that: The preset spacing ranges from 0.1 mm to 2.0 mm.
9. The multi-chip module packaging structure according to any one of claims 1 to 3, characterized in that: The outer edge region of the heat dissipation metal layer exceeds the edge region of the corresponding chip by 0.1 mm to 2.0 mm.