Top heat dissipation type MOS packaging structure

Abstract

The utility model belongs to the technical field of semiconductor device packaging, and particularly relates to a top heat dissipation type MOS packaging structure, which comprises a frame body, a first base island, a second base island and a third base island which are sequentially arranged side by side, and a fourth base island which is arranged on the opposite side in parallel, the first base island, the second base island and the third base island are respectively connected with a pin area, and the fourth base island is connected with three pin areas; the chip set comprises a first chip, a second chip and a third chip which are arranged on the first base island, the second base island and the third base island respectively, and a fourth chip, a fifth chip and a sixth chip which are arranged on the fourth base island side by side in the length direction of the fourth base island; and the packaging layer coats the frame body, and exposes one side, deviating from the chip group, of the frame body and all the pin areas. According to the utility model, six MOS chips are sealed into one device, the space utilization rate of a PCB (Printed Circuit Board) is improved, the production cost is reduced, and the device can be used for high-power and high-current application scenes.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor device packaging, in particular to a top heat dissipation type MOS packaging structure. Background Art

[0002] In recent years, with the development of high-tech industries such as new energy vehicles and artificial intelligence, semiconductor power MOS chips have been widely used in circuit control, power management, electrical signal conversion, and other fields in circuit systems. MOS chips are integrated circuit chips made of metal (Metal) - oxide (Oxide) - semiconductor (Semiconductor) structure, which has the characteristics of high efficiency, high reliability, low noise and high integration.

[0003] At present, in some high-power and high-current application scenarios, a single MOS chip cannot withstand the current impact, and multiple MOS chips occupy a large PCB (printed circuit board) area, resulting in reduced space utilization and higher costs. Therefore, it is urgent to design a MOS packaging structure to solve the above problems. Utility Model Content

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a top-heat-dissipating MOS packaging structure, which is used to solve the technical problem in the prior art that multiple MOS are used in high-power and high-current application scenarios, resulting in reduced PCB board space utilization and increased costs.

[0005] In order to achieve the above-mentioned purpose and other related purposes, the technical solution of the utility model is as follows:

[0006] A top heat dissipation MOS packaging structure, comprising:

[0007] The frame body includes a first base island, a second base island and a third base island arranged side by side and in sequence, and a fourth base island arranged in parallel on the opposite side, wherein the first base island, the second base island and the third base island are respectively connected to a pin area, and the fourth base island is connected to three pin areas;

[0008] A chipset, comprising a first chip, a second chip and a third chip respectively arranged on the first base island, the second base island and the third base island, and a fourth chip, a fifth chip and a sixth chip arranged side by side along the length direction of the fourth base island;

[0009] The packaging layer is coated on the frame body and exposes a side of the frame body away from the chipset and all the pin areas.

[0010] Optionally, a first pin is provided in the pin area of the first base island, a second pin is provided in the pin area of the second base island, a third pin is provided in the pin area of the third base island, and a fourth pin is provided in each pin area connected to the fourth base island.

[0011] Optionally, a fifth pin is provided between the first base island and the second base island, and a sixth pin is provided between the second base island and the third base island.

[0012] Optionally, a first group of seventh pins is provided between the first pin and the fifth pin, a second group of seventh pins is provided between the second pin and the sixth pin, a third group of seventh pins is provided on the right side of the third pin, and the first group of seventh pins, the second group of seventh pins, and the third group of seventh pins each include two pin portions arranged side by side.

[0013] Optionally, a first group of eighth pins is provided between the fourth pin in the middle of the fourth base island and the fourth pin on the left side, and a second group of eighth pins is provided between the fourth pin in the middle of the fourth base island and the fourth pin on the right side. The first group of eighth pins includes four pin portions arranged side by side, and the second group of eighth pins includes two pin portions arranged side by side.

[0014] Optionally, it further includes a first bonding wire for connecting the first chip, the fifth pin, the second chip, the sixth pin, and the third chip.

[0015] Optionally, it further includes a second bonding wire for connecting between the first chip and the first group of seventh pins, between the second chip and the second group of seventh pins, and between the third chip and the third group of seventh pins respectively.

[0016] Optionally, it further includes a third bonding wire for connecting between the fourth chip and the first group of eighth pins, between the fifth chip and the first group of eighth pins, and between the sixth chip and the second group of eighth pins respectively.

[0017] Optionally, it further includes a fourth bonding wire for connecting between the first base island and the fourth chip, between the second base island and the fifth chip, and between the third base island and the sixth chip respectively.

[0018] Optionally, between the first chip and the first base island, between the second chip and the second base island, between the third chip and the third base island, and between the fourth chip, the fifth chip, and the sixth chip and the fourth base island are all connected by a connecting material.

[0019] As described above, a packaging structure of a top - heat - dissipating MOS of the present utility model has the following beneficial effects:

[0020] By reasonably arranging the first base island, the second base island, the third base island, and the fourth base island on the frame body, as well as the pin areas and chip sets corresponding to each base island, six MOS chips are integrated into one device, greatly reducing the area of the PCB board used, improving the space utilization rate of the PCB, reducing the production cost of the enterprise, improving the efficiency, and being applicable to high-power and high-current application scenarios. Description of the Drawings

[0021] Figure 1 Internal schematic diagram of a top-cooled MOS package structure according to an embodiment of the present invention;

[0022] Figure 2 External schematic of a top-cooled MOS package structure according to an embodiment of the present invention Figure 1 ;

[0023] Figure 3 External schematic of a top-cooled MOS package structure according to an embodiment of the present invention Figure 2 ;

[0024] Figure 4 External side view of a top-cooled MOS package structure according to an embodiment of the present invention.

[0025] Description of the Reference Numerals

[0026] 10 - Frame body;

[0027] 101 - First base island; 102 - Second base island; 103 - Third base island; 104 - Fourth base island;

[0028] 11 - First pin; 12 - Second pin; 13 - Third pin; 14 - Fourth pin; 15 - Fifth pin; 16 - Sixth pin;

[0029] 171 - First group of seventh pins; 171a - First source pin part; 171b - First gate pin part;

[0030] 172 - Second group of seventh pins; 172a - Second source pin part; 172b - Second gate pin part;

[0031] 173 - Third group of seventh pins; 173a - Third source pin part; 173b - Third gate pin part;

[0032] 181 - First group of eighth pins; 181a - Fourth gate pin part; 181b - Fourth source pin part; 181c - Fifth gate pin part; 181d - Fifth source pin part;

[0033] 182 - The eighth pin of the second group; 182a - The sixth gate pin part; 182b - The sixth source pin part;

[0034] 20 - Chipset;

[0035] 21 - The first chip; 22 - The second chip; 23 - The third chip; 24 - The fourth chip; 25 - The fifth chip; 26 - The sixth chip;

[0036] 30 - Encapsulation layer;

[0037] 41 - The first bonding wire; 42 - The second bonding wire; 43 - The third bonding wire; 44 - The fourth bonding wire. Detailed implementation mode

[0038] The following specific embodiments illustrate the implementation mode of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The actual form, quantity, and proportion of each component during actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex. It should be known that the structures, proportions, sizes, etc. shown in the diagrams of this specification are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have technical substantive significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope for the implementation of the present invention. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope within which the present invention can be implemented.

[0040] In order to be able to describe the present invention in detail, a specific description of a top - heat - dissipating MOS packaging structure of the present invention is given next:

[0041] Please refer to Figures 1 to 4As shown in the figure, the utility model provides a packaging structure of a top-cooled MOS, including: a frame body 10, a chip group 20, and a packaging layer 30. Among them, the frame body 10 includes a first base island 101, a second base island 102, and a third base island 103 arranged side by side and in sequence, and a fourth base island 104 arranged in parallel on the opposite side. Each of the first base island 101, the second base island 102, and the third base island 103 is connected to a pin area, and the fourth base island 104 is connected to three pin areas; the chip group 20 includes a first chip 21, a second chip 22, and a third chip 23 respectively arranged on the first base island 101, the second base island 102, and the third base island 103, and a fourth chip 24, a fifth chip 25, and a sixth chip 26 arranged side by side along the length direction of the fourth base island 104; the packaging layer 30 covers the frame body 10, and exposes the side of the frame body 10 facing away from the chip group 20 and all pin areas.

[0042] Specifically, the frame body 10 includes a first base island 101, a second base island 102, and a third base island 103 arranged on one side, and a fourth base island 104 arranged on the opposite side. The first base island 101, the second base island 102, and the third base island 103 are arranged in a row at intervals along the length direction of the frame body 10; the first chip 21 is arranged on the first base island 101, the second chip 22 is arranged on the second island, the third chip 23 is arranged on the third base island 103, and the fourth chip 24, the fifth chip 25, and the sixth chip 26 are arranged side by side and at intervals on the fourth base island 104. Among them, all the chips in the chip group 20 are MOS chips; the packaging layer 30 is used to cover the frame body 10, enclose the chip group 20, and expose the side of the frame body 10 facing away from the chip group 20 (i.e., the top of the frame body 10) and all pin areas. Exemplarily, the packaging layer 30 can be made of epoxy resin.

[0043] This structure has the following effects: 1. High - efficient heat dissipation performance. Since the back of the base island in the frame body 10 is used for top - side heat dissipation, the "top - side heat dissipation" means that the back of the base island in the frame body 10 is located at the top for heat dissipation, and its heat dissipation effect is better, effectively reducing the working temperature of the chip and extending the service life of the device. Compared with the traditional bottom - side heat dissipation method, top - side heat dissipation reduces the distance and obstruction of heat propagation through the PCB (printed circuit board), thereby reducing the heat borne by the PCB and helping to reduce the working temperature of surrounding components, improving the stability and reliability of the overall system. 2. Optimized space utilization. Through the first base island 101, the second base island 102, the third base island 103 arranged side - by - side and the fourth base island 104 arranged in parallel, this packaging structure realizes multi - chip integration while maintaining a high space utilization rate. This layout enables more chips to be accommodated within a limited packaging size, thus increasing the power density and integration degree. Through the layout optimization and connection design of the pin area, it helps to reduce the source parasitic inductance and improve the overall performance of the circuit. Low parasitic inductance helps to reduce voltage spikes and electromagnetic interference during the switching process, improving the efficiency and stability of the circuit.

[0044] In some embodiments, a first pin 11 is provided in the pin area of the first base island 101, a second pin 12 is provided in the pin area of the second base island 102, a third pin 13 is provided in the pin area of the third base island 103, and a fourth pin 14 is provided in each pin area connected to the fourth base island 104. Specifically, the first pin 11 is located at the lower left of the first base island 101, the second pin 12 is located at the lower left of the second base island 102, the third pin 13 is located at the lower left of the third base island 103, and the first pin 11, the second pin 12 and the third pin 13 are connected to each other. The three fourth pins 14 provided on the fourth base island 104 are respectively: the fourth pin 14 located on the left side of the fourth base island 104, the fourth pin 14 located in the middle of the fourth base island 104, and the fourth pin 14 located on the right side of the fourth base island 104. The first pin 11, the second pin 12 and the third pin 13 have the same structure; the three fourth pins 14 have the same structure; the first pin 11 is used for signal connection of the first chip 21, the second pin 12 is used for signal connection of the second chip 22, the third pin 13 is used for signal connection of the third chip 23, and the three fourth pins 14 respectively correspond to signal connections of the fourth chip 24, the fifth chip 25 and the sixth chip 26.

[0045] In the above-described embodiment, a fifth pin 15 is provided between the first base island 101 and the second base island 102, and a sixth pin 16 is provided between the second base island 102 and the third base island 103. Specifically, the fifth pin 15 and the sixth pin 16 have the same structure, and both the fifth pin 15 and the sixth pin 16 are flush with and connected to the first pin 11, the second pin 12, and the third pin 13. The fifth pin 15 serves as a bridge between the first base island 101 and the second base island 102, enhancing the signal connectivity and transmission ability between these two regions, which helps ensure that data and control signals can be exchanged efficiently and accurately between the first chip 21 and the second chip 22; the sixth pin 16 serves as a bridge between the second base island 102 and the third base island 103, enhancing the signal connectivity and transmission ability between these two regions, which helps ensure that data and control signals can be exchanged efficiently and accurately between the second chip 22 and the third chip 23.

[0046] In the above-described embodiment, a first set of seventh pins 171 is provided between the first pin 11 and the fifth pin 15, a second set of seventh pins 172 is provided between the second pin 12 and the sixth pin 16, and a third set of seventh pins 173 is provided on the right side of the third pin 13. The first set of seventh pins 171, the second set of seventh pins 172, and the third set of seventh pins 173 each include two pin portions arranged side by side. Specifically, the first set of seventh pins 171 is located on the lower right side of the first base island 101, the second set of seventh pins 172 is located on the lower right side of the second base island 102, and the third set of seventh pins 173 is located on the lower right side of the third base island 103. The first set of seventh pins 171, the second set of seventh pins 172, and the third set of seventh pins 173 are all flush with and connected to the first pin 11, the second pin 12, and the third pin 13. The first set of seventh pins 171 includes two pin portions, namely a first source pin portion 171a and a first gate pin portion 171b; the second set of seventh pins 172 includes two pin portions, namely a second source pin portion 172a and a second gate pin portion 172b; the third set of seventh pins 173 includes two pin portions, namely a third source pin portion 173a and a third gate pin portion 173b. With the above structure, by providing multiple sets of seventh pins between specific pins (such as between the first pin 11 and the fifth pin 15, and between the second pin 12 and the sixth pin 16) and at specific positions (such as the right side of the third pin 13), and each set includes two pin portions arranged side by side, this layout effectively utilizes the space of the frame body 10. Compared with a single-pin layout, this multi-pin side-by-side setting method can provide more connection points without increasing the size of the frame body 10, improving the space utilization efficiency. The multiple sets of side-by-side pins may help form a more uniform heat distribution and reduce local overheating. Especially in high-power density applications, this layout may help improve the overall heat dissipation effect.

[0047] In the above embodiment, between the fourth pin 14 in the middle and the fourth pin 14 on the left side of the fourth base island 104, a first group of eighth pins 181 is provided, and between the fourth pin 14 in the middle and the fourth pin 14 on the right side, a second group of eighth pins 182 is provided. The first group of eighth pins 181 includes four pin parts arranged side by side, and the second group of eighth pins 182 includes two pin parts arranged side by side. Specifically, both the first group of eighth pins 181 and the second group of eighth pins 182 are flush with the three fourth pins 14; the four pin parts included in the first group of eighth pins 181, along the direction from the fourth chip 24 to the fifth chip 25, are respectively a fourth gate pin part 181a, a fourth source pin part 181b, a fifth gate pin part 181c, and a fifth source pin part 181d; the two pin parts included in the second group of eighth pins 182 are respectively a sixth gate pin part 182a and a sixth source pin part 182b. This layout effectively utilizes the space on the frame body 10. This way of arranging multiple pins side by side can provide more connection points without increasing the size of the frame body 10, improving the space utilization efficiency.

[0048] In some embodiments, the package structure of the top heat dissipation type MOS further includes a first bonding wire 41 for connecting the first chip 21, the fifth pin 15, the second chip 22, the sixth pin 16, and the third chip 23. Specifically, the upper surface of the chip is provided with a source electrode and a gate electrode, and the lower surface is provided with a drain electrode; the drain electrode of the chip is connected to the corresponding base island; the first bonding wire 41 is in a continuous wavy shape, and two first bonding wires 41 are arranged in parallel. The source electrodes of the first chip 21, the fifth pin 15, the second chip 22, the sixth pin 16, and the third chip 23 are electrically connected through the first bonding wire 41, ensuring the reliability of the electrical connection and facilitating the simplification of the wiring complexity.

[0049] In the above embodiment, the package structure of the top heat dissipation type MOS further includes a second bonding wire 42, which is respectively used for connecting between the first chip 21 and the first group of seventh pins 171, between the second chip 22 and the second group of seventh pins 172, and between the third chip 23 and the third group of seventh pins 173. Specifically, six second bonding wires 42 are provided. Among them, between the source electrode of the first chip 21 and the first source electrode pin part 171a, between the gate electrode of the first chip 21 and the first gate electrode pin part 171b, between the source electrode of the second chip 22 and the second source electrode pin part 172a, between the gate electrode of the second chip 22 and the second gate electrode pin part 172b, between the source electrode of the third chip 23 and the third source electrode pin part 173a, and between the gate electrode of the third chip 23 and the third gate electrode pin part 173b, a second bonding wire 42 is connected. With this structure, the electrical connection between the first chip 21 and the first group of seventh pins 171, between the second chip 22 and the second group of seventh pins 172, and between the third chip 23 and the third group of seventh pins 173 is realized, and it is beneficial to simplify the wiring complexity.

[0050] In the above embodiment, the package structure of the top heat dissipation type MOS further includes a third bonding wire 43, which is respectively used for connecting between the fourth chip 24 and the first group of eighth pins 181, between the fifth chip 25 and the first group of eighth pins 181, and between the sixth chip 26 and the second group of eighth pins 182. Specifically, six third bonding wires 43 are provided. Among them, between the gate electrode of the fourth chip 24 and the fourth gate electrode pin part 181a, between the source electrode of the fourth chip 24 and the fourth source electrode pin part 181b, between the gate electrode of the fifth chip 25 and the fifth gate electrode pin part 181c, between the source electrode of the fifth chip 25 and the fifth source electrode pin part 181d, between the gate electrode of the sixth chip 26 and the sixth gate electrode pin part 182a, and between the source electrode of the sixth chip 26 and the sixth source electrode pin part 182b, a third bonding wire 43 is provided. With this structure, the electrical connection between the fourth chip 24 and the first group of eighth pins 181, between the fifth chip 25 and the first group of eighth pins 181, and between the sixth chip 26 and the second group of eighth pins 182 is realized, and it is beneficial to simplify the wiring complexity.

[0051] In the above embodiment, the encapsulation structure of the top heat dissipation type MOS further includes a fourth bonding wire 44, which is respectively used to connect between the first base island 101 and the fourth chip 24, between the second base island 102 and the fifth chip 25, and between the third base island 103 and the sixth chip 26. Specifically, three groups of fourth bonding wires 44 are provided, and each group of fourth bonding wires 44 includes two wires arranged in parallel. Among them, two fourth bonding wires 44 are provided between the source electrode of the first base island 101 and the fourth chip 24, between the source electrode of the second base island 102 and the fifth chip 25, and between the source electrode of the third base island 103 and the sixth chip 26. This structure not only ensures the electrical connection between each chip, but also further optimizes the heat transfer path. Since the bonding wires themselves are also good conductors of heat, they can assist in conducting heat from the chips to the base islands, and then dissipate it through the frame body 10, thereby reducing the operating temperature of the chips.

[0052] It can be understood that the first chip 21 and the first base island 101, the second chip 22 and the second base island 102, the third chip 23 and the third base island 103, and the fourth chip 24, the fifth chip 25 and the sixth chip 26 and the fourth base island 104 are all connected by a connecting material. Specifically, between the drain electrode of the first chip 21 and the first base island 101, between the drain electrode of the second chip 22 and the second base island 102, between the drain electrode of the third chip 23 and the third base island 103, between the drain electrode of the fourth chip 24, the drain electrode of the fifth chip 25 and the drain electrode of the sixth chip 26 and the fourth base island 104, they are all connected by a connecting material. The connecting material can be lead-tin-silver solder, nano silver, SAC305, etc., which is used to realize the connection between the chip and the corresponding base island on the frame body 10.

[0053] In summary, the encapsulation structure of the top heat dissipation type MOS provided by the present invention realizes the integration of 6 MOS chips into one device by reasonably arranging the first base island 101, the second base island 102, the third base island 103 and the fourth base island 104 on the frame body 10, as well as the pin areas and chip groups 20 corresponding to each base island. This greatly reduces the usage area of the PCB board, improves the space utilization rate of the PCB, reduces the production cost of the enterprise, improves the efficiency, and can be used in high-power and high-current application scenarios.

[0054] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A top heat dissipation MOS packaging structure, characterized in that: include: The frame body includes a first base island, a second base island and a third base island arranged side by side and in sequence, and a fourth base island arranged in parallel on the opposite side, wherein the first base island, the second base island and the third base island are respectively connected to a pin area, and the fourth base island is connected to three pin areas; A chipset, comprising a first chip, a second chip and a third chip respectively arranged on the first base island, the second base island and the third base island, and a fourth chip, a fifth chip and a sixth chip arranged side by side along the length direction of the fourth base island; The packaging layer is coated on the frame body and exposes a side of the frame body away from the chipset and all the pin areas.

2. A top heat dissipation MOS packaging structure according to claim 1, characterized in that: The pin area of ​​the first base island is provided with a first pin, the pin area of ​​the second base island is provided with a second pin, the pin area of ​​the third base island is provided with a third pin, and each pin area connected to the fourth base island is provided with a fourth pin.

3. A top heat dissipation MOS packaging structure according to claim 2, characterized in that: A fifth pin is disposed between the first base island and the second base island, and a sixth pin is disposed between the second base island and the third base island.

4. The top heat dissipation MOS packaging structure according to claim 3, characterized in that: A first group of seventh pins is arranged between the first pin and the fifth pin, a second group of seventh pins is arranged between the second pin and the sixth pin, a third group of seventh pins is arranged on the right side of the third pin, and the first group of seventh pins, the second group of seventh pins and the third group of seventh pins each include two pin portions arranged side by side.

5. The top heat dissipation MOS packaging structure according to claim 2, characterized in that: A first group of eighth pins is arranged between the fourth pin in the middle and the fourth pin on the left side of the fourth base island, and a second group of eighth pins is arranged between the fourth pin in the middle and the fourth pin on the right side. The first group of eighth pins includes four pin portions arranged side by side, and the second group of eighth pins includes two pin portions arranged side by side.

6. The top heat dissipation MOS packaging structure according to claim 3, characterized in that: It also includes a first bonding wire for connecting the first chip, the fifth pin, the second chip, the sixth pin and the third chip.

7. The top heat dissipation MOS packaging structure according to claim 4, characterized in that: It also includes second bonding wires, which are respectively used to connect the first chip and the first group of seventh pins, the second chip and the second group of seventh pins, and the third chip and the third group of seventh pins.

8. The top heat dissipation MOS packaging structure according to claim 5, characterized in that: It also includes third welding wires, which are respectively used to connect the fourth chip and the first group of eighth pins, the fifth chip and the first group of eighth pins, and the sixth chip and the second group of eighth pins.

9. The top heat dissipation MOS packaging structure according to claim 1, characterized in that: It also includes fourth bonding wires, which are respectively used to connect the first base island and the fourth chip, the second base island and the fifth chip, and the third base island and the sixth chip.

10. The top heat dissipation MOS packaging structure according to claim 1, characterized in that: The first chip and the first base island, the second chip and the second base island, the third chip and the third base island, and the fourth chip, the fifth chip and the sixth chip and the fourth base island are all connected by connecting materials.

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