Multi-channel data acquisition circuit for network equipment logs

Abstract

The embodiment of the utility model provides a multi-channel data acquisition circuit for network equipment logs, which comprises an isolation circuit, a buffer circuit, a single chip microcomputer U1, a transmission circuit, a power supply circuit and at least one interface circuit, and is characterized in that network equipment is connected with the input end of the single chip microcomputer U1 through the interface circuit, the isolation circuit and the buffer circuit in sequence; the output end of the single-chip microcomputer U1 is in communication connection with an upper computer through the transmission circuit, and the power supply circuit is used for supplying power to the whole acquisition circuit. According to the application, the data of the network equipment can be extracted and integrated, the data is utilized, and the practicability is high.

Description

Technical Field

[0001] This application belongs to the technical field of network devices, and particularly relates to a multi-channel data acquisition circuit for network device logs. Background Art

[0002] The so-called real-time data acquisition from network transmission devices refers to directly reading the data transmitted in the network from network data transmission devices such as network interface cards and optical fiber splitters according to established data protocols, so that data can be collected into the big data platform at the maximum rate for data value-added processing and processing. With the popularization of "Internet +", society has crossed from the "IT" era to the "DT" era, and the big data platform has emerged as the times require.

[0003] Existing network ports generally can access one data acquisition device, and each data acquisition device is a single-channel data. Therefore, the device access capacity of the network port is low, the amount of accessed data is small, and the data acquisition efficiency is low, which cannot meet the big data acquisition requirements. Summary of the Invention

[0004] To solve one of the above technical defects, an embodiment of this application provides a multi-channel data acquisition circuit for network device logs.

[0005] According to an embodiment of this application, a multi-channel data acquisition circuit for network device logs is provided, including: an isolation circuit, a buffer circuit, a single-chip microcomputer U1, a transmission circuit, a power supply circuit, and at least one interface circuit. The network device is sequentially connected to the input end of the single-chip microcomputer U1 through the interface circuit, the isolation circuit, and the buffer circuit. The output end of the single-chip microcomputer U1 is communicatively connected to the host computer through the transmission circuit, and the power supply circuit is used to supply power to the entire acquisition circuit.

[0006] Preferably, the interface circuit includes a USB interface J1. The GND_DRAIN terminal of the USB interface J1 is respectively connected to the 5V power supply terminal, the VBUS terminal of the USB interface J1, and one end of a capacitor C1. The other end of the capacitor C1 is grounded. The D+ terminal and the D- terminal of the USB interface J1 are respectively connected to the input end of the isolation circuit through connection terminals A+ and A-. The GND terminal of the USB interface J1 is connected to the SHELL terminal of the USB interface J1 and then grounded.

[0007] Preferably, the isolation circuit includes a transformer chip U2. The HDB3_RXO_P terminal and the HDB3_RXO_N terminal of the transformer chip U2 are respectively connected to the terminal A+ and the terminal A-. A resistor R3 is connected in series between the HDB3_RXO_P terminal and the HDB3_RXO_N terminal of the transformer chip U2. The output middle shaft head terminal of the transformer chip U2 is respectively connected to one end of a capacitor C2 and one end of a resistor R2. The other end of the capacitor C2 is connected to the other end of the resistor R2 and then grounded. The connection line between the capacitor C2 and the resistor R2 is connected to the 3.3V power supply terminal after being connected in series with a resistor R1. The HDB3_RXYO+ terminal and the HDB3_RXYO- terminal of the transformer chip U2 are respectively connected to the positive input terminal and the negative input terminal of the buffer circuit.

[0008] Preferably, the buffer circuit includes a buffer chip U3. The 1G# terminal of the buffer chip U3 is grounded after being connected in series with a resistor R4. The connection line between the 1G# terminal of the buffer chip U3 and the resistor R4 is connected to the 2G# terminal of the buffer chip U3. The GND terminal of the buffer chip U3 is connected to the 5V power supply terminal after being connected in series with a capacitor C3. The 1A1 terminal and the 1A2 terminal of the buffer chip U3 are respectively connected to the HDB3_RXYO+ terminal and the HDB3_RXYO- terminal of the transformer chip U2. The 1G# terminal of the transformer chip U2 is connected to the input terminal of the single-chip microcomputer U1.

[0009] Preferably, the transmission circuit includes an Ethernet controller U5 and a network transformer U6. The SD0 terminal to the SD4 terminal of the Ethernet controller U5 are respectively connected to the PA8 terminal to the PA12 terminal of the single-chip microcomputer U1. The SD5 terminal to the SD7 terminal of the Ethernet controller U5 are respectively connected to the PD4 terminal to the PD6 terminal of the single-chip microcomputer U1. The SD8 terminal to the SD11 terminal of the Ethernet controller U5 are respectively connected to the PD12 terminal to the PD15 terminal of the single-chip microcomputer U1. The SD12 terminal to the SD15 terminal of the Ethernet controller U5 are respectively connected to the PC6 terminal to the PC9 terminal of the single-chip microcomputer U1. The CMD terminal of the Ethernet controller U5 is connected to the PD11 terminal of the single-chip microcomputer U1. The INT terminal, the IOR terminal, and the IOW terminal of the Ethernet controller U5 are respectively connected to the PD10 terminal, the PD9 terminal, and the PD8 terminal of the single-chip microcomputer U1;

[0010] The TX- and TX+ terminals of the Ethernet controller U5 are respectively connected to the TD- and TD+ terminals of the network transformer U6, and the RX- and RX+ terminals of the Ethernet controller U5 are respectively connected to the RD- and RD+ terminals of the network transformer U6. The TD+ terminal of the network transformer U6 is sequentially connected in series with a resistor R5 and a capacitor C6 and then grounded. The connection line between the resistor R5 and the capacitor C6 is connected in series with a resistor R6 and then connected to the TD- terminal of the network transformer U6. The RD+ terminal of the network transformer U6 is sequentially connected in series with a resistor R7 and a capacitor C9 and then grounded. The connection line between the resistor R7 and the capacitor C9 is connected in series with a resistor R8 and then connected to the RD- terminal of the network transformer U6. The TCT terminal of the network transformer U6 is connected in series with a capacitor C10 and then grounded. The connection line between the TCT terminal of the network transformer U6 and the capacitor C10 is connected to the RCT terminal of the network transformer U6.

[0011] Preferably, the model of the single-chip microcomputer U1 is STM32F103VCT6.

[0012] Preferably, the model of the voltage transformation chip U2 is 16ST1225CR.

[0013] Preferably, the model of the buffer chip U3 is SN74LS240DWR..

[0014] Preferably, the model of the Ethernet controller U5 is DM9000, and the model of the network transformer U6 is YL18-2050S..

[0015] Adopting a multi-channel data acquisition circuit for network device logs provided in the embodiment of the present application, the network device is connected to the single-chip microcomputer U1 through an interface circuit, an isolation circuit, and a buffer circuit. The log data of the network device can perform impedance matching and signal clutter suppression through the isolation circuit, ensuring the safety of the device. In addition, after being processed by the isolation circuit, it enters the buffer circuit, and the buffer circuit can protect the entire acquisition circuit and reduce the switching loss of the device. The present application can extract and integrate the data of the network device and utilize the data, with strong practicability. Description of the Drawings

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0017] Figure 1 is a schematic structural diagram of a multi-channel data acquisition circuit for network device logs provided by an embodiment of the present application;

[0018] Figure 2 is a circuit schematic diagram of an interface circuit in a multi-channel data acquisition circuit for network device logs provided by an embodiment of the present application;

[0019] Figure 3 This is the circuit schematic diagram of the isolation circuit in a multi-channel data acquisition circuit for network device logs provided by an embodiment of the present application;

[0020] Figure 4 This is the circuit schematic diagram of the buffer circuit in a multi-channel data acquisition circuit for network device logs provided by an embodiment of the present application;

[0021] Figure 5 、 Figure 6 This is the circuit schematic diagram of the transmission circuit in a multi-channel data acquisition circuit for network device logs provided by an embodiment of the present application;

[0022] In the figure: 1 is the isolation circuit, 2 is the buffer circuit, 3 is the transmission circuit, 4 is the power supply circuit, and 5 is the interface circuit. Detailed implementation manners

[0023] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further details the exemplary embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0024] The following details an embodiment of the present application with reference to the accompanying drawings.

[0025] Embodiment 1

[0026] As Figure 1 shown, a multi-channel data acquisition circuit for network device logs includes: an isolation circuit 1, a buffer circuit 2, a single-chip microcomputer U1, a transmission circuit 3, a power supply circuit 4, and at least one interface circuit 5. The network device is successively connected to the input end of the single-chip microcomputer U1 through the interface circuit 5, the isolation circuit 1, and the buffer circuit 2. The output end of the single-chip microcomputer U1 is communicatively connected to the host computer through the transmission circuit 3. The power supply circuit 4 is used to supply power to the entire acquisition circuit.

[0027] In this embodiment, the network device is connected to the single-chip microcomputer U1 through the interface circuit 5, the isolation circuit 1, and the buffer circuit 2. The log data of the network device can perform impedance matching and signal clutter suppression through the isolation circuit 1, ensuring the safety of the device. In addition, after being processed by the isolation circuit 1 and entering the buffer circuit 2, the buffer circuit 2 can protect the entire acquisition circuit and reduce the switching loss of the device. The present application can extract and integrate the data of the network device and utilize the data, with strong practicability.

[0028] Embodiment 2

[0029] As shown Figure 2 in FIG. 0, the interface circuit 5 includes a USB interface J1. The GND_DRAIN terminal of the USB interface J1 is respectively connected to the 5V power supply terminal, the VBUS terminal of the USB interface J1, and one end of a capacitor C1. The other end of the capacitor C1 is grounded. The D+ terminal and the D- terminal of the USB interface J1 are respectively connected to the input end of the isolation circuit 1 through a terminal block A+ and a terminal block A-. The GND terminal of the USB interface J1 is connected to the SHELL terminal of the USB interface J1 and then grounded.

[0030] As shown Figure 3 in FIG. 1, the isolation circuit 1 includes a transformer chip U2, and the model of the transformer chip U2 is 16ST1225CR. The HDB3_RXO_P terminal and the HDB3_RXO_N terminal of the transformer chip U2 are respectively connected to the terminal block A+ and the terminal block A-. A resistor R3 is connected in series between the HDB3_RXO_P terminal and the HDB3_RXO_N terminal of the transformer chip U2. The output middle tap terminal of the transformer chip U2 is respectively connected to one end of a capacitor C2 and one end of a resistor R2. The other end of the capacitor C2 is connected to the other end of the resistor R2 and then grounded. The connection line between the capacitor C2 and the resistor R2 is connected to the 3.3V power supply terminal after being connected in series with a resistor R1. The HDB3_RXYO+ terminal and the HDB3_RXYO- terminal of the transformer chip U2 are respectively connected to the positive input terminal and the negative input terminal of the buffer circuit 2.

[0031] Specifically, the HDB3_RXO_P terminal and the HDB3_RXO_N terminal of the transformer chip U2 are the input terminals of the transformer chip U2, and the corresponding HDB3_RXYO+ terminal and HDB3_RXYO- terminal are the output terminals of the transformer chip U2; similarly, the HDB3_TXO_P terminal and the HDB3_TXO_N terminal of the transformer chip U2 are the input terminals of the transformer chip U2, and the corresponding HDB3_TXYO+ terminal and HDB3_TXYO- terminal are the output terminals of the transformer chip U2; it can connect 2 USB interfaces for data acquisition and transmission.

[0032] In this embodiment, a resistor R3 is connected in series between the input terminals HDB3_RXO_P and HDB3_RXO_N of the transformer chip U2. The resistor R3 is a matching resistor. The isolation circuit 1 can couple and filter the differential signal input from the previous stage with a differential-mode coupling coil to enhance the signal, and through the conversion coupling of the electromagnetic field to the other end of the transformer chip U2, so that there is no physical connection between the two ends of the transformer chip U2 to transmit the signal, blocking the direct current in the signal, and can transmit data between devices with different levels.

[0033] As shown Figure 4As shown in the figure, the buffer circuit 2 includes a buffer chip U3, and the model of the buffer chip U3 is SN74LS240DWR. The 1G# terminal of the buffer chip U3 is connected to the ground after being serially connected with a resistor R4. The connection line between the 1G# terminal of the buffer chip U3 and the resistor R4 is connected to the 2G# terminal of the buffer chip U3. The GND terminal of the buffer chip U3 is connected to the 5V power supply terminal after being serially connected with a capacitor C3. The 1A1 terminal and 1A2 terminal of the buffer chip U3 are respectively connected to the HDB3_RXYO+ terminal and HDB3_RXYO- terminal of the transformer chip U2. The 1G# terminal of the transformer chip U2 is connected to the input terminal of the single-chip microcomputer U1. Specifically, since the waveform of the log data of the network device often distorts after being transmitted through the isolation circuit 1, resulting in the input waveform not being a standard differential signal. After passing through the buffer chip U3 in the buffer circuit 2, the buffer chip U3 converts the input distorted differential signal into a standard differential signal, effectively increasing the data transmission distance and reducing data reception errors caused by signal distortion during data transmission.

[0034] As Figure 5 shown in the figure, the transmission circuit 3 includes an Ethernet controller U5 and a network transformer U6. The model of the Ethernet controller U5 is DM9000, and the model of the network transformer U6 is YL18-2050S. The model of the single-chip microcomputer U1 is STM32F103VCT6. The SD0 terminal to SD4 terminal of the Ethernet controller U5 are respectively connected to the PA8 terminal to PA12 terminal of the single-chip microcomputer U1. The SD5 terminal to SD7 terminal of the Ethernet controller U5 are respectively connected to the PD4 terminal to PD6 terminal of the single-chip microcomputer U1. The SD8 terminal to SD11 terminal of the Ethernet controller U5 are respectively connected to the PD12 terminal to PD15 terminal of the single-chip microcomputer U1. The SD12 terminal to SD15 terminal of the Ethernet controller U5 are respectively connected to the PC6 terminal to PC9 terminal of the single-chip microcomputer U1. The CMD terminal of the Ethernet controller U5 is connected to the PD11 terminal of the single-chip microcomputer U1. The INT terminal, IOR terminal, and IOW terminal of the Ethernet controller U5 are respectively connected to the PD10 terminal, PD9 terminal, and PD8 terminal of the single-chip microcomputer U1.

[0035] As Figure 6As shown, the TX- terminal and TX+ terminal of the Ethernet controller U5 are respectively connected to the TD- terminal and TD+ terminal of the network transformer U6, the RX- terminal and RX+ terminal of the Ethernet controller U5 are respectively connected to the RD- terminal and RD+ terminal of the network transformer U6. The TD+ terminal of the network transformer U6 is connected to the ground after sequentially connecting the resistor R5 and the capacitor C6 in series. The connection line between the resistor R5 and the capacitor C6 is connected to the TD- terminal of the network transformer U6 after connecting the resistor R6 in series. The RD+ terminal of the network transformer U6 is connected to the ground after sequentially connecting the resistor R7 and the capacitor C9 in series. The connection line between the resistor R7 and the capacitor C9 is connected to the RD- terminal of the network transformer U6 after connecting the resistor R8 in series. The TCT terminal of the network transformer U6 is connected to the ground after connecting the capacitor C10 in series. The connection line between the TCT terminal of the network transformer U6 and the capacitor C10 is connected to the RCT terminal of the network transformer U6.

[0036] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0037] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0038] In the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or communication with each other; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal connection of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0039] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0040] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to cover these modifications and variations.

Claims

1. A multi-channel data acquisition circuit for network device logs, characterized in that: include: An isolation circuit (1), a buffer circuit (2), a single-chip computer U1, a transmission circuit (3), a power supply circuit (4) and at least one interface circuit (5); the network device is connected to the input end of the single-chip computer U1 via the interface circuit (5), the isolation circuit (1) and the buffer circuit (2) in sequence; the output end of the single-chip computer U1 is connected to a host computer via the transmission circuit (3); and the power supply circuit (4) is used to supply power to the entire acquisition circuit.

2. A multi-channel data acquisition circuit for network device logs according to claim 1, characterized in that: The interface circuit (5) comprises a USB interface J1, wherein a GND_DRAIN terminal of the USB interface J1 is respectively connected to a 5V power supply terminal, a VBUS terminal of the USB interface J1, and one end of a capacitor C1, the other end of the capacitor C1 is grounded, a D+ terminal and a D- terminal of the USB interface J1 are respectively connected to an input terminal of the isolation circuit (1) via a wiring terminal A+ and a wiring terminal A-, and a GND terminal of the USB interface J1 is connected to a SHELL terminal of the USB interface J1 and then grounded.

3. A multi-channel data acquisition circuit for network device logs according to claim 1, characterized in that: The isolation circuit (1) comprises a transformer chip U2, wherein the HDB3_RXO_P terminal and the HDB3_RXO_N terminal of the transformer chip U2 are respectively connected to the wiring terminal A+ and the wiring terminal A-, a resistor R3 is connected in series between the HDB3_RXO_P terminal and the HDB3_RXO_N terminal of the transformer chip U2, the output intermediate shaft head end of the transformer chip U2 is respectively connected to one end of a capacitor C2 and one end of a resistor R2, the other end of the capacitor C2 is connected to the other end of the resistor R2 and then grounded, the connection between the capacitor C2 and the resistor R2 is connected in series with a resistor R1 and then connected to a 3.3V power supply terminal, and the HDB3_RXYO+ terminal and the HDB3_RXYO- terminal of the transformer chip U2 are respectively connected to the input positive terminal and the input negative terminal of the buffer circuit (2).

4. A multi-channel data acquisition circuit for network device logs according to claim 3, characterized in that: The buffer circuit (2) comprises a buffer chip U3, wherein the 1G# terminal of the buffer chip U3 is connected in series with a resistor R4 and then grounded, the connection line between the 1G# terminal of the buffer chip U3 and the resistor R4 is connected to the 2G# terminal of the buffer chip U3, the GND terminal of the buffer chip U3 is connected in series with a capacitor C3 and then connected to a 5V power supply terminal, the 1A1 terminal and the 1A2 terminal of the buffer chip U3 are respectively connected to the HDB3_RXYO+ terminal and the HDB3_RXYO- terminal of the transformer chip U2, and the 1G# terminal of the transformer chip U2 is connected to the input terminal of the single-chip computer U1.

5. The multi-channel data acquisition circuit for network device logs according to claim 1, characterized in that: The transmission circuit (3) comprises an Ethernet controller U5 and a network transformer U6, wherein the SD0 to SD4 terminals of the Ethernet controller U5 are respectively connected to the PA8 to PA12 terminals of the single-chip microcomputer U1, the SD5 to SD7 terminals of the Ethernet controller U5 are respectively connected to the PD4 to PD6 terminals of the single-chip microcomputer U1, the SD8 to SD11 terminals of the Ethernet controller U5 are respectively connected to the PD12 to PD15 terminals of the single-chip microcomputer U1, the SD12 to SD15 terminals of the Ethernet controller U5 are respectively connected to the PC6 to PC9 terminals of the single-chip microcomputer U1, the CMD terminal of the Ethernet controller U5 is connected to the PD11 terminal of the single-chip microcomputer U1, and the INT terminal, IOR terminal and IOW terminal of the Ethernet controller U5 are respectively connected to the PD10 terminal, PD9 terminal and PD8 terminal of the single-chip microcomputer U1; The TX- and TX+ ends of the Ethernet controller U5 are connected to the TD- and TD+ ends of the network transformer U6 respectively, and the RX- and RX+ ends of the Ethernet controller U5 are connected to the RD- and RD+ ends of the network transformer U6 respectively. The TD+ end of the network transformer U6 is connected in series with resistor R5 and capacitor C6 in sequence and then grounded. The line between the resistor R5 and the capacitor C6 is connected in series with resistor R6 and then connected to the TD- end of the network transformer U6. The RD+ end of the network transformer U6 is connected in series with resistor R7 and capacitor C9 in sequence and then grounded. The line between the resistor R7 and the capacitor C9 is connected in series with resistor R8 and then connected to the RD- end of the network transformer U6. The TCT end of the network transformer U6 is connected in series with capacitor C10 and then grounded. The line between the TCT end of the network transformer U6 and the capacitor C10 is connected to the RCT end of the network transformer U6.

6. A multi-channel data acquisition circuit for network device logs according to claim 1, characterized in that: The model of the single chip microcomputer U1 is STM32F103VCT6.

7. A multi-channel data acquisition circuit for network device logs according to claim 3, characterized in that: The model of the transformer chip U2 is 16ST1225CR.

8. A multi-channel data acquisition circuit for network device logs according to claim 4, characterized in that: The model of the buffer chip U3 is SN74LS240DWR.

9. The multi-channel data acquisition circuit for network device logs according to claim 5, characterized in that: The model of the Ethernet controller U5 is DM9000, and the model of the network transformer U6 is YL18-2050S.

Images