Semiconductor device

Abstract

Embodiments described herein provide for various embodiments of gate-based alignment patterns for semiconductor process alignment of a substrate on which a plurality of semiconductor devices are fabricated. In some implementations described herein, a gate-based alignment pattern may be included in an alignment mark region of a semiconductor device, the alignment mark region fabricated on a substrate. The alignment mark region may include a plurality of gate structures that are etched to form a gate-based alignment pattern. The use of the gate-based alignment pattern may reduce and / or may prevent the likelihood that the gate-based alignment pattern is masked or covered by residual material byproducts from one or more semiconductor processing operations performed to form various layers and / or structures of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices including alignment marks. Background Art

[0002] Fin-based transistors, such as fin field effect transistors (finFETs) and nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate all around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors), are three-dimensional structures that include a channel region in a fin (or a portion of a fin), the fin extending above a semiconductor substrate as a three-dimensional structure. A gate structure, configured to control the flow of charge carriers within the channel region, the gate structure surrounds the fin of semiconductor material. As one embodiment, in a fin field effect transistor, the gate structure surrounds three sides of the fin (and therefore surrounds the channel region), thereby enabling increased control of the channel region (and therefore controlling the switching of the fin field effect transistor). As another embodiment, in a nanostructure transistor, the gate structure surrounds multiple channel regions in the fin structure, such that the gate structure surrounds each of the multiple channel regions. Source / drain regions (e.g., epitaxial regions) are located on opposite sides of the gate structure. Utility Model Content

[0003] Some embodiments of the present disclosure provide a semiconductor device comprising: one or more device regions and an alignment mark. The one or more device regions include a plurality of active transistor structures. The alignment mark is adjacent to at least a subset of the one or more device regions, and the alignment mark includes a plurality of non-active gate structures arranged in a pattern.

[0004] Other embodiments of the present disclosure provide a semiconductor device comprising: one or more device regions and an alignment mark. The one or more device regions include a plurality of active transistor structures. The alignment mark is adjacent to at least a subset of the one or more device regions, and the alignment mark includes a plurality of non-active gate structures arranged in a pattern. The pattern includes a plurality of rows of the plurality of non-active gate structures, and the plurality of rows are separated by a plurality of gaps between the plurality of rows.

[0005] Still other embodiments of the present disclosure provide a semiconductor device comprising: one or more device regions, a first alignment mark region, and a second alignment mark region. The one or more device regions include a plurality of active transistor structures. The first alignment mark region is adjacent to at least a subset of the one or more device regions, the first alignment mark region includes a plurality of non-active gate structures arranged in a pattern. The second alignment mark region is adjacent to another subset of the one or more device regions, the second alignment mark region includes a plurality of non-active fin structures arranged in a second pattern, and the second alignment mark region does not include a gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be seen in the following detailed description and in conjunction with the accompanying Figure 1 Please read together for the best understanding. It is noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2A and Figure 2B is a schematic diagram of an embodiment region of a semiconductor device described herein;

[0009] Figures 3A to 3G is a schematic diagram of an example implementation of an alignment mark (or portion of an alignment mark) that may be included in a semiconductor device described herein;

[0010] FIG. 4A to FIG. 4D is a schematic diagram of an implementation of the example embodiments described herein;

[0011] FIG. 5A to FIG. 5F is a schematic diagram of an implementation of the example embodiments described herein;

[0012] FIG. 6A to FIG. 6G is a schematic diagram of an implementation of the example embodiments described herein;

[0013] FIG. 7A to FIG. 7D is a schematic diagram of an example implementation of an active gate structure and a non-active gate structure described herein;

[0014] FIG. 8A to FIG. 8C is a schematic diagram of an embodiment region of a semiconductor device described herein;

[0015] 9A to 9C is a schematic diagram of an embodiment region of a semiconductor device described herein;

[0016] Fig. 10A and Fig. 10B is a schematic diagram of an embodiment region of a semiconductor device described herein;

[0017] Fig.11 is a schematic diagram of an embodiment lithography system described herein;

[0018] Fig.12 is a schematic diagram of an example implementation of performing alignment of a substrate as described herein;

[0019] Fig.13 is a schematic diagram of an embodiment assembly of an apparatus associated with a semiconductor device including an alignment mark;

[0020] Fig.14 is a flow chart of an embodiment process associated with forming a semiconductor device including an alignment mark as described herein;

[0021] Fig.15 is a flow chart of an embodiment process associated with alignment of a semiconductor device using the alignment marks described herein.

[0022]

Explanation of symbols

[0023] 100: Environment

[0024] 102:Deposition tools (semiconductor processing tools)

[0025] 104: Exposure tool (semiconductor processing tool)

[0026] 106: Developer tool (semiconductor processing tool)

[0027] 108: Etching tools (semiconductor processing tools)

[0028] 110: Planarization tool (semiconductor processing tool)

[0029] 112: Plating tools (semiconductor processing tools)

[0030] 114: Wafer / die transport tool (semiconductor processing tool)

[0031] 200:Semiconductor devices

[0032] 202:Substrate

[0033] 204: Active device area

[0034] 206: Alignment mark area

[0035] 208a: Fin structure

[0036] 208b: Fin structure

[0037] 208c: Fin structure

[0038] 210: shallow trench isolation layer

[0039] 210a: shallow trench isolation area

[0040] 210b: shallow trench isolation area

[0041] 210c: shallow trench isolation area

[0042] 212a: dummy gate structure

[0043] 212b: dummy gate structure

[0044] 214: Source / drain region

[0045] 216: Active transistor structure

[0046] 300: Implementation Method

[0047] 302: Pattern

[0048] 304: Column

[0049] 306: Column

[0050] 308: Gap

[0051] 310: Dielectric layer

[0052] 400: Implementation Method

[0053] 500: Implementation Method

[0054] 502a: Sealing spacer layer

[0055] 502b: Sealing spacer layer

[0056] 504a: bulk spacer layer

[0057] 504b: Bulk spacer layer

[0058] 506: Photoresist layer

[0059] 508: Pattern

[0060] 510: Mask layer

[0061] 512: concave part

[0062] 514: Source / drain region

[0063] 600: Implementation method

[0064] 602a: contact etching stop layer

[0065] 602b: contact etching stop layer

[0066] 604a: interlayer dielectric layer

[0067] 604b: interlayer dielectric layer

[0068] 606a: opening (recess)

[0069] 606b: opening (recess)

[0070] 608a: Gate structure

[0071] 608b: Gate structure

[0072] 700: Implementation method

[0073] 702:Metal Electrode

[0074] 704: Adhesive layer

[0075] 706: Work function metal layer

[0076] 708: Barrier layer

[0077] 710: Covering layer

[0078] 712: High dielectric constant dielectric layer

[0079] 714: Interface layer

[0080] 716: Covering layer

[0081] 718: Implementation Method

[0082] 720: Work function metal layer

[0083] 722: Implementation Method

[0084] 724: Work function metal layer

[0085] 726: Implementation Method

[0086] 728: Work function metal layer

[0087] 800:Semiconductor devices

[0088] 900:Semiconductor devices

[0089] 902: Pattern

[0090] 904: Column

[0091] 906: Column

[0092] 908: Gap

[0093] 1000:Semiconductor devices

[0094] 1100: Lithography System

[0095] 1102: Radiation Source

[0096] 1104:Exposure Tools

[0097] 1106: Radiation

[0098] 1108: Photomask

[0099] 1110: Photoresist layer

[0100] 1112:Container

[0101] 1114: Collector

[0102] 1116: Focus

[0103] 1118: Microdrops

[0104] 1120:Laser beam

[0105] 1122: Droplet generator head

[0106] 1124: Window

[0107] 1126: Illuminator

[0108] 1128:Projection Optical Box

[0109] 1130a: Reflector

[0110] 1130b: Reflector

[0111] 1132: Reflector

[0112] 1134a: Reflector

[0113] 1134b: Reflector

[0114] 1134c: Reflector

[0115] 1134d: Reflector

[0116] 1134e: Reflector

[0117] 1134f: Reflector

[0118] 1136: Wafer table

[0119] 1138: Bottom module

[0120] 1140: Mask stage

[0121] 1142: Laser source

[0122] 1144: Pre-alignment unit

[0123] 1200: Implementation method

[0124] 1202:Semiconductor device

[0125] 1204: Notch

[0126] 1206: Rough wafer alignment operation

[0127] 1208: Fine wafer alignment operation

[0128] 1210:Laser beam

[0129] 1210a: Laser beam

[0130] 1210b: Laser beam

[0131] 1212: Reflected light

[0132] 1300: Device

[0133] 1310: Bus

[0134] 1320: Processor

[0135] 1330:Memory

[0136] 1340: Input component

[0137] 1350: Output component

[0138] 1360: Communication Components

[0139] 1400: Craftsmanship

[0140] 1410: Block

[0141] 1420: Block

[0142] 1430: Block

[0143] 1440: Block

[0144] 1450: Block

[0145] 1500: Craftsmanship

[0146] 1510: Block

[0147] 1520: Block

[0148] D1: Dimensions

[0149] D2: Dimensions

[0150] D3: Dimensions

[0151] D4: Dimensions

[0152] D5: Dimensions

[0153] D6: Dimensions

[0154] D7: Dimensions

[0155] D8: Dimensions

[0156] D9: Dimensions

[0157] D10: Dimensions

[0158] AA: Section plane (cross section)

[0159] BB: Section plane (cross section)

[0160] CC: Section plane (cross section)

[0161] DD: Section plane (cross section)

[0162] EE: Cross-section

[0163] O1: Offset distance

[0164] x: direction

[0165] y: direction

[0166] z: direction DETAILED DESCRIPTION

[0167] The disclosure that follows provides many different implementations or embodiments for implementing different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify the disclosure. Of course, these are merely embodiments and are not restrictive. For example, in the subsequent description, a first feature is formed above or on a second feature, and an implementation in which the first feature and the second feature are formed in direct contact may be included, and an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplification and clarity, and the repetition itself does not mean the relationship between the various embodiments and / or configurations discussed.

[0168] Additionally, to facilitate description of the relationship of one element or feature to another element or feature as depicted in the figures, spatially relative terms may be used herein, such as "below," "below," "lower," "above," "upper," and the like. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0169] Semiconductor device manufacturing uses patterning techniques to transfer multiple layer designs on an optical mask or reticle to a semiconductor substrate. In other embodiments, a series of deposition, patterning, and etching techniques are used to build up the semiconductor device layer by layer. Accordingly, precise alignment of multiple layers in a semiconductor device (referred to as overlay or OVL) is an important parameter in achieving high yield and low rework rate in semiconductor manufacturing.

[0170] A substrate may include one or more alignment marks to facilitate accurate and repeatable alignment of the substrate across multiple semiconductor processing operations. An alignment mark includes an area of ​​the substrate that includes an alignment pattern that can be scanned and tracked to fine-tune the orientation of the substrate. For example, a laser illumination system of a lithography tool may scan the pattern of alignment marks to generate alignment data that may be used to determine whether alignment of the substrate has passed or failed. Additionally, the alignment data may be used to generate an overlay (OVL) compensation value to fine-tune alignment for subsequent semiconductor processing.

[0171] In some cases, the pattern of the alignment mark may become blurred so that the laser illumination system of the lithography tool can no longer reliably scan the pattern. This may occur, for example, when one or more semiconductor process operations cause residual material to remain above the pattern in the alignment mark. In some cases, residual material may remain above the pattern in the alignment mark because of depressions that occur when the dielectric layer above the pattern is planarized. The dielectric layer may be planarized in a planarization operation in preparation for performing a subsequent process, such as a replacement gate process, in which a dummy gate structure of a semiconductor device on a substrate is removed and replaced with a metal gate structure. The depressions may cause the height of the top surface of the dielectric layer to be smaller near the center of the alignment mark and larger near the periphery of the alignment mark.

[0172] Recesses in the dielectric layer above the pattern in the alignment mark may cause residual metal material from the replacement gate process to remain above the pattern, thereby obscuring the pattern and preventing the laser-based illumination system from scanning the pattern. This may result in alignment errors to the substrate, which may degrade overlay (OVL) performance for semiconductor devices on the substrate. Among other embodiments, the degraded overlay performance may result in reduced semiconductor device yield, increased alignment time (and therefore, reduced lithography tool productivity and yield), and / or increased semiconductor device rework.

[0173] In some cases, dishing can be mitigated by stopping the planarization of the dielectric layer prematurely, but this can result in insufficient planarization of the dielectric layer. In particular, if the planarization operation is stopped too early, insufficient dielectric layer may be removed from the top of the dummy gate structure, which may result in the inability to reach the dummy gate structure through the dielectric layer for the replacement gate process.

[0174] The various embodiments described herein provide various embodiments of gate-based alignment patterns for semiconductor process alignment of a substrate (on which a plurality of semiconductor devices are manufactured). In some embodiments described herein, a gate-based alignment pattern may be included in an alignment mark region in a semiconductor device (which is manufactured on a substrate). The alignment mark region may include a plurality of gate structures (e.g., dummy gate structures, polysilicon gate structures, metal gate structures), which are etched to form a gate-based alignment pattern. The use of a gate-based alignment pattern may reduce and / or prevent the possibility of the gate-based alignment pattern being obscured or covered by residual material byproducts from one or more semiconductor processing operations, which are performed to form various layers and / or structures of the semiconductor device. For example, a gate-based alignment pattern may enable a gate spacing parameter or design rule for a semiconductor device to be met in the alignment mark region. This may reduce the possibility of a depression in a dielectric layer above the gate structure in the alignment mark region. It may be possible to prevent dishing (or the extent of dishing may be minimized) because the close spacing of the gate structures in the alignment mark area may prevent or reduce the extent of deformation of the polishing pad when the dielectric layer is planarized (e.g., as part of a replacement gate process). The reduction in the extent of dishing or prevention of dishing in the dielectric layer may reduce and / or prevent the likelihood of residual metal material and / or other material remaining above the dielectric layer in the alignment mark area, which residual metal material and / or other material is deposited as part of a replacement gate process to form a metal gate structure of a semiconductor device. Accordingly, the gate-based alignment pattern of the alignment mark area may reduce and / or prevent the likelihood of residual metal material and / or other material shielding or blocking the pattern in the alignment mark area.

[0175] In this way, the gate-based alignment patterns described herein can improve the scanning accuracy and reliability of a laser-based illumination system for scanning the gate-based alignment patterns. This can reduce the likelihood of alignment errors to the substrate, which can improve the overlay performance for multiple semiconductor devices on the substrate. Among other embodiments, the increased overlay performance can achieve increased semiconductor device yields, can achieve reduced alignment times (and thereby increase the productivity and output of lithography tools), and / or can result in reduced semiconductor device rework. In addition, the gate-based alignment patterns described herein enable reduced recessing of the dielectric layer without increasing the likelihood that residual material from the dielectric layer is retained above the dummy gate structure of the semiconductor.

[0176] Figure 1 1 is a schematic diagram of an embodiment environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in , the embodiment environment 100 may include a plurality of semiconductor processing tools 102 to 112 and a wafer / die transport tool 114. The plurality of semiconductor processing tools 102 to 112 may include a deposition tool 102, an exposure tool 104, a developer tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or another type of semiconductor processing tool. Among other embodiments, the plurality of tools included in the embodiment environment 100 may be included in a semiconductor clean room, a semiconductor manufacturing plant, a semiconductor process facility, and / or a manufacturing facility.

[0177] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of chemical vapor deposition tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of physical vapor deposition tool. In some embodiments, deposition tool 102 includes an epitaxial tool configured to form multiple layers and / or multiple regions of a device via epitaxial growth. In some embodiments, embodiment environment 100 includes multiple deposition tools 102 and / or multiple types of deposition tools 102.

[0178] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet light (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool. In some embodiments, the embodiment environment 100 includes multiple exposure tools 104 and / or multiple types of exposure tools 104.

[0179] The developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing multiple unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing multiple exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving multiple exposed portions or multiple unexposed portions of the photoresist layer through the use of a chemical developer. In some embodiments, the embodiment environment 100 includes multiple developer tools 106 and / or multiple types of developer tools 106.

[0180] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may etch one or more portions of the substrate, using plasma etching or plasma-assisted etching, which may involve using ionized gas to etch one or more portions isotropically or directionally. In some embodiments, the embodiment environment 100 includes a plurality of etching tools 108 and / or a plurality of types of etching tools 108.

[0181] The planarization tool 110 is a semiconductor processing tool capable of grinding or flattening the individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool, and / or another type of planarization tool that grinds or flattens the layer or surface of the deposited material or the plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and abrasive-free grinding) to grind or flatten the surface of the semiconductor device. The planarization tool 110 may utilize grinding and corrosive chemical slurries, in combination with a grinding pad and a fixed ring (e.g., typically having a larger diameter than the semiconductor device). The grinding pad and the semiconductor device may be pressed together via a dynamic grinding head and maintained in a fixed position via a fixed ring. The dynamic grinding head may be rotated with different rotation axes to remove material and flatten any irregular topography of the semiconductor device, so that the semiconductor device becomes flat or flat. In some embodiments, the embodiment environment 100 includes a plurality of planarization tools 110 and / or a plurality of types of planarization tools 110.

[0182] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials. In some embodiments, the embodiment environment 100 includes a plurality of plating tools 112 and / or a plurality of types of plating tools 112.

[0183] The wafer / die transport tool 114 includes a mobile robot, a robotic arm, a tram, or a rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and / or another type of device configured to transport substrates and / or semiconductor devices between multiple semiconductor processing tools 102 to 112, configured to transport substrates and / or semiconductor devices between multiple processing chambers of the same semiconductor processing tool, and / or configured to transport substrates and / or semiconductor devices to other locations (e.g., wafer racks, storage chambers, and / or the like) and from other locations. In some embodiments, the wafer / die transport tool 114 may be a programmed device that is configured to travel a specific path and / or may be semi-automatically operated or automatically operated. In some embodiments, the embodiment environment 100 includes multiple wafer / die transport tools 114 and / or multiple types of wafer / die transport tools 114.

[0184] For example, in other embodiments, the wafer / die transport tool 114 may be included in a cluster tool, or in another type of tool including multiple processing chambers, and may be configured to transport substrates and / or semiconductor devices between multiple processing chambers, to transport substrates and / or semiconductor devices between a processing chamber and a buffer area, to transport substrates and / or semiconductor devices between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or to transport substrates and / or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)). In some embodiments, the wafer / die transport tool 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices), and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport tool 114 is configured to transport substrates and / or semiconductor devices between multiple process chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between the multiple process chambers and / or between multiple processing operations in the deposition tool 102, as described herein.

[0185] In some embodiments, one or more of the plurality of semiconductor processing tools 102 to 114 may perform one or more semiconductor processing operations described herein. For example, in other embodiments, one or more of the plurality of semiconductor processing tools 102 to 114 may perform other semiconductor processing operations described herein, such as in combination with FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5F , FIG. 6A to FIG. 6G , Fig.11 , Fig.12 , Fig.14 , and / or Fig.15 .

[0186] Provided in Figure 1 The number and arrangement of the devices shown in FIG. 1 are provided as one or more embodiments. Figure 1 There may be additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG. Figure 1 Two or more of the devices shown in the figure may be implemented in a single device, or in Figure 1The single device shown in the embodiment 100 may be implemented as multiple distributed devices. Additionally or alternatively, a group of multiple devices (e.g., one or more devices) of the embodiment environment 100 may perform one or more functions that are described as being performed by another group of multiple devices of the embodiment environment 100.

[0187] Figure 2A and Figure 2B 2 is a schematic diagram of an embodiment area of ​​a semiconductor device 200 described herein. The semiconductor device 200 may include a semiconductor die, a semiconductor wafer, and / or another type of semiconductor device fabricated on a substrate 202 .

[0188] The substrate 202 includes a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium (SiGe) substrate, or another type of semiconductor substrate. In other embodiments, the substrate 202 may include a round / circular substrate having a diameter of about 200 millimeters (mm), a diameter of about 300 mm, or another diameter (e.g., 450 mm). The substrate 202 may alternatively be any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a polygonal substrate.

[0189] The semiconductor device 200 may include one or more active device regions 204 and one or more alignment mark regions 206. Figure 2A The layouts, shapes, numbers, and / or arrangements of the active device regions 204 and the alignment mark regions 206 depicted are examples, and other layouts, shapes, numbers, and / or arrangements are also within the scope of the present disclosure.

[0190] An “active device region 204” refers to a region of the semiconductor device 200 that is functional in the final form of the semiconductor device 200. For example, in other embodiments, one active device region 204 may include a processor core, another active device region 204 may include a memory region, another active device region 204 may include an input / output (I / O), and / or another active device region 204 may include a power management region.

[0191] An “alignment mark region 206” refers to a region of a semiconductor device 200 that includes a pattern that is used for semiconductor processing operations (e.g., lithography or mask operations) to align a substrate 202 in a particular direction. An alignment mark region 206 may be a region of a semiconductor device 200 that is not functional in the final form of the semiconductor device 200. In some embodiments, a plurality of semiconductor devices 200 each include a corresponding alignment mark region 206 to enable multiple-point alignment to be performed on the substrate 202.

[0192] Figure 2B A perspective view of a portion of the active device area 204 and a portion of the alignment mark area 206 is depicted. FIG. 4A to FIG. 6G is Figure 2B Schematic cross-sectional views of various portions of the active device region 204 and the alignment mark region 206 are depicted and correspond to various processing stages of forming fin-based transistors in the active device region 204 and forming patterns in the alignment mark region 206 .

[0193] As in Figure 2B As shown in , a plurality of fin structures may be included above the substrate 202 for the active device region 204 and, in some cases, for the alignment mark region 206. Specifically, the fin structure 208a may be included above the substrate 202 in the active device region 204. In some embodiments, a plurality of fin structures 208b are included above the substrate 202 in the alignment mark region 206. However, as shown in Fig. 8A and Figure 8B As shown in FIG. 2 , for example, the fin structure 208 b may be omitted from the alignment mark region 206 .

[0194] The fin structure 208a may be referred to as an active fin structure because the fin structure 208a provides an active region in which one or more devices (e.g., fin-based transistors) are formed. The fin structure 208b may be referred to as an inactive fin structure (or a dummy fin structure) because the fin structure 208b may not be used for active devices of the semiconductor device 200. In some embodiments, the fin structures 208a and 208b include a silicon material or another elemental semiconductor material, such as germanium, or a compound semiconductor material, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. In some embodiments, the fin structures 208a and 208b may include an alloy semiconductor material, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or a combination thereof. In some embodiments, the fin structures 208 a and 208 b may be doped using n-type and / or p-type dopants.

[0195] In other embodiments, the fin structures 208a and 208b are fabricated by suitable semiconductor process techniques, such as masking, photolithography, and / or etching processes. As one embodiment, the fin structures 208a and 208b can be formed by etching away a portion of the substrate 202 to form a recess in the substrate 202. The recess can then be filled with an isolation material, which is recessed or etched back to form a shallow trench isolation (STI) region 210a above the substrate 202 and between the plurality of fin structures 208a, and a shallow trench isolation region 210b above the substrate 202 and between the plurality of fin structures 208b. Other fabrication techniques for the shallow trench isolation regions 210a and 210b and / or the fin structures 208a and 208b can be used. The shallow trench isolation regions 210a and 210b may electrically isolate adjacent multiple active regions in the fin structures 208a and 208b and / or may provide structural support for the fin structures 208a and 208b. The shallow trench isolation regions 210a and 210b may include dielectric materials, such as silicon oxide SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low dielectric constant (k) dielectric materials, and / or other suitable insulating materials. The shallow trench isolation regions 210a and 210b may include a multilayer structure, for example, with one or more liner layers.

[0196] A plurality of dummy gate structures 212a are included in the active device region 204 above the fin structure 208a (e.g., approximately perpendicular to the fin structure 208a). A plurality of dummy gate structures 212b are included in the alignment mark region 206 above the fin structure 208b (e.g., approximately perpendicular to the fin structure 208b). The dummy gate structure 212a and / or the dummy gate structure 212b may each include a polysilicon (poly or PO) structure and may therefore be referred to as a dummy polysilicon structure. In other embodiments, additionally and / or alternatively, the dummy gate structure 212a and / or the dummy gate structure 212b may each include one or more layers, such as a gate dielectric layer, a gate electrode layer, and / or a hard mask layer. The dummy gate structure 212a may include portions surrounding at least three sides of one or more fin structures 208a and portions on top of the shallow trench isolation region 210a. The dummy gate structure 212 b may include a portion surrounding at least three sides of the one or more fin structures 208 b and a portion on top of the shallow trench isolation region 210 b .

[0197] As used herein, the term "dummy" refers to a sacrificial structure that will be removed in a subsequent stage and replaced by another structure, such as a metal gate structure (including a high dielectric constant (high-k) dielectric and / or metal layer). The process of replacing the dummy gate structures 212a and 212b with metal gate structures may be referred to as a replacement gate process (RGP), and the embodiment process is combined with FIG. 6A to FIG. 6G Draw and describe.

[0198] Relative to the dummy gate structure 212a, multiple source / drain regions 214 are disposed in multiple regions relative to the fin structure 208a. "Source / drain" may refer to a source or a drain, individually or collectively depending on the context. Multiple source / drain regions 214 include multiple regions in the active device region 204, wherein multiple source / drain regions of multiple active transistor structures 216 are formed in the active device region 204. Multiple source / drain regions in the active device region 204 may include silicon (Si) epitaxially grown on the fin structure 208a. In some embodiments, the source / drain region may be doped with one or more types of dopants, such as p-type materials and / or n-type materials. Among other embodiments, the p-type material may include boron (B) or germanium (Ge). Among other embodiments, the n-type material may include phosphorus (P) or arsenic (As).

[0199] Some source / drain regions may be shared between transistors in the active device region 204. In some embodiments, each of the plurality of source / drain regions may be connected or coupled together such that the plurality of fin-based transistors in the active device region 204 are implemented as two functional transistors. For example, if adjacent (e.g., not opposing) source / drain regions are electrically connected, such as by epitaxial growth to merge these regions (e.g., adjacent plurality of source / drain regions are merged together, rather than multiple source / drain regions on opposite sides of the dummy gate structure 212a), then two functional transistors may be implemented. Other configurations in other embodiments may implement other numbers of functional transistors.

[0200] Figure 2B Further illustrating the reference cross-sections used in the following figures, in other embodiments, including FIG. 4A to FIG. 6G . Section AA is in a plane along a channel in the fin structure 208a between opposing source / drain regions 214. Section BB is in a plane along a channel in the fin structure 208b. Section CC is in a plane perpendicular to section AA and spans multiple source / drain regions 214 in the fin structure 208a. Section DD is in a plane perpendicular to section BB and spans multiple fin structures 208b and multiple shallow trench isolation regions 210b. Section EE is also in a plane perpendicular to section BB and along a dummy gate structure 212b in the alignment mark area 206. For clarity, subsequent multiple figures refer to these reference cross sections. In some figures, in order to facilitate the description of these figures, some reference numbers of components or features shown therein may be omitted to avoid obscuring other components or features.

[0201] As mentioned above, it provides Figure 2A and Figure 2B As an example, other embodiments may differ from the Figure 2A and Figure 2B The content described.

[0202] Figures 3A to 3G is a schematic diagram of an example implementation 300 of an alignment mark region 206 (or a portion thereof) that may be included in the semiconductor device 200 described herein.

[0203] Figure 3A A top view of an example implementation 300 of the alignment mark region 206 is depicted. Figure 3AAs shown in , the alignment mark area 206 may include a dimension D1, which corresponds to the length of the alignment mark area 206. In some embodiments, the dimension D1 is included in the range of about 30 microns to about 300 microns. However, other values ​​for this range are also within the scope of the present disclosure. The alignment mark area 206 may include a dimension D2, which corresponds to the width of the alignment mark area 206. In some embodiments, the dimension D2 is included in the range of about 30 microns to about 300 microns. However, other values ​​for this range are also within the scope of the present disclosure. In some embodiments, the ratio of the dimension D2 to the dimension D1 may be included in the range of about 1:1 to about 100:1. However, other values ​​for this range are also within the scope of the present disclosure. In some embodiments, the ratio of the dimension D1 to the dimension D2 may be included in the range of about 1:1 to about 100:1. However, other values ​​for this range are also within the scope of the present disclosure.

[0204] As in Figure 3A As further shown in FIG. 1 , the alignment mark region 206 may include a plurality of fin structures 208 b extending in a first direction (e.g., an x-direction) in the semiconductor device 200. The alignment mark region 206 may also include a plurality of dummy gate structures 212 b extending in a second direction (e.g., a y-direction) in the semiconductor device 200 over at least a subset of the fin structures 208 b. The first direction and the second direction may be approximately perpendicular, and thus the fin structures 208 b and the dummy gate structures 212 b may be approximately perpendicular in the alignment mark region 206.

[0205] As described above, a replacement gate process may be performed to replace the dummy gate structure 212b with a metal gate structure. Accordingly, the metal gate structure in the alignment mark region 206 in the final structure of the semiconductor device 200 may meet the requirements of the bonding process. Figures 3A to 3G The arrangement and characteristics of the pattern 302 and the dummy gate structure 212b described. The dummy gate structure 212b (and therefore, the metal gate structure replacing this dummy gate structure 212b) may have a dimension D3 and a dimension D4. The dimension D3 may correspond to the length of the dummy gate structure 212b. The dimension D4 may correspond to the width of the dummy gate structure 212b. In some embodiments, the dimension D3 may be included in the range of about 1,000 nanometers to about 4,000 nanometers. However, other values ​​for this range are also within the scope of the present disclosure. In some embodiments, the dimension D4 may be included in the range of about 100 nanometers to about 300 nanometers. However, other values ​​for this range are also within the scope of the present disclosure.

[0206] The alignment mark region 206 may include a pattern 302 formed by an arrangement of a plurality of dummy gate structures 212b in the alignment mark region 206. Thus, the pattern 302 in the alignment mark region 206 may be referred to as a polysilicon gate-based alignment pattern or a dummy gate-based alignment pattern. The pattern 302 may include a plurality of angled columns 304 and columns 306 separated by a plurality of gaps 308. The columns 304 and columns 306 may extend in the xy direction in the alignment mark region 206 such that the columns 304 and columns 306 are diagonal to the fin structures 208b. Thus, the columns 304 and columns 306 may extend in a non-perpendicular direction relative to the direction (x direction) in which the fin structures 208b (e.g., non-active fin structures) extend. The plurality of columns 304 may include a plurality of non-intersecting columns, and the plurality of columns 306 may include a plurality of intersecting columns 304 , thereby forming a plurality of approximately V-shaped columns 306 separated by a plurality of approximately V-shaped gaps 308 .

[0207] The pattern 302 may be formed by forming a plurality of dummy gate structures 212b such that the plurality of dummy gate structures 212b extend in a second direction (e.g., the y-direction), and then etching portions of the plurality of dummy gate structures 212b to remove the portions of the plurality of dummy gate structures 212b, which results in the formation of a plurality of gaps 308 between the plurality of columns 304, 306. The plurality of dummy gate structures 212b may be etched such that the ends of the plurality of dummy gate structures 212b in a same column 304 or column 306 are staggered or offset by an offset distance O1 in a first direction (e.g., the x-direction). The plurality of dummy gate structures 212b in a column 304 or column 306 may be separated by a dimension D5 from the plurality of dummy gate structures 212b in an adjacent column 304 or column 306 via the gaps 308. The plurality of dummy gate structures 212b in the same column 304 or column 306 may be separated by a dimension D6. In some embodiments, the gate pitch (e.g., dimensions D5 and D6) of the plurality of dummy gate structures 212b in the alignment mark region 206 may be substantially the same as the gate pitch of the plurality of dummy gate structures 212a in the active device region of the semiconductor device 200. This may be because the dummy gate structures 212a and the dummy gate structures 212b are formed in the same set of semiconductor processes.

[0208] Figure 3B and Figure 3C Draw along the Figure 2B and Figure 3A Section view of the middle section EE. Figure 3B and Figure 3CAs shown in , the dummy gate structure 212b may extend across the plurality of fin structures 208b in the alignment mark region 206. The dummy gate structure 212b may be covered by a dielectric layer 310. The dielectric layer 310 may correspond to an interlayer dielectric (ILD) layer, such as an ILD0 layer, of the semiconductor device 200. In some embodiments, the dielectric layer 310 may have a thickness included in the range of about 200 nanometers to about 5,000 nanometers. However, other values ​​for this range are also within the scope of the present disclosure. In some embodiments, the dielectric layer 310 may have a thickness included in the range of about 200 nanometers to about 3,000 nanometers. However, other values ​​for this range are also within the scope of the present disclosure. The dielectric layer 310 may include an oxide-containing material, a nitride-containing material, and / or another type of dielectric material. In other embodiments, the dielectric layer 310 may include a dielectric material including silicon (Si), hafnium (Hf), zirconium (Zr), lead (Pb), antimony (Sb), and / or lanthanum (La).

[0209] The use of the dummy gate structures 212b in the alignment mark area 206 can reduce or prevent the possibility of the pattern 302 being obscured or covered by residual material byproducts from one or more semiconductor processing operations performed to form various layers and / or structures of the semiconductor device 200. For example, the use of the dummy gate structures 212b in the alignment mark area 206 can enable gate spacing parameters or design rules for the semiconductor device 200 to be met in the alignment mark area 206. Specifically, the dimensions D5 and D6 can meet the gate spacing parameters with an area of ​​about 2 square microns or less between the plurality of dummy gate structures 212b in the alignment mark area 206. This can reduce the possibility of depressions in the dielectric layer 310, where the height of the dielectric layer 310 at the center of the alignment mark area 206 is less than the height of the dielectric layer 310 at the periphery of the alignment mark area. Disk formation may be prevented (or the magnitude of the disk formation may be minimized) because the close spacing of the plurality of dummy gate structures 212 b in the alignment mark region 206 may prevent or reduce the extent of deformation of the polishing pad of the planarization tool 110 when the planarization tool 110 is used to planarize the dielectric layer 310 (e.g., as part of a replacement gate process). The reduction in the extent of disk formation or the prevention of disk formation in the dielectric layer 310 may reduce and / or prevent the likelihood of residual metal material and / or other material remaining above the dielectric layer 310 in the alignment mark region 206, which residual metal material and / or other material is deposited as part of a replacement gate process to form a metal gate structure of the semiconductor device 200. Accordingly, in the example implementation 300, the polysilicon gate-based alignment pattern or the dummy gate-based alignment pattern of the alignment mark region 206 may reduce and / or prevent the likelihood of residual metal material and / or other material shielding or blocking the pattern 302 in the alignment mark region 206.

[0210] Figures 3D to 3G Various top-down shapes and / or arrangements for the alignment mark areas 206 are depicted. Figure 3D In the y direction, the dimension D2 is larger than the dimension D1 in the x direction. Figure 3E In the example, the dimension D1 in the x direction is larger than the dimension D2 in the y direction. Figure 3F In FIG. 2 , the alignment mark region 206 is rotated so that the dimensions D1 and D2 are in the xy direction in the semiconductor device 200 . FIG. 3A to FIG. 3F In some embodiments, the alignment mark area 206 includes a substantially rectangular shape. Alternatively, the alignment mark area 206 may include a substantially square, substantially triangular, substantially circular, and / or another shape. In some embodiments, the alignment mark area 206 may include an irregular shape, such as in Figure 3GGenerally, the alignment mark region 206 can be sized, shaped, and / or oriented to accommodate placement of the alignment mark region 206 in the semiconductor device 200 layout and to accommodate the layout and / or arrangement of the plurality of active device regions 204 in the semiconductor device 200 layout.

[0211] As mentioned above, providing Figures 3A to 3G As an example, other embodiments may differ from the Figures 3A to 3G The content described.

[0212] FIG. 4A to FIG. 4D is a schematic diagram of an example implementation 400 described herein. Example implementation 400 includes an example of forming fin structures 208a and 208b for active device region 204 and alignment mark region 206 of semiconductor device 200. FIG. 4A to FIG. 4D , for active device region 204, from Figure 2B The angle of the cross-sectional plane CC in the alignment mark area 206 is Figure 2B In some embodiments, the alignment mark region 206 may be masked during the fin formation process such that the plurality of fin structures 208 a are formed only in the active device region 204 and the plurality of fin structures 208 b are omitted from the alignment mark region 206 .

[0213] Steering Figure 4A , example implementation 400 includes semiconductor processing operations associated with substrate 202 , in which and / or on which transistors in active device region 204 may be formed, and in which and / or on which pattern 302 in alignment mark region 206 may be formed.

[0214] As in Figure 4B As shown in FIG. 1 , a plurality of fin structures 208 a and 208 b are respectively formed in the active device region 204 and the alignment mark region 206 in the substrate 202. Specifically, one or more fin structures 208 a are formed in the active device region 204 in the substrate 202, and one or more fin structures 208 b are formed in the alignment mark region 206 in the substrate 202.

[0215] In some embodiments, a pattern in a photoresist layer is used to form fin structures 208a and 208b. In these embodiments, a deposition tool 102 is used to form a photoresist layer on a substrate 202. An exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 is used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch into the substrate 202 to form multiple fin structures 208a and 208b. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based formation of fin structures 208a and 208b.

[0216] As in Figure 4C As shown in FIG. 1 , a shallow trench isolation layer 210 is formed between the plurality of fin structures 208 a and between the plurality of fin structures 208 b. A deposition tool 102 is used to deposit the shallow trench isolation layer 210, using chemical vapor deposition technology, physical vapor deposition technology, atomic layer deposition technology, or a combination of the above. Figure 1 The deposition technique described, and / or another deposition technique. In some embodiments, the shallow trench isolation layer 210 is formed to a height greater than the height of the fin structures 208a and 208b. In these embodiments, a planarization tool 110 is used to perform a planarization (or grinding) operation to planarize the shallow trench isolation layer 210 so that the top surface of the shallow trench isolation layer 210 is substantially flat and smooth, and the top surface of the shallow trench isolation layer 210 and the top surfaces of the plurality of fin structures 208a and 208b are approximately the same height. The planarization operation can increase the uniformity of the shallow trench isolation regions 210a and 210b formed in a subsequent back etch operation.

[0217] As in Figure 4DAs shown in , the shallow trench isolation layer 210 is etched in an etch-back operation to expose multiple portions of the plurality of fin structures 208a and 208b. An etching tool 108 is used to etch a portion of the shallow trench isolation layer 210, using a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. The remaining portion of the shallow trench isolation layer 210 between the plurality of fin structures 208a includes a shallow trench isolation region 210a, and the remaining portion of the shallow trench isolation layer 210 between the plurality of fin structures 208b includes a shallow trench isolation region 210b. In some embodiments, the shallow trench isolation layer 210 is etched so that the height of the exposed portion of the fin structure 208a (e.g., the portion of the fin structure 208a above the top surface of the shallow trench isolation region 210a) and the height of the exposed portion of the fin structure 208b (e.g., the portion of the fin structure 208b above the top surface of the shallow trench isolation region 210b) are the same height. In some embodiments, the shallow trench isolation layer 210 is etched such that the height of the exposed portion of the fin structure 208 a and the height of the exposed portion of the fin structure 208 b are different.

[0218] As mentioned above, providing FIG. 4A to FIG. 4D As an example, other embodiments may differ from the FIG. 4A to FIG. 4D The content described.

[0219] FIG. 5A to FIG. 5F is a schematic diagram of an example implementation 500 described herein. Example implementation 500 includes forming a plurality of dummy gate structures 212a and 212b, forming pattern 302 from dummy gate structure 212b in alignment mark region 206, and forming source / drain regions in source / drain region 214 of active device region 204. For active device region 204, FIG. 5A to FIG. 5F It is from Figure 2B As shown in FIG. 1 , for the alignment mark region 206 , FIG. 5A to FIG. 5F It is from Figure 2B In some embodiments, in combination with FIG. 4A to FIG. 4D After the described fin formation process, the operations described in conjunction with the embodiment 500 are performed.

[0220] As in Figure 5AAs shown in , a plurality of dummy gate structures 212a are formed in the active device region 204, and a plurality of dummy gate structures 212b are formed in the alignment mark region 206. The dummy gate structure 212a is formed and included above the fin structure 208a, and surrounds multiple sides of the fin structure 208a, so that the dummy gate structure 212a surrounds the fin structure 208a at least three sides of the fin structure 208a. The dummy gate structure 212b is formed and included above the fin structure 208b, and surrounds multiple sides of the fin structure 208b, so that the dummy gate structure 212b surrounds the fin structure 208b at three sides of the fin structure 208b. The dummy gate structures 212a and 212b may each include a polysilicon layer and / or other suitable layers. The dummy gate structures 212 a and 212 b may be formed via a suitable deposition process (eg, using deposition tool 102 ), such as low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, among other embodiments.

[0221] The plurality of dummy gate structures 212 a and 212 b are formed as placeholders for actual gate structures (e.g., replacing a high-k gate or a metal gate) to be formed in the active device region 204 and the alignment mark region 206, respectively. The dummy gate structures 212 a and 212 b may be replaced as part of a replacement gate process, which enables other layers and / or structures to be formed prior to the formation of the replacement gate structures.

[0222] As in Figure 5A As further shown in , the sealing spacer layer 502a may be included on the sidewalls of the dummy gate structure 212a. Similarly, the sealing spacer layer 502b may be included on the sidewalls of the dummy gate structure 212b. The sealing spacer layers 502a and 502b may be conformally deposited (e.g., using the deposition tool 102) and may include silicon oxycarbide (SiOC), nitrogen-free SiOC, or another suitable material. Among other embodiment deposition techniques, the sealing spacer layers 502a and 502b may be formed in an atomic layer deposition operation, wherein various types of precursor gases including silicon (Si) and carbon (C) are sequentially supplied in multiple alternating cycles to form the sealing spacer layers 502a and 502b.

[0223] As in Figure 5AAs further shown in , bulk spacer layer 504a may be formed on sealing spacer layer 502a. Similarly, bulk spacer layer 504b may be formed on sealing spacer layer 502b. Bulk spacer layers 504a and 504b may be formed of materials similar to sealing spacer layers 502a and 502b. However, bulk spacer layers 504a and 504b may be formed without plasma surface treatment for sealing spacer layers 502a and 502b. In addition, bulk spacer layers 504a and 504b may be formed to a greater thickness (relative to the thickness of sealing spacer layers 502a and 502b).

[0224] In some embodiments, the sealing spacer layers 502a and 502b and the bulk spacer layers 504a and 504b are conformally deposited (e.g., using deposition tool 102) on the dummy gate structures 212a and 212b, respectively, and on the fin structures 208a and 208b, respectively. The sealing spacer layers 502a and 502b and the bulk spacer layers 504a and 504b are then patterned (e.g., using deposition tool 102, exposure tool 104, and developer tool 106) and etched (e.g., using etching tool 108) to remove the sealing spacer layers 502a and 502b and the bulk spacer layers 504a and 504b from the top of the dummy gate structures 212a and 212b, respectively, and from the fin structures 208a and 208b, respectively.

[0225] As in Figure 5B As shown in , a photoresist layer 506 is formed over and / or on fin structure 208a, over and / or on dummy gate structure 212a, over and / or on fin structure 208b, and over and / or on dummy gate structure 212b. Photoresist layer 506 may also be formed over shallow trench isolation region 210a (e.g., exposed portion of shallow trench isolation region 210a) and over shallow trench isolation region 210b (e.g., exposed portion of shallow trench isolation region 210b). Deposition tool 102 may be used to form photoresist layer 506 using a spin coating technique or another deposition technique. A photoresist layer 506 is formed to protect portions of the fin structure 208a, the shallow trench isolation region 210a, the dummy gate structure 212a, the fin structure 208b, the shallow trench isolation region 210b, and the dummy gate structure 212b during a subsequent etching operation, in which other portions of the dummy gate structure 212b are etched to form a pattern 302 (e.g., a dummy gate-based alignment pattern or a polysilicon-based alignment pattern) in the alignment mark region 206.

[0226] As in Figure 5B and Figure 5CAs shown in , a pattern 508 can be formed in the photoresist layer 506 over the dummy gate structure 212 b in the alignment mark region 206. The pattern 508 can include a plurality of openings in the photoresist layer 506 over the dummy gate structure 212 b through which portions of the dummy gate structure 212 b are exposed through the photoresist layer 506. An exposure tool 104 can be used to expose the photoresist layer 506 to a radiation source to form the pattern 508 in the photoresist layer 506. A developer tool 106 is used to develop and remove portions of the photoresist layer 506 to expose the pattern 508.

[0227] As in Figure 5D As shown in , an etching tool 108 is used to etch multiple portions of the multiple dummy gate structures 212b exposed by the pattern 508 in the photoresist layer 506 to remove multiple exposed portions of the dummy gate structures 212b. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. Removing the multiple exposed portions of the multiple dummy gate structures 212b causes the formation of a pattern in the alignment mark area 206, which may include multiple columns 304, columns 306 of multiple dummy gate structures 212b separated by multiple gaps 308. In some embodiments, after the formation of the pattern 302, the photoresist removal tool removes multiple remaining portions of the photoresist layer (for example, using a chemical stripper, plasma ashing, and / or another technique).

[0228] As in Figure 5E As shown in , a mask layer 510 is formed above and / or on the fin structure 208b and above and / or on the dummy gate structure 212b. The mask layer 510 may also be formed over the shallow trench isolation region 210b (e.g., the exposed portion of the shallow trench isolation region 210b). A deposition tool 102 may be used to form the mask layer 510, using a spin coating technique or another deposition technique. The mask layer 510 is formed to protect the fin structure 208b, the shallow trench isolation region 210b, and the dummy gate structure 212b in a subsequent etching operation, in which the recessed portion for the source / drain region of the transistor in the active device region 204 is partially etched. Additionally, a mask layer 510 is formed to protect the fin structure 208 b , the shallow trench isolation region 210 b , and the dummy gate structure 212 b during a subsequent epitaxial growth operation in which source / drain regions of transistors in the active device region 204 are formed in the recesses.

[0229] As in Figure 5EAs further shown in FIG. 1 , during the etching operation, a plurality of recesses 512 are formed in the plurality of fin structures 208a in the active device region 204 between the plurality of dummy gate structures 212a. The etching operation may be referred to as a strained source / drain (SSD) etching operation, and the recesses 512 may be referred to as strained source / drain regions. After forming the mask layer 510, an etching tool 108 may be used to form the recesses 512. In this manner, the mask layer 510 protects the fin structures 208b and other structures in the active device region 204 from being etched during the etching operation. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique.

[0230] As in Fig. 5F As shown in , source / drain regions 514 are formed in recesses 512 in the active device region 204 of the semiconductor device 200 above the substrate 202. A deposition tool 102 may be used to form the source / drain regions 514 using an epitaxial growth technique in which an epitaxial material layer is deposited in the recess 512 so that multiple layers of the source / drain regions 514 are formed via epitaxial growth with a specific crystal orientation. The source / drain regions 514 are included between multiple dummy gate structures 212a and are at least partially below and / or lower than the dummy gate structures 212a. The source / drain regions 514 may partially extend above the top surface of the fin structure 208a.

[0231] The material used to form the source / drain regions 514 (e.g., silicon (Si), gallium (Ga), or another type of semiconductor material) may be doped with p-type dopants (e.g., a type of dopant that includes electron acceptor atoms (which create holes in the material)), n-type dopants (e.g., a type of dopant that includes hole acceptor atoms (which create electrons in the material)), and / or another type of dopant. Doping the material may be accomplished by adding impurities (e.g., p-type dopants or n-type dopants) to source gases used during epitaxial operations.

[0232] As mentioned above, it provides FIG. 5A to FIG. 5F As an example, other embodiments may differ from the FIG. 5A to FIG. 5F The content described.

[0233] FIG. 6A to FIG. 6G 600. The embodiment 600 includes an embodiment replacement gate process in which the dummy gate structures 212a and 212b are replaced with metal gate structures (including high-k and / or metal layers). For the active device region 204, FIG. 6A to FIG. 6G It is from Figure 2B As shown in FIG. 1 , for the alignment mark region 206 , FIG. 6A to FIG. 6G It is from Figure 2B The angle of the cross-sectional plane BB is shown.

[0234] As in Fig. 6A As shown in FIG. 1 , a contact etch stop layer (CESL) 602a is conformally deposited (e.g., using deposition tool 102) over source / drain regions 514, over dummy gate structures 212a, and on sidewalls of bulk spacer layer 504a. Similarly, a contact etch stop layer 602b is conformally deposited (e.g., using deposition tool 102) over fin structures 208b, over shallow trench isolation regions 210b, over dummy gate structures 212b, and on sidewalls of bulk spacer layer 504b. When planarizing an interlayer dielectric layer (formed over dummy gate structures 212a and 212b) as part of a replacement gate process, contact etch stop layers 602a and 602b may provide a mechanism to stop the planarization operation. Contact etch stop layers 602a and 602b may be formed of a dielectric material having a different etch selectivity than adjacent layers or components. The contact etch stop layers 602a and 602b may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Further, in other embodiments, the contact etch stop layers 602a and 602b may include or may be silicon nitride, silicon carbon nitride, carbon nitride, silicon oxynitride, silicon carbide, or a combination thereof. Deposition (e.g., using deposition tool 102) The contact etch stop layers 602a and 602b may be deposited via a deposition process, such as atomic layer deposition, chemical vapor deposition, or another deposition technique.

[0235] As in Figure 6B As shown in , an interlayer dielectric layer 604a is formed above and / or on the contact etch stop layer 602a (e.g., using deposition tool 102). The interlayer dielectric layer 604a is filled in multiple regions between multiple dummy gate structures 212a above the source / drain region 514. An interlayer dielectric layer 604b is formed above and / or on the contact etch stop layer 602b (e.g., using deposition tool 102). The interlayer dielectric layer 604b is filled in multiple regions between multiple dummy gate structures 212b. The interlayer dielectric layer 604b may correspond to the dielectric layer 310. The interlayer dielectric layers 604a and 604b are formed to allow replacement gate structure processes to be performed in the active device region 204 and the alignment mark region 206, respectively, wherein metal gate structures are formed to replace the dummy gate structures 212a and 212b.

[0236] In some embodiments, the interlayer dielectric layer 604a is formed to a height (or thickness) such that the interlayer dielectric layer 604a covers the dummy gate structure 212a. Figure 6BSimilarly, the interlayer dielectric layer 604b may be formed to a height (or thickness) such that the interlayer dielectric layer 604b covers the dummy gate structure 212b, as shown in FIG. Figure 6B As shown in the embodiment of FIG.

[0237] As in Figure 6C and Fig.6D As shown in , one or more planarization operations (e.g., CMP operations performed using planarization tool 110) are performed to planarize interlayer dielectric layers 604a and 604b and contact etch stop layers 602a and 602b so that the top surfaces of interlayer dielectric layers 604a and 604b are at approximately the same height as the top surfaces of dummy gate structures 212a and 212b, respectively. In this way, one or more planarization operations are performed to expose multiple tops of dummy gate structures 212a and 212b through interlayer dielectric layers 604a and 604b and contact etch stop layers 602a and 602b. This enables dummy gate structures 212a and 212b to be removed via etching.

[0238] As in Figure 6C As shown in , a first planarization operation is performed to planarize interlayer dielectric layers 604a and 604b, and the planarization operation stops on contact etch stop layers 602a and 602b. A planarization tool 110 can be used to planarize interlayer dielectric layers 604a and 604b in the first planarization. As described above, the use of dummy gate structures 212b in alignment mark area 206 can enable gate spacing parameters or design rules for semiconductor device 200 to be met in alignment mark area 206. This can reduce the possibility of depression in interlayer dielectric layer 604b. Depression can be prevented (or the magnitude of depression can be minimized) because when using planarization tool 110 to planarize interlayer dielectric layer 604b in the first planarization operation, the close spacing of multiple dummy gate structures 212b in alignment mark area 206 can prevent or reduce the degree of deformation of the polishing pad of planarization tool 110.

[0239] As in Fig.6D As shown in , after the first planarization operation, a second planarization operation is performed. The second planarization operation may be performed to open the contact etch stop layers 602a and 602b above the dummy gate structures 212a and 212b, respectively, to expose the dummy gate structures 212a and 212b. In some embodiments, different planarization operations are performed for the interlayer dielectric layers 604a and 604b and the contact etch stop layers 602a and 602b, such as in Figure 6C and Fig.6DAs shown in the embodiment of FIG, different polishing pads and / or different planarization parameters can be used for the first planarization operation and the second planarization operation. In other embodiments, different planarization parameters may include different polishing pad hardnesses, different polishing pad rotation speeds, and / or different degrees of down force.

[0240] As in Fig. 6E and Fig. 6F As shown in FIG. 2 , the dummy gate structure 212a is removed from the active device region 204, and the dummy gate structure 212b is removed from the alignment mark region 206. In some embodiments, the removal of the dummy gate structure 212b is omitted, and the dummy gate structure 212b is retained in the alignment mark region 206 for subsequent alignment-based processes. The removal of the dummy gate structure 212a leaves a plurality of openings (or recesses) 606a between the plurality of bulk spacer layers 504a and between the plurality of source / drain regions 514. The removal of the dummy gate structure 212b leaves a plurality of openings (or recesses) 606b between the plurality of bulk spacer layers 504b.

[0241] As in Fig. 6E and Fig. 6F As further shown in FIG. 1 , the dummy gate structures 212 a and 212 b may be removed in multiple etching operations. Fig. 6E As shown in , the removal of the first portion of the dummy gate structures 212a and 212b may be performed in a dry etching operation using the etching tool 108. Fig. 6F As shown in FIG. 1 , removal of the remaining portions of the dummy gate structures 212 a and 212 b may be performed in a wet etching operation using an etching tool 108 .

[0242] As in Figure 6G , the replacement gate operation continues, wherein the deposition tool 102 and / or the plating tool 112 forms a gate structure (e.g., a replacement gate structure) 608a in the opening 606a between the plurality of bulk spacer layers 504a and between the plurality of source / drain regions 514, and forms a gate structure 608b in the opening 606b between the plurality of bulk spacer layers 504b. The gate structures 608a and 608b may each include a metal gate structure, a high dielectric constant gate structure, or other types of gate structures. The gate structure 608a may be referred to as an "active" gate structure because the gate structure 608a is included in a functional transistor in the active device region 204. The gate structure 608b may be referred to as a "non-active" gate structure because the gate structure 608b is not used in an active device of the semiconductor device 200, but is used for alignment purposes.

[0243] As mentioned above, it provides FIG. 6A to FIG. 6GAs an example, other embodiments may differ from the FIG. 6A to FIG. 6G The content described.

[0244] FIG. 7A to FIG. 7D 6 is a schematic diagram of an example implementation of an active gate structure and a non-active gate structure described herein. An "active gate structure" may refer to a gate structure 608a, which is included in the active device region 204 of the semiconductor device 200 described herein. A "non-active gate structure" may refer to a gate structure 608b, which is included in the alignment mark region 206 of the semiconductor device 200 described herein.

[0245] Fig. 7A An example implementation 700 is shown of a gate structure 608a included in the active device region 204 and a gate structure 608b included in the alignment mark region 206. Fig. 7A As shown in , the gate structure 608a and the gate structure 608b may each include a plurality of layers. For example, in other embodiments, the gate structure 608a and the gate structure 608b may each include a metal electrode 702, a glue layer 704 surrounding three sides of the metal electrode 702, a work function metal (WFM) layer 706 (e.g., wherein the glue layer 704 adheres the work function metal layer 706 to the metal electrode 702), a barrier layer 708, a cap layer 710, a high dielectric constant dielectric layer 712, an interfacial layer (IL) 714, and a cap layer 716. The work function metal layer 706 may be included between the glue layer 704 and the barrier layer 708. The barrier layer 708 may be included between the work function metal layer 706 and the cap layer 710. The cap layer 710 may be included between the barrier layer 708 and the high dielectric constant dielectric layer 712. A high-k dielectric layer 712 may be included between the cap layer 710 and the interface layer 714. The interface layer 714 may be included between the gate structure 608a and the fin structure 208a below. The interface layer 714 may be included between the gate structure 608b and the fin structure 208b below. A cap layer 716 may be included on the gate structure 608a, and another cap layer 716 may be included on the gate structure 608b.

[0246] The metal electrode 702 may include tungsten (W) and / or another conductive metal. The glue layer 704 may include titanium nitride (TiN) and / or another adhesion material. The thickness of the glue layer 704 may be included in the range of about 20 angstroms to about 40 angstroms. However, other values ​​for this range are also within the scope of the present disclosure.

[0247] The work function metal layer 706 may include titanium (Ti), aluminum (Al), tantalum (Ta), zirconium (Zr), zinc (Zn), alloys thereof, and / or another material. The thickness of the work function metal layer 706 may be included in the range of about 40 angstroms to about 60 angstroms. However, other values ​​for this range are also within the scope of the present disclosure.

[0248] The barrier layer 708 may include tantalum nitride (TaN) and / or another barrier material. The thickness of the barrier layer 708 may be included in the range of about 5 angstroms to about 20 angstroms. However, other values ​​for this range are also within the scope of the present disclosure.

[0249] The capping layer 710 may include titanium nitride (TiN) and / or another capping layer material. In other embodiments, the high-k dielectric layer 712 may include one or more high-k dielectric materials, such as zirconium oxide (ZrO x , such as ZrO 2 ), aluminum oxide (Al x O y , such as Al 2 O 3 ), silicon nitride (Si x N y , such as Si 3 N 4 ), yttrium oxide (Y x O y , for example, Y 2 O 3 ), lanthanum oxide (La x O y , such as La 2 O 3 ), yttrium titanium oxide (Y x TiO y , for example, Y 2 TiO 5 ), hafnium oxide (HfO x , such as HfO 2 ), and / or tantalum oxide (Ta x O y , for example 2 O 5 The interface layer 714 may include an oxide-containing dielectric material (eg, silicon oxide (SiO x )), nitride-containing dielectric materials (e.g., silicon nitride (Si x N y )), and / or another suitable material. The cap layer 716 may include an oxide-containing dielectric material (eg, silicon oxide (SiO x )), nitride-containing dielectric materials (e.g., silicon nitride (Si x Ny )), and / or another suitable material.

[0250] A combination and / or arrangement of multiple layers for the included gate structure 608a and gate structure 608b in the example implementation 700 may be used, wherein the transistors of the active device region 204 include n-type low threshold voltage transistors (N-LVT) or n-type ultra-low threshold voltage transistors (N-uLVT). This enables full process integration for the formation of the gate structure 608a and gate structure 608b.

[0251] Figure 7B An example implementation 718 of a gate structure 608a included in the active device region 204 and a gate structure 608b included in the alignment mark region 206 is depicted. Figure 7B As shown in FIG. 1 , gate structure 608 a and gate structure 608 b may each include multiple layers similar to those in FIG. Fig. 7A The combination and arrangement of multiple layers 702 to 716 in the embodiment embodiment 700 of the present invention. In the embodiment embodiment 718, the gate structure 608a and the gate structure 608b may each include an additional work function metal layer 720 for further work function tuning. The work function metal layer 720 may be included between the work function metal layer 706 and the barrier layer 708, and may include an oxide and / or nitride of titanium (Ti), aluminum (Al), tantalum (Ta), zirconium (Zr), zinc (Zn), and / or another material. In some embodiments, the thickness of the work function metal layer 720 is included in the range of about 5 angstroms to about 15 angstroms. However, other values ​​for this range are also within the scope of the present disclosure.

[0252] In other embodiments, a combination and / or arrangement of multiple layers for gate structure 608a and gate structure 608b included in embodiment implementation 718 may be used, wherein transistors in active device region 204 include n-type standard threshold voltage transistors (N-SVT), n-type input / output transistors (N-IO), pass-gate (PG) transistors, and / or pull-down (PD) transistors. This enables full process integration of the formation of gate structure 608a and gate structure 608b.

[0253] Figure 7C An example implementation 722 of a gate structure 608a included in the active device region 204 and a gate structure 608b included in the alignment mark region 206 is depicted. Figure 7C As shown in FIG. 1 , gate structure 608 a and gate structure 608 b may each include multiple layers similar to those in FIG. Figure 7B 718. In an example embodiment 722, the gate structure 608a and the gate structure 608b may each include an additional work function metal layer 724 for further work function tuning. The work function metal layer 724 may be included between the work function metal layer 720 and the barrier layer 708. In some embodiments, the thickness of the work function metal layer 724 is included in the range of about 10 angstroms to about 20 angstroms. However, other values ​​for this range are also within the scope of the present disclosure.

[0254] In some embodiments, the work function metal layer 724 may include an oxide and / or nitride of titanium (Ti), aluminum (Al), tantalum (Ta), zirconium (Zr), zinc (Zn), and / or another material. In some embodiments, among other embodiments, the work function metal layer 706, the work function metal layer 720, and the work function metal layer 724 may each include a different material selected from an oxide or nitride of titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), molybdenum (Mo), copper (Cu), zirconium (Zr), zinc (Zn), iron (Fe), and / or tin (Sn).

[0255] In other embodiments, a combination and / or arrangement of multiple layers for gate structure 608a and gate structure 608b included in embodiment implementation 722 may be used, wherein transistors in active device region 204 include p-type standard threshold voltage transistors (P-SVT), p-type input / output transistors (P-IO), and / or pull-down (PD) transistors. This enables full process integration of the formation of gate structure 608a and gate structure 608b.

[0256] Fig.7D An example implementation 726 of a gate structure 608a included in the active device region 204 and a gate structure 608b included in the alignment mark region 206 is depicted. Fig.7D As shown in FIG. 1 , gate structure 608 a and gate structure 608 b may each include multiple layers similar to those in FIG. Figure 7CIn an example embodiment 722, the combination and arrangement of multiple layers 702 to 716, 720, and 724. In an example embodiment 726, the gate structure 608a and the gate structure 608b can each include an additional work function metal layer 728 for further work function tuning. The work function metal layer 728 can be included between the work function metal layer 724 and the barrier layer 708. In some embodiments, the thickness of the work function metal layer 728 is included in the range of about 10 angstroms to about 20 angstroms. However, other values ​​for this range are also within the scope of the present disclosure.

[0257] In some embodiments, the work function metal layer 728 may include an oxide and / or nitride of titanium (Ti), aluminum (Al), tantalum (Ta), zirconium (Zr), zinc (Zn), and / or another material. In some embodiments, among other embodiments, the work function metal layer 706, the work function metal layer 720, the work function metal layer 724, and the work function metal layer 728 may each include a different material selected from an oxide or nitride of titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), molybdenum (Mo), copper (Cu), zirconium (Zr), zinc (Zn), iron (Fe), and / or tin (Sn).

[0258] In other embodiments, a combination and / or arrangement of multiple layers for gate structure 608a and for gate structure 608b included in embodiment 726 may be used, wherein transistors of active device region 204 include p-type low threshold voltage transistors (P-LVT) and / or p-type ultra-low voltage threshold transistors (P-uLVT). This enables full process integration of the formation of gate structure 608a and gate structure 608b.

[0259] As mentioned above, it provides FIG. 7A to FIG. 7D As multiple embodiments. Other embodiments may differ from the FIG. 7A to FIG. 7D The content described.

[0260] FIG. 8A to FIG. 8C 2 is a schematic diagram of an embodiment area of ​​a semiconductor device 800 described herein. The semiconductor device 800 may include a semiconductor die, a semiconductor wafer, and / or another type of semiconductor device fabricated on a substrate 202 .

[0261] As in Fig. 8AAs shown in , semiconductor device 800 may be similar to semiconductor device 200 and may include one or more active device regions 204 and one or more alignment mark regions 206. Fig. 8A The layout, shape, number, and / or arrangement of the active device area 204 and the alignment mark area 206 shown in the figure is one embodiment, and other layouts, shapes, numbers, and / or arrangements are also within the scope of the present disclosure.

[0262] As in Figure 8B As shown in FIG. 8 , the active device region 204 of the semiconductor device 800 may include an arrangement of multiple components similar to the active device region 204 of the semiconductor device 200 , including a substrate 202, a fin structure 208 a (e.g., an active fin structure), a shallow trench isolation region 210 a, and a dummy gate structure 212 a. The dummy gate structure 212 a may be replaced with one or more metal gate structures (e.g., gate structure 608 a) described herein.

[0263] As in Figure 8B As further shown in FIG. 8 , the alignment mark region 206 of the semiconductor device 800 may include an arrangement of multiple components similar to the alignment mark region 206 of the semiconductor device 200 , including the substrate 202 , the shallow trench isolation region 210 b , and the dummy gate structure 212 b . The dummy gate structure 212 b may be replaced with one or more metal gate structures (e.g., gate structure 608 b ) described herein.

[0264] As in Figure 8B and Figure 8C As shown in FIG. 8 , the fin structure 208 b (e.g., a non-active fin structure) is omitted from the alignment mark region 206 of the semiconductor device 800, and the dummy gate structure 212 b (and subsequent gate structure 608 b) are formed and included directly on the shallow trench isolation region 210 b. This can reduce the process complexity for the alignment mark region 206. In this way, the pattern 302 in the dummy gate structure 212 a is formed directly on the shallow trench isolation region 210 b, as shown in FIG. Figure 8C as shown in .

[0265] As mentioned above, it provides FIG. 8A to FIG. 8C As an example, other embodiments may be different from the FIG. 8A to FIG. 8C The content described.

[0266] 9A to 9C 2 is a schematic diagram of an embodiment area of ​​a semiconductor device 900 described herein. The semiconductor device 900 may include a semiconductor die, a semiconductor wafer, and / or another type of semiconductor device fabricated on a substrate 202 .

[0267] As in Fig. 9AAs shown in , semiconductor device 900 may be similar to semiconductor device 200 and may include one or more active device regions 204 and one or more alignment mark regions 206. Fig. 9A The layout, shape, number, and / or arrangement of the active device area 204 and the alignment mark area 206 shown in the figure is one embodiment, and other layouts, shapes, numbers, and / or arrangements are also within the scope of the present disclosure.

[0268] As in Fig. 9A As further shown in FIG. 1 , the semiconductor device 900 may include a plurality of alignment mark regions 206, including an alignment mark region 206a and an alignment mark region 206b. In the top-down layout of the semiconductor device 900, the alignment mark region 206b may be adjacent to the alignment mark region 206a, may be adjacent to a subset of one or more active device regions 204, and / or may be located at another location in the top-down layout of the semiconductor device 900.

[0269] As in Fig. 9B As shown in , the alignment mark region 206a of the semiconductor device 900 may include a similar arrangement of multiple components of the alignment mark region 206 of the semiconductor device 200, including the substrate 202, the fin structure 208b (e.g., a non-active fin structure), the shallow trench isolation region 210b, and the dummy gate structure 212b. The dummy gate structure 212b may be replaced with one or more metal gate structures (e.g., gate structure 608a) described herein. Therefore, the alignment mark region 206a may be a polysilicon gate-based alignment mark region or a dummy gate-based alignment mark region.

[0270] As in Fig. 9B As further shown in FIG. 1 , the alignment mark region 206 b of the semiconductor device 900 may include an arrangement of multiple components similar to the alignment mark region 206 a, including the substrate 202, the fin structure 208 c (e.g., a non-active fin structure), and the shallow trench isolation region 210 c. However, the dummy gate structure may be omitted from the alignment mark region 206 b. Therefore, the alignment mark region 206 b may be a fin-based alignment mark region or an operation domain (OD)-based alignment mark region.

[0271] As in Fig. 9C As shown in , the alignment mark region 206a may include a pattern 302 (e.g., a polysilicon gate-based alignment mark pattern or a dummy gate-based alignment mark pattern). The pattern 302 includes a plurality of dummy gate structures 212b (or gate structures 608b) above the fin structure 208b (e.g., a non-active fin structure), wherein the plurality of dummy gate structures 212b are arranged in a plurality of diagonal columns 304, 306 separated by a plurality of gaps 308.

[0272] As in Fig. 9C As further shown in FIG. 3 , the alignment mark region 206 b may include a pattern 902 (e.g., a fin-based alignment mark pattern or an operational domain-based alignment mark pattern). The pattern 902 includes a plurality of fin structures 208 c (e.g., non-active fin structures) above the shallow trench isolation region 210 c, wherein the plurality of fin structures 208 c are arranged in a plurality of diagonal columns 904, columns 906 separated by a plurality of gaps 908. The plurality of fin structures 208 c may also extend in the same direction as the fin structures 208 b and may be formed in the same set of one or more semiconductor processing operations as the fin structures 208 a and the fin structures 208 b. Thus, the direction of the pattern 902 may be rotated approximately 90 degrees relative to the pattern 302 because the pattern 902 is formed in the plurality of fin structures 208 c, relative to the pattern 302 formed in the dummy gate structure 212 b (or gate structure 608 b).

[0273] Including both pattern 302 (e.g., polysilicon gate-based alignment mark pattern or dummy gate-based alignment mark pattern) and pattern 902 (e.g., fin-based alignment mark pattern or OD-based alignment mark pattern) allows pattern 302 and pattern 902 to be used for alignment of substrate 202 for different stages of fabrication of semiconductor device 900 on substrate 202. For example, pattern 902 may be formed as a combination of FIG. 4A to FIG. 4D The fin formation process described above may be part of (or after) the fin formation process and may be used to align the substrate 202 for semiconductor processes performed to form the dummy gate structures 212a and 212b, such as in combination with FIG. 5A to FIG. 5F After the formation of the dummy gate structures 212a and 212b, the pattern 302 may be used for alignment of the substrate 202 in subsequent semiconductor processes.

[0274] As mentioned above, it provides 9A to 9C As an embodiment. Other embodiments may be related to 9A to 9C The content described is different.

[0275] Fig. 10A and Fig. 10B 2 is a schematic diagram of an embodiment area of ​​a semiconductor device 1000 described herein. The semiconductor device 1000 may include a semiconductor die, a semiconductor wafer, and / or another type of semiconductor device fabricated on a substrate 202 .

[0276] As in Fig. 10AAs shown in , semiconductor device 1000 may be similar to semiconductor device 900 and may include one or more active device regions 204 and one or more alignment mark regions 206 (eg, alignment mark region 206a, alignment mark region 206b). Fig. 10A The layouts, shapes, quantities, and / or arrangements of the active device regions 204 and the alignment mark regions 206 illustrated in the drawings are examples, and other layouts, shapes, quantities, and / or arrangements are also within the scope of the present disclosure.

[0277] As in Fig. 10A and Fig. 10B As further shown in the semiconductor device 1000 in the top-down layout of the semiconductor device 1000, the alignment mark area 206a may be included around the periphery of the alignment mark area 206b. The alignment mark area 206b may include a dimension D7 (corresponding to the width of the alignment mark area 206b) and a dimension D8 (corresponding to the length of the alignment mark area 206b). The alignment mark area 206a may include a dimension D9 (corresponding to the width of the alignment mark area 206a) and a dimension D10 (corresponding to the length of the alignment mark area 206b). In some embodiments, the dimension D7 is included in the range of about 100 microns to about 300 microns. However, other values ​​for this range are also within the scope of the present disclosure. In some embodiments, the dimension D8 is included in the range of about 100 microns to about 300 microns. However, other values ​​for this range are also within the scope of the present disclosure. In some embodiments, the ratio of the dimensions D7 to D9 (D7:D9) is included in the range of about 1:1.1 to about 1:1.5. However, other values ​​for this range are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D8 to D10 (D8:D10) is included in the range of about 1:1.1 to about 1:1.5. However, other values ​​for this range are also within the scope of the present disclosure.

[0278] Including both the alignment mark region 206a (e.g., a polysilicon gate-based alignment mark or a dummy gate-based alignment mark) and the alignment mark region 206b (e.g., a fin-based alignment mark or an operational domain-based alignment mark) allows the alignment mark region 206a and the alignment mark region 206b to be used for aligning the substrate 202 at different stages of manufacturing the semiconductor device 1000 on the substrate 202. For example, the alignment mark region 206b may be formed as a combination of FIG. 4A to FIG. 4D The fin formation process described above may be part of (or after) the fin formation process and may be used to align the substrate 202 for semiconductor processes performed to form the dummy gate structures 212a and 212b, such as in combination with FIG. 5A to FIG. 5FAfter the formation of the dummy gate structures 212a and 212b, the alignment mark region 206a may be used for alignment of the substrate 202 in subsequent semiconductor processes.

[0279] As mentioned above, it provides Fig. 10A and Fig. 10B As an example, other embodiments may differ from the Fig. 10A and Fig. 10B The content described.

[0280] Fig.11 1 is a schematic diagram of an embodiment of a lithography system 1100 described herein. The lithography system 1100 includes an extreme ultraviolet lithography system or another type of lithography system configured to transfer a pattern to a substrate 202 using mirror-based optics. The lithography system 1100 includes an embodiment of an exposure tool 1104. The lithography system 1100 may be configured for use in a semiconductor processing environment, for example in conjunction with Figure 1 An embodiment environment 100 is described.

[0281] As in Fig.11 As shown in , lithography system 1100 includes radiation source 1102 and exposure tool 1104. Radiation source 1102 (e.g., an EUV radiation source or another type of radiation source) is configured to generate radiation 1106, such as EUV radiation and / or another type of electromagnetic radiation (e.g., light). Exposure tool 1104 (e.g., an EUV scanner or another type of exposure tool) is configured to focus radiation 1106 onto a reflective mask 1108 (or optical mask) so that a pattern is transferred from mask 1108 to a photoresist layer 1110 above substrate 202 using radiation 1106.

[0282] The radiation source 1102 includes a container 1112 and a collector 1114 in the container 1112. The collector 1114 includes a curved mirror configured to collect radiation 1106 generated by the radiation source 1102 and focus the radiation 1106 toward an intermediate focal point 1116. The radiation 1106 is generated from a plasma generated from droplets 1118 (e.g., tin (Sn) droplets or another type of droplet) exposed to a laser beam 1120. The droplets 1118 are provided across the front of the collector 1114 via a droplet generator (DG) head 1122. The droplet generator head 1122 is pressurized to provide a fine and controlled output of the droplets 1118.

[0283] Laser sources, such as pulsed carbon dioxide (CO 2) laser, generating a laser beam 1120. The laser beam 1120 is provided (e.g., via a beam delivery system to a focusing lens) so that the laser beam 1120 is focused through a window 1124 of the collector 1114. The laser beam 1120 is focused onto droplets 1118 that generate plasma. The plasma generates plasma emissions, some of which are radiation 1106. The laser beam 1120 pulse time is synchronized with the flow of droplets 1118 from the droplet generator head 1122.

[0284] The exposure tool 1104 includes an illuminator 1126 and a projection optics box (POB) 1128. The illuminator 1126 includes a plurality of mirrors configured to focus and / or direct radiation 1106 onto a mask 1108 so as to illuminate a pattern on the mask 1108. The plurality of mirrors include, for example, a mirror 1130a and a mirror 1130b. The mirror 1130a includes a field facet mirror (FFM) or another type of mirror including a plurality of field facets. The mirror 1130b includes a pupil facet mirror (PFM) or another type of mirror also including a plurality of pupil facets. The facets of the mirrors 1130a and 1130b are arranged to focus, polarize, and / or otherwise adjust the radiation 1106 from the radiation source 1102 to increase the uniformity of the radiation 1106 and / or increase a particular type of radiation component (e.g., transverse electric (TE) polarized radiation, transverse magnetic (TM) polarized radiation). Another mirror 1132 (e.g., a relay mirror) is included to direct the radiation 1106 from the illuminator 1126 onto the mask 1108.

[0285] The projection optics box 1128 includes a plurality of mirrors configured to project radiation 1106 onto a photoresist layer 1110 on the substrate 202 after the radiation 1106 is modified based on the pattern of the mask 1108. The plurality of reflective mirrors include, for example, mirrors 1134a to 1134f. In some embodiments, the plurality of mirrors 1134a to 1134f are configured to focus or reduce the radiation 1106 into an exposure field, which may include one or more die regions on the substrate 202.

[0286] The exposure tool 1104 includes a wafer stage 1136 (e.g., a substrate stage) configured to support the substrate 202. In addition, the wafer stage 1136 is configured to move (or step) the substrate 202 through a plurality of exposure fields as the radiation 1106 transfers a pattern from the mask 1108 to the photoresist layer 1110 on the substrate 202. The wafer stage 1136 is included in a bottom module 1138 of the exposure tool 1104. The bottom module 1138 includes a removable subsystem of the exposure tool 1104. The bottom module 1138 can be slid out of the exposure tool 104 and / or removed from the exposure tool 1104 to enable cleaning and inspection of the wafer stage 1136 and / or various components of the wafer stage 1136. The bottom module 1138 isolates the wafer stage 1136 from other areas in the exposure tool 1104 to reduce and / or minimize contamination of the substrate 202. Additionally, the base module 1138 can provide physical isolation for the wafer stage 1136 by reducing the transfer of vibrations (e.g., vibrations in the semiconductor processing environment in which the lithography system 1100 is located, vibrations in the lithography system 1100 during operation of the lithography system 1100) to the wafer stage 1136 and, therefore, to the substrate 202. This reduces movement and / or disturbance of the substrate 202, which reduces the likelihood that vibrations may cause pattern misalignment.

[0287] Exposure tool 1104 also includes a reticle stage 1140 configured to support and / or secure reticle 1108. Furthermore, reticle stage 1140 is configured to move or slide the reticle through radiation 1106 such that reticle 1108 is scanned by radiation 1106. In this manner, a pattern that is larger than the field or beam of radiation 1106 can be transferred to photoresist layer 1110 on substrate 202.

[0288] The lithography system 1100 includes a laser source 1142. The laser source 1142 is configured to generate a laser beam 1120. The laser source 1142 may include a CO based 2 laser source or another type of laser source. 2 The wavelength of the laser beam generated by the laser source is in the infrared (IR) region, and the laser beam can be highly absorbed by tin, which makes the CO-based 2 The laser source can achieve higher power and energy for exciting the tin-based plasma. In some embodiments, the laser beam 1120 includes multiple types of laser beams generated by the laser source 1142 using a multi-pulse technique (or a multi-stage excitation technique), wherein the laser source 1142 generates a pre-pulse laser beam and a main pulse laser beam to achieve greater heating efficiency of the tin (Sn)-based plasma, thereby improving the conversion efficiency.

[0289] In an embodiment exposure operation (e.g., extreme ultraviolet exposure operation), a droplet generator head 1122 provides a stream of droplets 1118 across the front of the collector 1114. The laser beam 1120 contacts the droplets 1118, which results in the generation of plasma. The laser source 1142 generates and provides a pre-pulse laser beam toward a target material droplet in the stream of droplets 1118, which is absorbed by the target material droplet. This transforms the target material droplet into a disk or mist. Subsequently, the laser source 1142 provides a main pulse laser beam with high intensity and energy toward the disk-shaped target material or the target material mist. Here, the atoms of the target material are neutralized and ions are generated by heat flux and shock waves. The main pulse laser beam excites the ions to a higher charge state, which causes the ions to emit radiation 1106 (e.g., EUV light).

[0290] Radiation 1106 is collected by collector 1114 and directed out of container 1112 and into exposure tool 1104 toward mirror 1130a of illuminator 1126. Mirror 1130a reflects radiation 1106 onto mirror 1130b, which reflects radiation 1106 onto mirror 1132 toward reticle 1108. Radiation 1106 is modified via a pattern in reticle 1108. In other words, radiation 1106 is reflected from reticle 1108 based on the pattern of reticle 1108. Reflective reticle 1108 directs radiation 1106 toward mirror 1134a in projection optics box 1128, which reflects radiation 1106 onto mirror 1134b. Radiation 1106 continues to be reflected and reduced by mirrors 1134c through 1134f in projection optics box 1128. The mirror 1134f reflects the radiation 1106 onto the photoresist layer 1110 on the substrate 202, so that the pattern of the mask 1108 is transferred to the photoresist layer 1110 on the substrate 202. The exposure operation described above is an embodiment, and the lithography system 1100 can be operated according to other extreme ultraviolet technologies and radiation paths, including more mirrors, fewer mirrors, and / or mirrors in different configurations.

[0291] As in Fig.11As further shown in FIG. 1 , a pre-alignment unit 1144 may be included in the bottom module 1138. The pre-alignment unit 1144 (also referred to as a temperature stabilizing unit (TSU)) may be configured to perform a rough alignment of the substrate 202 prior to an exposure operation. The pre-alignment unit 1144 may also be used to perform measurements and / or determine an OVL compensation value for an exposure operation. After the rough alignment, the alignment mark area 206 (e.g., a polysilicon gate-based alignment mark or a dummy gate-based alignment mark) on the substrate 202 may be used to perform a fine wafer alignment of the substrate 202 for an exposure operation. In some embodiments, the OVL compensation value may be used during the fine wafer alignment of the substrate 202.

[0292] As mentioned above, it provides Fig.11 As an example, other embodiments may be related to Fig.11 The content described is different.

[0293] Fig.12 is a schematic diagram of an example implementation 1200 of performing substrate alignment as described herein. Fig.12 As shown in , the substrate 202 may include a plurality of semiconductor devices 1202 in the process of being manufactured on the substrate 202. The semiconductor devices 1202 may include the semiconductor device 200, the semiconductor device 800, the semiconductor device 900, the semiconductor device 1000, and / or other semiconductor devices described herein (including polysilicon gate-based alignment marks or dummy gate-based alignment marks). The substrate 202 may also include a notch 1204 at the periphery of the substrate 202.

[0294] A coarse wafer alignment (COWA) operation 1206 may be performed in which the substrate 202 is placed on the pre-alignment unit 1144 of the lithography system 1100 and rotated in one or more directions to align the notch 1204 of the substrate 202 with a reference position on the pre-alignment unit 1144. At least two positions may be selected to determine a reference origin (e.g., Cartesian coordinates, polar coordinates) of a coordinate system for aligning the notch 1204 with the reference position.

[0295] After the rough wafer alignment operation 1206, a fine wafer alignment (FIWA) operation 1208 may be performed, in which a plurality of laser beams 1210 are used to scan the alignment mark area 206 on the substrate 202. A green laser beam 1210a and a red laser beam 1210b may be directed onto the alignment mark area 206, wherein the pattern 302 in the alignment mark area scatters the green laser beam 1210a and the red laser beam 1210b. The reflection and diffraction levels of the reflected light 1212 from the green laser beam 1210a and the red laser beam 1210b may be measured to determine the alignment of the substrate 202 in the fine wafer alignment operation 1208 and to fine-tune the orientation of the substrate on the wafer stage 1136.

[0296] As mentioned above, it provides Fig.12 As an example, other embodiments may be related to Fig.12 The content described is different.

[0297] Fig.13 1 is a schematic diagram of example components of apparatus 1300 associated with a semiconductor device including alignment marks. In some embodiments, one or more of the plurality of semiconductor processing tools 102-112, the wafer / die transport tool 114, and / or the lithography system 1100 may include one or more apparatuses 1300 and / or one or more components of apparatuses 1300. Fig.13 As shown in , device 1300 may include a bus 1310 , a processor 1320 , a memory 1330 , an input component 1340 , an output component 1350 , and / or a communication component 1360 .

[0298] The bus 1310 may include one or more components that enable wired and / or wireless communication between the various components of the device 1300. The bus 1310 may include one or more components that enable wired and / or wireless communication between the various components of the device 1300. Fig.13 Two or more components of a processor 1320 are coupled together, for example, via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 1310 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 1320 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 1320 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1320 may include one or more processors that are programmable to perform one or more operations or processes described elsewhere herein.

[0299] Memory 1330 may include volatile and / or non-volatile memory. For example, memory 1330 may include random access memory (RAM), read only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1330 may include internal memory (e.g., random access memory, read only memory, or hard drive), and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1330 may be a non-transitory computer-readable medium. Memory 1330 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of device 1300. In some embodiments, memory 1330 may include one or more memories that are coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1320), such as via bus 1310. The communicative coupling between processor 1320 and memory 1330 may enable processor 1320 to read and / or process information stored in memory 1330 and / or store information in memory 1330 .

[0300] Input component 1340 may enable device 1300 to receive input, such as user input and / or sensed input. For example, input component 1340 may include a touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, global positioning system sensor, accelerometer, gyroscope, and / or actuator. Output component 1350 may enable device 1300 to provide output, such as via a display, speaker, and / or light emitting diode. Communication component 1360 may enable device 1300 to communicate with other devices via wired connection and / or wireless connection. For example, communication component 1360 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0301] Device 1300 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1330) may store a set of multiple instructions (e.g., one or more instructions or program codes) for implementation via processor 1320. Processor 1320 may implement multiple instructions of the set to perform one or more operations or processes described herein. In some embodiments, the implementation of multiple instructions of the set via one or more processors 1320 causes one or more processors 1320 and / or device 1300 to perform one or more operations or processes described herein. In some embodiments, hard-wired circuits may be used to replace multiple instructions or to be combined with multiple instructions to perform one or more operations or processes described herein. Additionally or alternatively, processor 1320 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0302] Provided in Fig.13 The number and arrangement of components shown in FIG. are provided as an example. Fig.13 , device 1300 may include additional components, fewer components, different components, or components in a different arrangement. Additionally or alternatively, a group of multiple components (e.g., one or more components) of device 1300 may perform one or more functions described as being performed by another group of multiple components of device 1300.

[0303] Fig.14 is a flow chart of an embodiment process 1400 associated with forming a semiconductor device including alignment marks as described herein. In some implementations, performing Fig.14 The one or more process blocks of use one or more semiconductor processing tools (e.g., one or more of the plurality of semiconductor processing tools 102-112). Additionally or alternatively, performing Fig.14 One or more process blocks may be implemented via one or more components of the device 1300 , such as a processor 1320 , a memory 1330 , an input component 1340 , an output component 1350 , and / or a communication component 1360 .

[0304] As in Fig.14 As shown in , process 1400 may include forming a plurality of active fin structures above a substrate in an active device region of a semiconductor device (block 1410). For example, one or more of semiconductor processing tools 102-112 may be used to form a plurality of active fin structures (e.g., fin structures 208a) above a substrate 202 in an active device region 204 of a semiconductor device (e.g., semiconductor devices 200, 800, 900, and / or 1000), as described herein.

[0305] As in Fig.14 As further shown in the process 1400, the process 1400 may include forming a shallow trench isolation region above the substrate (block 1420). For example, one or more of the semiconductor processing tools 102-112 may be used to form a shallow trench isolation region (e.g., shallow trench isolation layer 210) above the substrate, as described herein. In some embodiments, a first portion of the shallow trench isolation region (e.g., shallow trench isolation region 210a) is formed in the active device region between the plurality of active fin structures. In some embodiments, a second portion of the shallow trench isolation region (e.g., shallow trench isolation region 210b) is formed in an alignment mark region (e.g., alignment mark region 206, alignment mark region 206a) of the semiconductor device above the substrate.

[0306] As in Fig.14 As further shown in the process 1400, the process 1400 may include forming a first plurality of dummy gate structures in the active device region above a first portion of the shallow trench isolation region (block 1430). For example, one or more of the semiconductor processing tools 102 to 112 may be used to form the first plurality of dummy gate structures 212a in the active device region above a first portion of the shallow trench isolation region, as described herein. In some embodiments, the first plurality of dummy gate structures surround the plurality of active fin structures on at least three sides of the plurality of active fin structures.

[0307] As in Fig.14 As further shown in the process 1400, the process 1400 may include forming a second plurality of dummy gate structures (212b) in the alignment mark region at a second portion above the shallow trench isolation region (block 1440). For example, one or more of the semiconductor processing tools 102-112 may be used to form the second plurality of dummy gate structures 212b in the alignment mark region at a second portion above the shallow trench isolation region, as described herein.

[0308] As in Fig.14 As further shown in FIG. 1 , process 1400 may include etching a second plurality of dummy gate structures to form an alignment mark pattern in the alignment mark region (block 1450). For example, one or more of semiconductor processing tools 102 to 112 may be used to etch a second plurality of dummy gate structures to form an alignment mark pattern (e.g., pattern 302) in the alignment mark region, as described herein.

[0309] Process 1400 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0310] In a first embodiment, process 1400 includes forming a plurality of non-active fin structures (e.g., fin structure 208b) above the substrate in the alignment mark area, wherein a second portion of the shallow trench isolation region is formed between the plurality of non-active fin structures, and wherein forming a second plurality of dummy gate structures includes forming a second plurality of dummy gate structures such that the second plurality of dummy gate structures surround the plurality of non-active fin structures on at least three sides of the plurality of non-active fin structures.

[0311] In the second embodiment, alone or in combination with the first embodiment, the process 1400 includes forming a plurality of source / drain regions 514 on opposite sides of the first plurality of dummy gate structures while the second plurality of dummy gate structures are covered by the mask layer 510 .

[0312] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 1400 includes forming a contact etch stop layer (e.g., contact etch stop layer 602a, contact etch stop layer 602b) on the first plurality of dummy gate structures and the second plurality of dummy gate structures, forming an interlayer dielectric layer (e.g., interlayer dielectric layer 604a, interlayer dielectric layer 604b) on the contact etch stop layer, performing a plurality of planarization operations to remove the contact etch stop layer and the interlayer dielectric layer from the top of the first plurality of dummy gate structures and the top of the second plurality of dummy gate structures, and A first plurality of dummy gate structures and a second plurality of dummy gate structures are exposed through a contact etch stop layer and an interlayer dielectric layer, the first plurality of dummy gate structures and the second plurality of dummy gate structures are removed after a plurality of planarization operations, a plurality of active metal gate structures (e.g., gate structure 608a) are formed in a first recess (e.g., recess 606a) formed by the removal of the first plurality of dummy gate structures, and a plurality of inactive metal gate structures (e.g., gate structure 608b) are formed in a second recess (e.g., recess 606a) formed by the removal of the second plurality of dummy gate structures.

[0313] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the plurality of non-active metal gate structures each include a conductive structure (e.g., a metal electrode 702), a work function metal layer (e.g., a work function metal layer 706), an adhesion layer (e.g., a glue layer 704) between the conductive structure and the work function metal layer, a high dielectric constant dielectric layer (e.g., a high dielectric constant dielectric layer 712) below the work function metal layer, and an interface layer (e.g., an interface layer 714) below the high dielectric constant dielectric layer.

[0314] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the plurality of non-active metal gate structures each include a conductive structure (e.g., metal electrode 702), a plurality of work function metal layers (e.g., work function metal layers 706, 720, 724, and / or 728), an adhesion layer (e.g., glue layer 704) between the conductive structure and the plurality of work function metal layers, a high dielectric constant dielectric layer (e.g., high dielectric constant dielectric layer 712) below the plurality of work function metal layers, and an interface layer (e.g., interface layer 714) below the high dielectric constant dielectric layer.

[0315] In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, etching a second plurality of dummy gate structures to form an alignment mark pattern in the alignment mark region includes etching a second plurality of dummy gate structures such that the alignment mark pattern includes a plurality of approximately V-shaped gaps (e.g., gaps 308) between a plurality of columns (e.g., column 304, column 306) of the second plurality of dummy gate structures.

[0316] although Fig.14 Several example blocks of process 1400 are shown, but in some embodiments, the Fig.14 , process 1400 may include additional blocks, fewer blocks, different blocks, or blocks in a different arrangement. Additionally or alternatively, two or more blocks of process 1400 may be performed in parallel.

[0317] Fig.15 is a flow chart of an embodiment process 1500 associated with aligning a semiconductor device using the alignment marks described herein. Fig.15 In one or more process blocks, a lithography system (e.g., lithography system 1100) is used. Additionally or alternatively, performing Fig.15 One or more process blocks may be implemented via one or more components of the device 1300 , such as a processor 1320 , a memory 1330 , an input component 1340 , an output component 1350 , and / or a communication component 1360 .

[0318] As in Fig.15 As shown in FIG. 1 , process 1500 may include receiving a substrate having a photoresist layer in an exposure tool (block 1510 ). For example, lithography system 1100 may be used to receive substrate 202 having photoresist layer 1110 in exposure tool 1104 as described herein.

[0319] As in Fig.15As further shown in FIG. 1 , process 1500 may include directing EUV radiation from a radiation source to the photoresist layer to form a patterned photoresist layer in an exposure operation (block 1520). For example, lithography system 1100 may be used to direct EUV radiation from radiation source 1102 to photoresist layer 1110 to form a patterned photoresist layer in an exposure operation, as described herein. In some embodiments, a polysilicon gate-based alignment mark pattern (e.g., pattern 302) in a polysilicon gate-based alignment mark region (e.g., alignment mark region 206, alignment mark region 206a) is used to align substrate 202 for this exposure operation.

[0320] Process 1500 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0321] In a first embodiment, the exposure operation includes a second exposure operation, and process 1500 includes directing extreme ultraviolet radiation from radiation source 1102 to another photoresist layer 1110 to form another patterned photoresist layer in a first exposure operation performed prior to the second exposure operation, wherein a fin-based alignment mark pattern (e.g., pattern 902) in a fin-based alignment mark area (e.g., alignment mark area 206b) is used to align substrate 202 for the first exposure operation.

[0322] In the second embodiment, either alone or in combination with the first embodiment, the fin-based alignment mark region and the polysilicon gate-based alignment mark region are located in different regions of the substrate 202 .

[0323] In a third embodiment, alone or in combination with one or more of the first and second embodiments, the polysilicon gate based alignment mark area is located around the perimeter of the fin based alignment mark area.

[0324] although Fig.15 1500 is shown as an example block, but in some embodiments, process 1500 includes Fig.15 More blocks, fewer blocks, different blocks, or different arrangements of blocks than those shown. Additionally or alternatively, two or more blocks of process 1500 may be performed in parallel.

[0325] In this way, a gate-based alignment pattern can be included in an alignment mark region of a semiconductor device manufactured on a substrate. The alignment mark region can include a plurality of gate structures (e.g., dummy gate structures, polysilicon gate structures, metal gate structures) that are etched to form a gate-based alignment pattern. The use of a gate-based alignment pattern can reduce and / or prevent the possibility that the gate-based alignment pattern is obscured or covered by residual material byproducts from one or more semiconductor processing operations that are performed to form various layers and / or structures of a semiconductor device. For example, a gate-based alignment pattern can enable gate spacing parameters or design rules for semiconductor devices to be met in the alignment mark region. This can reduce the possibility of depression in a dielectric layer higher than a gate structure in the alignment mark region. Depression can be prevented (or the extent of depression can be minimized) because the close spacing of the gate structures in the alignment mark region can prevent or reduce the extent of deformation of the polishing pad when the dielectric layer is planarized (e.g., as part of a replacement gate process). Reducing or preventing the degree of recess in the dielectric layer can reduce and / or prevent the likelihood of residual metal material and / or other materials remaining above the dielectric layer in the alignment mark region that is deposited as part of a replacement gate process to form a metal gate structure of a semiconductor device. Accordingly, the gate-based alignment pattern of the alignment mark region can reduce and / or prevent the likelihood of residual metal material and / or other materials shielding or blocking the pattern in the alignment mark region.

[0326] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes one or more device regions, the device regions including a plurality of active transistor structures. The semiconductor device includes an alignment mark adjacent to at least a subset of the one or more device regions, including a plurality of inactive gate structures arranged in a pattern.

[0327] In some embodiments, in a semiconductor device, the pattern includes: a plurality of columns of the plurality of inactive gate structures, wherein the plurality of columns are separated by a plurality of gaps between the plurality of columns.

[0328] In some embodiments, in the semiconductor device, the alignment mark further includes: a plurality of inactive fin structures, wherein the plurality of inactive gate structures surround the plurality of inactive fin structures on at least three sides of the plurality of inactive fin structures.

[0329] In some embodiments, in a semiconductor device, the plurality of inactive fin structures extend in a first direction in the semiconductor device; and wherein the plurality of inactive gate structures extend in a second direction in the semiconductor device, the second direction being approximately perpendicular to the first direction.

[0330] In some embodiments, in a semiconductor device, the pattern includes: a plurality of columns of the plurality of inactive gate structures, wherein the plurality of columns extend in a direction that is not perpendicular to a direction in which the plurality of inactive fin structures extend.

[0331] In some embodiments, in a semiconductor device, the multiple active transistor structures include multiple active gate structures; and wherein a spacing between two or more of the multiple inactive gate structures and a spacing between two or more of the multiple active gate structures are approximately the same spacing.

[0332] In some embodiments, in a semiconductor device, the alignment mark further comprises: a shallow trench isolation (STI) region above a substrate of the semiconductor device, wherein the plurality of inactive gate structures are included on the shallow trench isolation region.

[0333] In some embodiments, in a semiconductor device, the alignment mark includes a first alignment mark; wherein the semiconductor device also includes a second alignment mark, the second alignment mark comprising a plurality of non-active fin structures arranged in another pattern; and wherein the second alignment mark is adjacent to at least another subset of the one or more device regions.

[0334] In some embodiments, in a semiconductor device, the pattern includes a first pattern; wherein the alignment mark further includes a plurality of inactive fin structures arranged in a second pattern; and wherein the first pattern is located around a perimeter of the second pattern.

[0335] As described in more detail above, some embodiments described herein provide a method. The method includes forming a plurality of active fin structures above a substrate in an active device region of a semiconductor device. The method includes forming a shallow trench isolation region above the substrate, wherein a first portion of the shallow trench isolation region is formed in the active device region between the plurality of active fin structures, and wherein a second portion of the shallow trench isolation region is formed in an alignment mark region of the semiconductor device above the substrate. The method includes forming a first plurality of dummy gate structures at a first portion above the shallow trench isolation region in the active device region, wherein the first plurality of dummy gate structures surround the plurality of active fin structures on at least three sides of the plurality of active fin structures. The method includes forming a second plurality of dummy gate structures at a second portion above the shallow trench isolation region in the alignment mark region. The method includes etching the second plurality of dummy gate structures to form an alignment mark pattern in the alignment mark region.

[0336] In some embodiments, the method of forming a semiconductor device further includes: forming a plurality of non-active fin structures in the alignment mark area at a position higher than the substrate, wherein the second portion of the shallow trench isolation area is formed between the plurality of non-active fin structures, and wherein forming the second plurality of dummy gate structures includes: forming the second plurality of dummy gate structures so that the second plurality of dummy gate structures surround the plurality of non-active fin structures on at least three sides of the plurality of non-active fin structures.

[0337] In some embodiments, the method of forming a semiconductor device further includes: forming a plurality of source / drain regions on opposite sides of the first plurality of dummy gate structures, while the second plurality of dummy gate structures are covered by a mask layer.

[0338] In some embodiments, the method of forming a semiconductor device further includes: forming a contact etch stop layer (CESL) on the first plurality of dummy gate structures and on the second plurality of dummy gate structures; forming an interlayer dielectric (ILD) layer on the contact etch stop layer; performing multiple planarization operations to remove the contact etch stop layer and the interlayer dielectric layer from the top of the first plurality of dummy gate structures and the top of the second plurality of dummy gate structures to expose the first plurality of dummy gate structures and the second plurality of dummy gate structures through the contact etch stop layer and the interlayer dielectric layer; after the multiple planarization operations, removing the first plurality of dummy gate structures and the second plurality of dummy gate structures; forming a plurality of active metal gate structures in a plurality of first recesses formed by the removal of the first plurality of dummy gate structures; and forming a plurality of non-active metal gate structures in a plurality of second recesses formed by the removal of the second plurality of dummy gate structures.

[0339] In some embodiments, in a method of forming a semiconductor device, each of the plurality of non-active metal gate structures comprises: a conductive structure, a work function metal layer, an adhesion layer, a high dielectric constant (high-k) dielectric layer, and an interface layer. The adhesion layer is between the conductive structure and the work function metal layer. The high dielectric constant (high-k) dielectric layer is below the work function metal layer. The interface layer is below the high dielectric constant dielectric layer.

[0340] In some embodiments, in a method of forming a semiconductor device, each of the plurality of non-active metal gate structures comprises: a conductive structure, a plurality of work function metal layers, an adhesion layer, a high dielectric constant (high-k) dielectric layer, and an interface layer. The adhesion layer is between the conductive structure and the plurality of work function metal layers. The high dielectric constant (high-k) dielectric layer is below the plurality of work function metal layers. The interface layer is below the high dielectric constant dielectric layer.

[0341] In some embodiments, in a method of forming a semiconductor device, etching the second plurality of dummy gate structures to form the alignment mark pattern in the alignment mark area includes: etching the second plurality of dummy gate structures so that the alignment mark pattern includes a plurality of approximately V-shaped gaps between multiple columns of the second plurality of dummy gate structures.

[0342] As described in more detail above, some embodiments described herein provide a method. The method includes receiving a substrate having a photoresist layer in an exposure tool. The method includes directing extreme ultraviolet radiation from a radiation source to the photoresist layer to form a patterned photoresist layer in an exposure operation, wherein a polysilicon gate-based alignment mark pattern in a polysilicon gate-based alignment mark area is used to align the substrate for the exposure operation.

[0343] In some embodiments, in a method of forming a semiconductor device, the exposure operation includes a second exposure operation; and wherein the method further includes: in a first exposure operation performed before the second exposure operation, extreme ultraviolet radiation from a radiation source is directed to another photoresist layer to form another patterned photoresist layer, wherein a fin-based alignment mark pattern in a fin-based alignment mark area is used to align the substrate for the first exposure operation.

[0344] In some embodiments, in a method of forming a semiconductor device, the fin-based alignment mark region and the polysilicon gate-based alignment mark region are located in different regions of the substrate.

[0345] In some embodiments, in a method of forming a semiconductor device, the polysilicon gate-based alignment mark region is located around a perimeter of the fin-based alignment mark region.

[0346] Some embodiments of the present disclosure provide a semiconductor device comprising: one or more device regions and an alignment mark. The one or more device regions include a plurality of active transistor structures. The alignment mark is adjacent to at least a subset of the one or more device regions, and the alignment mark includes a plurality of non-active gate structures arranged in a pattern. The pattern includes a plurality of rows of the plurality of non-active gate structures, and the plurality of rows are separated by a plurality of gaps between the plurality of rows.

[0347] Some embodiments of the present disclosure provide a semiconductor device comprising: one or more device regions, a first alignment mark region, and a second alignment mark region. The one or more device regions include a plurality of active transistor structures. The first alignment mark region is adjacent to at least a subset of the one or more device regions, the first alignment mark region includes a plurality of non-active gate structures arranged in a pattern. The second alignment mark region is adjacent to another subset of the one or more device regions, the second alignment mark region includes a plurality of non-active fin structures arranged in a second pattern, and the second alignment mark region does not include a gate structure.

[0348] Depending on the context, as used herein, "satisfies a threshold" may mean that a value is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like.

[0349] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purpose as the embodiments introduced herein, and / or to achieve the same advantages. Those skilled in the art will also appreciate that such equal constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: one or more device regions including a plurality of active transistor structures; and An alignment mark is adjacent to at least a subset of the one or more device regions, the alignment mark comprising a plurality of inactive gate structures arranged in a pattern.

2. The semiconductor device according to claim 1, wherein The alignment mark also contains: Multiple non-active fin structures, The plurality of inactive gate structures surround the plurality of inactive fin structures on at least three sides of the plurality of inactive fin structures.

3. The semiconductor device according to claim 2, wherein: The plurality of inactive fin structures extend in a first direction in the semiconductor device; and The plurality of inactive gate structures extend in a second direction in the semiconductor device, and the second direction is approximately perpendicular to the first direction.

4. The semiconductor device according to claim 2, wherein: The pattern contains: the plurality of inactive gate structures of a plurality of columns, The plurality of columns extend in a direction that is not perpendicular to a direction in which the plurality of inactive fin structures extend.

5. The semiconductor device according to claim 1, wherein: The plurality of active transistor structures include a plurality of active gate structures; and A pitch between two or more of the plurality of inactive gate structures and a pitch between two or more of the plurality of active gate structures are approximately the same pitch.

6. The semiconductor device according to claim 1, wherein: The alignment mark also contains: a shallow trench isolation (STI) region above a substrate of the semiconductor device, The plurality of inactive gate structures are included on the shallow trench isolation region.

7. The semiconductor device according to claim 1, wherein The alignment mark includes a first alignment mark; The semiconductor device further comprises a second alignment mark, wherein the second alignment mark comprises a plurality of inactive fin structures arranged in another pattern; and The second alignment mark is adjacent to at least another subset of the one or more device regions.

8. The semiconductor device according to claim 1, wherein The pattern includes a first pattern; wherein the alignment mark further comprises a plurality of inactive fin structures arranged in a second pattern; and The first pattern is located around a periphery of the second pattern.

9. A semiconductor device, characterized in that: Include: one or more device regions including a plurality of active transistor structures; and an alignment mark adjacent to at least a subset of the one or more device regions, the alignment mark comprising a plurality of inactive gate structures arranged in a pattern; The pattern includes a plurality of rows of the non-active gate structures, and the rows are separated by a plurality of gaps between the rows.

10. A semiconductor device, characterized in that: Include: one or more device regions including a plurality of active transistor structures; a first alignment mark region adjacent to at least a subset of the one or more device regions, the first alignment mark region comprising a plurality of inactive gate structures arranged in a first pattern; and A second alignment mark region is adjacent to another subset of the one or more device regions, the second alignment mark region comprising a plurality of inactive fin structures arranged in a second pattern and the second alignment mark region does not include a gate structure.

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