Radar data processing and storage system

Abstract

The utility model belongs to the technical field of data processing and storage. The utility model provides a radar data processing storage system. The system comprises a CPU chip, an FPGA chip, a PCIE bridge chip, a storage array, a CPLD chip and a VPX connector. According to the embodiment of the invention, a CPU chip is in communication connection with an FPGA chip and is used for configuring and managing the FPGA chip; the CPU chip, the FPGA chip, the storage array and the VPX connector are all in communication connection with the PCIE bridge sheet; the FPGA chip is provided with a DDR3 cache chip, and the CPU chip is provided with a DDR4 cache chip. The CPLD chip is used for completing the power-on of the whole board and the realization of a reset time sequence so as to complete the monitoring of a power supply of the whole board; the FPGA chip receives high-speed data through the 12-path light receiving and emitting module and the VPX connector and carries out data processing, and the processed data is sequentially transmitted to the storage array under the management of the CPU chip and the control of the PCIE bridge chip.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of data processing and storage, and in particular, to a radar data processing and storage system. Background Art

[0002] With the rapid development of modern information science and technology, in the context of the big data era, electronic information equipment has developed rapidly. In order to better analyze and optimize radar signal processing algorithms, it is necessary to record the original intermediate frequency data in real time when the radar is working, and at the same time achieve a sufficiently high data recording and processing speed and a sufficiently large storage capacity. However, often limited by the limitations of the environmental space and power supply, radar electronic equipment needs to meet the requirements of small size, light weight, and low power consumption. At the same time, Western countries have imposed technical blockades on domestic high-performance components and such equipment. Due to the above reasons, the existing radar data processing and storage systems are slow, inefficient, small in capacity, and low in localization rate. Therefore, a domestic high-speed radar data processing and storage system is needed. Utility Model Content

[0003] In order to avoid the deficiencies of the prior art, the present utility model provides a radar data processing and storage system to solve the problems of slow speed, low efficiency, small capacity, and low localization rate existing in the existing radar data processing and storage systems in the prior art.

[0004] According to an embodiment of the present disclosure, a radar data processing and storage system is provided, and the system includes:

[0005] A CPU chip, an FPGA chip, a PCIE bridge chip, several groups of storage arrays, a CPLD chip, and a VPX connector; wherein,

[0006] The CPU chip, the FPGA chip, and the storage array are respectively electrically connected to the PCIE bridge chip, the CPU chip is electrically connected to the FPGA chip, the CPU chip, the FPGA chip, and the PCIE bridge chip are respectively electrically connected to the VPX connector, and the CPU chip, the FPGA chip, the PCIE bridge chip, the storage array, and the VPX connector are respectively electrically connected to the CPLD chip.

[0007] Further, the FPGA chip is equipped with several groups of DDR3 cache chips, and the CPU chip is equipped with several groups of DDR4 cache chips.

[0008] Further, the storage array includes several hard disks, and the hard disks are electrically connected to the PCIE bridge chip through a PCIE bus.

[0009] Further, the hard disk is a solid-state drive, the single-block capacity of the solid-state drive is 4TB, the interface of the hard disk is an M.2 interface, and the PCIE bus standard is PCIE 3.0.

[0010] Further, the CPU chip is electrically connected to the VPX connector through an SGMII interface, a DP interface, and a USB interface respectively;

[0011] Further, the USB interface is a USB 2.0.

[0012] Further, the system further includes:

[0013] A network chip and a network port, the network chip is electrically connected to the network port and the CPU chip respectively.

[0014] Further, the number of the network ports is 2. One network port is electrically connected to the network chip, and the other network port is electrically connected to the VPX connector;

[0015] The network port is an RJ45 network port.

[0016] Further, the system further includes:

[0017] A 12-channel optical transceiver module and an optical interface, the 12-channel optical transceiver module is electrically connected to the optical interface and the FPGA chip respectively, so that the 12-channel optical transceiver module can receive an optical signal through the optical interface and transmit the electrical signal converted from the optical signal to the FPGA chip.

[0018] Further, the number of PCIE ports of the PCIE bridge chip is 10. Among them, 2 PCIE ports are communicatively connected to the FPGA chip, 6 PCIE ports are communicatively connected to the storage array, 1 PCIE port is communicatively connected to the CPU chip, and 1 PCIE port is electrically connected to the VPX connector.

[0019] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

[0020] In the embodiments of the present disclosure, through the above-mentioned radar data processing and storage system, which includes a CPU chip, an FPGA chip, a PCIE bridge chip, a storage array, a CPLD chip, and a VPX connector; the CPU chip is communicatively connected to the FPGA chip for configuring and managing the FPGA chip; the CPU chip, the FPGA chip, the storage array, and the VPX connector are all communicatively connected to the PCIE bridge chip; the FPGA chip is equipped with a DDR3 cache chip, and the CPU chip is equipped with a DDR4 cache chip; the CPLD chip realizes the power-on and reset timing of the entire board to complete the monitoring of the power supply of the entire board; the FPGA chip receives high-speed data through 12 transceiver optical modules and the VPX connector and performs data processing, and the processed data is sequentially transmitted to the storage array under the management of the CPU chip and the control of the PCIE bridge chip; the storage array uses multiple solid-state hard drives, greatly improving the data transmission and storage efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0022] Figure 1 The structural schematic diagram of a radar data processing and storage system in an exemplary embodiment of the present disclosure is shown.

[0023] In the figure, 1. FPGA chip; 2. PCIE bridge chip; 3. VPX connector; 4. Network chip; 5. CPU chip; 6. RJ45 network port; 7. Storage array; 8. 12 transceiver optical modules; 9. CPLD chip. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0025] In addition, the accompanying drawings are only schematic illustrations of the embodiments of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0026] In this exemplary embodiment, a radar data processing and storage system is provided. Refer to Figure 1 As shown in

[0027] a CPU chip (5), an FPGA chip (1), a PCIE bridge chip (2), several groups of storage arrays (7), a CPLD chip (9), and a VPX connector (3); wherein, the CPU chip (5), the FPGA chip (1), and the storage arrays (7) are respectively electrically connected to the PCIE bridge chip (2), the CPU chip (5) is electrically connected to the FPGA chip (1), the CPU chip (5), the FPGA chip (1), and the PCIE bridge chip (2) are respectively electrically connected to the VPX connector (3), and the CPU chip (5), the FPGA chip (1), the PCIE bridge chip (2), the storage arrays (7), and the VPX connector (3) are respectively electrically connected to the CPLD chip (9).

[0028] Specifically, the CPU chip (5), the FPGA chip (1), and the storage arrays (7) are all communicatively connected to the PCIE bridge chip (2); the CPU chip (5) is communicatively connected to the FPGA chip (1) for managing the FPGA chip (1); there are multiple groups of storage arrays (7); the CPU chip (5), the FPGA chip (1), and the PCIE bridge chip (2) are all electrically connected to the VPX connector (3); the CPU chip (5) and the FPGA chip (1) are both configured with multiple groups of DDR4 / DDR3 cache chips; the FPGA chip (1) receives high-speed data through an optical fiber module and the VPX connector (3) and performs data processing, and the processed data is stored in the storage arrays (7) in sequence under the management of the CPU chip (5); the CPU chip (5), the FPGA chip (1), the PCIE bridge chip (2), the storage arrays (7), the DDR3 / 4 chips, the CPLD chip (9), etc. are all domestic chips.

[0029] The storage array (7) contains 6 hard disks; the hard disks are solid-state drives; the hard disk interfaces are M.2 interfaces; the hard disks follow the NVME protocol; the hard disks communicate with the PCIE bridge chip (2) through the PCIE bus; the single capacity of the solid-state drive is 4TB; the PCIE bus standard is PCIE 3.0; the VPX connector (3) complies with the VITA46 standard.

[0030] The FPGA chip (1) is electrically connected to the VPX connector (3) through an SRIO interface; the SRIO interface is SRIO X4; the PCIE bridge chip (2) is electrically connected to the VPX connector (3) through a PCIE interface; the CPU chip (5) is respectively electrically connected to the VPX connector (3) through an SGMII interface, a DP interface, and a USB interface; the USB interface is USB 2.0.

[0031] The system further includes: a network chip (4) electrically connected to a network interface and communicatively connected to a CPU chip (5); the network interface is an RJ45 network interface (6); the number of RJ45 network interfaces (6) is 2; one of the network interfaces is electrically connected to a VPX connector (3).

[0032] The system further includes: a 12-channel optical transceiver module (8) electrically connected to an optical interface; the 12-channel optical transceiver module (8) is communicatively connected to an FPGA chip (1); the 12-channel optical transceiver module (8) receives an optical signal through the optical interface and converts it into an electrical signal for transmission to the FPGA.

[0033] The number of ports of the PCIE bridge chip (2) is 10; 2 of the ports are communicatively connected to an FPGA chip (1), and the PCIE interface is PCIE 3.0 X8; 6 of the ports are communicatively connected to a storage array (7), and the PCIE interface is PCIE 3.0 X4; 1 of the ports is communicatively connected to a CPU chip (5), and the PCIE interface is PCIE 3.0 X4; 1 of the ports is electrically connected to a VPX connector (3), and the PCIE interface is PCIE 3.0 X4.

[0034] Through the above radar data processing and storage system, via a CPU chip, an FPGA chip, a PCIE bridge chip, a storage array, a CPLD chip, and a VPX connector; the CPU chip is communicatively connected to the FPGA chip for configuring and managing the FPGA chip; the CPU chip, the FPGA chip, the storage array, and the VPX connector are all communicatively connected to the PCIE bridge chip; the FPGA chip is equipped with a DDR3 cache chip, and the CPU chip is equipped with a DDR4 cache chip; the CPLD chip realizes the power-on and reset timing of the entire board to complete the monitoring of the power supply of the entire board; the FPGA chip receives high-speed data through a 12-channel optical transceiver module and a VPX connector and performs data processing, and the processed data is sequentially transmitted to the storage array under the management of the CPU chip and the control of the PCIE bridge chip; the storage array uses multiple solid-state hard drives, greatly improving the data transmission and storage efficiency.

[0035] Next, reference will be made to Figure 1 for a more detailed description of each part of the above radar data processing and storage system in the present exemplary embodiment.

[0036] In one embodiment, the CPU chip (5), the FPGA chip (1), the storage array (7), and the VPX connector (3) are all communicatively connected to the PCIE bridge chip (2). The CPU chip (5), the FPGA chip (1), and the PCIE bridge chip (2) are all electrically connected to the VPX connector (3). The CPU chip (5) and the FPGA chip (1) are both configured with cache chips. The FPGA chip (1) receives high-speed data through a 12-channel optical transceiver module (8) and the VPX connector (3) and performs data processing. The processed data is stored in the storage array (7) in sequence under the management of the CPU chip (5). The FPGA chip (1) is equipped with several groups of DDR3 cache chips, and the CPU chip (5) is equipped with several groups of DDR4 cache chips. The CPU chip (5), the FPGA chip (1), the PCIE bridge chip (2), the storage array (7), the DDR3 / 4 chips, the CPLD chip (9), etc. are all domestic chips. The storage array (7) contains 6 hard disk solid-state drives and is communicatively connected to the PCIE bridge chip (2) through the PCIE bus.

[0037] In one embodiment, the VPX connector (3) complies with the VITA46 standard. The FPGA chip (1) is electrically connected to the VPX connector (3) through the SRIO interface. The PCIE bridge chip (2) is electrically connected to the VPX connector (3) through the PCIE interface. The CPU chip (5) is electrically connected to the VPX connector (3) through the SGMII interface, the DP interface, and the USB interface. The network chip (4) is electrically connected to the network port and communicatively connected to the CPU chip (5). The network port is an RJ45 network port (6), and the number of RJ45 network ports (6) is 2. One of the RJ45 network ports (6) is electrically connected to the VPX connector (3). The 12-channel optical transceiver module (8) is electrically connected to the optical interface and communicatively connected to the FPGA chip (1).

[0038] In one embodiment, the number of ports of the PCIE bridge chip (2) is 10; 2 of the ports are communicatively connected to the FPGA chip (1), and the PCIE interface is PCIE 3.0 X8; 6 of the ports are communicatively connected to the storage array (7), and the PCIE interface is PCIE3.0 X4; 1 of the ports is communicatively connected to the CPU chip (5), and the PCIE interface is PCIE 3.0 X4; 1 of the ports is electrically connected to the VPX connector (3), and the PCIE interface is PCIE 3.0 X4.

[0039] In one embodiment, the CPU chip (5) is of the ARM architecture processor FT-E2000Q model, and the FPGA chip (1) is of the JFM7VX690T model. The FT-E2000Q manages the JFM7VX690T through the PCIE 3.0 X1 interface and transmits instructions. The VPX connector (3) complies with the VITA46 standard. The periphery of the FPGA chip (1) includes two groups of DDR3 cache chips, each with a bit width of 64 bits and a capacity of 2GB, and includes FLASH chips for power-on information configuration. The periphery of the CPU chip (5) includes a group of DDR4 cache chips, each with a bit width of 64 bits and a capacity of 4GB, and includes EMMC chips for configuring and loading the operating system.

[0040] In one embodiment, the storage array (7) is communicatively connected to the PCIE bridge chip (2) through the PCIE interface. For example, the storage array (7) altogether includes 6 M.2 solid-state drives, follows the NVME protocol, each solid-state drive has a PCIE interface of PCIE 3.0X4, and a capacity of 4TB, totaling 24TB. And the NVME protocol has higher performance and faster speed than the AHCI protocol, and can achieve high-rate data transmission.

[0041] In one embodiment, the PCIE bridge chip (2) is of the SM8748 model, and its ports can be freely allocated. For example, the SM8748 has 10 ports, 2 of which are communicatively connected to the FPGA chip (1) with a PCIE interface of PCIE 3.0 X8; 6 of which are communicatively connected to the storage array (7) with a PCIE interface of PCIE 3.0 X4; 1 of which is communicatively connected to the CPU chip (5) with a PCIE interface of PCIE 3.0 X4; 1 of which is electrically connected to the VPX connector (3) with a PCIE interface of PCIE 3.0 X4.

[0042] In one embodiment, the FPGA chip (1) is electrically connected to the VPX connector (3) through the SRIO interface. For example, the SRIO interface is 4-way X4, and the transmission rate is compatible with 5Gbps and 6.25Gbps.

[0043] In one embodiment, the CPU chip (5) is electrically connected to the VPX connector (3) through the SGMII interface, DP interface, and USB interface. For example, the SMGII interface is 1-way, the DP interface is 1-way X1, and the USB interface is 1-way USB 2.0.

[0044] In one embodiment, it includes a network chip (4) and an RJ45 network interface (6). The network chip (4) is electrically connected to the RJ45 network interface and communicatively connected to the CPU chip (5). For example, the model of the network chip (4) is YT8531S, and it is electrically connected to the CPU chip (5) through an RGMII interface. The RJ45 network interface (6) is used to connect to an external host. The external host is connected to the network chip (4) by inserting into the RJ45 network interface (6), and can send debugging information to the CPU chip (5) through the network chip (4). The number of RJ45 network interfaces (6) is 2, and one of the RJ45 network interfaces (6) is suitable for being electrically connected to the VPX connector (3).

[0045] In one embodiment, it includes a 12-channel optical transceiver module (8). The 12-channel optical transceiver module (8) is communicatively connected to the FPGA chip (1) through 12 GTH high-speed signal lines. For example, the model of the 12-channel optical transceiver module (8) is HTA8550B. Each channel can provide a maximum transmission rate of 10.3125 Gbps. The transmission protocol uses the AURORA protocol, and the optical interface uses an MPO connector. When in use, the module is installed vertically downward facing the motherboard, so that the module positioning posts are vertically inserted into the positioning holes on the motherboard, and the bottom surface of the module is attached to the motherboard.

[0046] In one embodiment, the storage system further includes an MCU, a power supply module, a temperature sensor, a CPLD chip (9), etc. For example, the model of the MCU is GD32F103, which is electrically connected to the power supply module. The power supply module is electrically connected to the CPLD chip (9). The MCU monitors the voltage output of the power supply module and feeds back the information to the CPLD chip (9) for realizing the health management function. For example, the MCU accesses various power supplies of the whole board output by the power supply module. When the output voltage of the power supply module is unstable or too high, the MCU feeds back the monitoring information to the CPLD chip (9). The CPLD chip (9) disconnects the output power supply of the corresponding power supply module to protect the safety of each component and realizes the monitoring and health management of the power supply module. The CPLD chip (9) can flexibly control the power-on and power-off sequence of the device by being electrically connected to the power supply module, and reset and restart the device in a timely manner.

[0047] Through the above radar data processing and storage system, it includes a CPU chip, an FPGA chip, a PCIE bridge chip, a storage array, a CPLD chip, and a VPX connector; the CPU chip is communicatively connected to the FPGA chip for configuring and managing the FPGA chip; the CPU chip, the FPGA chip, the storage array, and the VPX connector are all communicatively connected to the PCIE bridge chip; the FPGA chip is equipped with a DDR3 cache chip, and the CPU chip is equipped with a DDR4 cache chip; the CPLD chip realizes the power-on and reset timing of the whole board to complete the monitoring of the power supply of the whole board; the FPGA chip receives high-speed data through 12 optical transceiver modules and the VPX connector and performs data processing, and the processed data is sequentially transmitted to the storage array under the management of the CPU chip and the control of the PCIE bridge chip; the storage array uses multiple solid-state hard drives, greatly improving the data transmission and storage efficiency.

[0048] It should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. in the above description is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the embodiments of the present disclosure.

[0049] In the embodiments of the present disclosure, unless otherwise clearly defined and limited, the terms "mounted", "connected", "connected to", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0050] In the embodiments of the present disclosure, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over", and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "below", "under", and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0051] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0052] After considering the specification and practicing the utility model disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A radar data processing and storage system, characterized in that: The system includes: CPU chip, FPGA chip, PCIE bridge chip, several groups of storage arrays, CPLD chip and VPX connector; among them, The CPU chip, the FPGA chip, and the storage array are electrically connected to the PCIE bridge chip, respectively. The CPU chip is electrically connected to the FPGA chip. The CPU chip, the FPGA chip, and the PCIE bridge chip are electrically connected to the VPX connector, respectively. The CPU chip, the FPGA chip, the PCIE bridge chip, the storage array, and the VPX connector are electrically connected to the CPLD chip, respectively.

2. The radar data processing and storage system according to claim 1, characterized in that: The FPGA chip is equipped with several groups of DDR3 cache chips, and the CPU chip is equipped with several groups of DDR4 cache chips.

3. The radar data processing and storage system according to claim 1, characterized in that: The storage array includes a plurality of hard disks, and the hard disks are electrically connected to the PCIE bridge chip via a PCIE bus.

4. The radar data processing and storage system according to claim 3, characterized in that: The hard disk is a solid state disk, the single block capacity of the solid state disk is 4TB, the interface of the hard disk is an M.2 interface, and the PCIE bus standard is PCIE 3.

0.

5. The radar data processing and storage system according to claim 1, characterized in that: The CPU chip is electrically connected to the VPX connector via an SGMII interface, a DP interface and a USB interface respectively.

6. The radar data processing and storage system according to claim 5, characterized in that: The USB interface is USB 2.

0.

7. The radar data processing and storage system according to claim 1, characterized in that: The system also includes: A network chip and a network port, wherein the network chip is electrically connected to the network port and the CPU chip respectively.

8. The radar data processing and storage system according to claim 7, characterized in that: The number of the network ports is 2, one of the network ports is electrically connected to the network chip, and the other network port is electrically connected to the VPX connector; The network port is an RJ45 network port.

9. The radar data processing and storage system according to claim 1, characterized in that: The system also includes: A 12-way light-receiving and light-emitting module and an optical interface, wherein the 12-way light-receiving and light-emitting module is electrically connected to the optical interface and the FPGA chip respectively, so that the 12-way light-receiving and light-emitting module can receive optical signals through the optical interface and transmit the electrical signals converted from the optical signals to the FPGA chip.

10. The radar data processing and storage system according to claim 1, characterized in that: The number of PCIE ports of the PCIE bridge is 10, of which 2 PCIE ports are communicatively connected to the FPGA chip, 6 PCIE ports are communicatively connected to the storage array, 1 PCIE port is communicatively connected to the CPU chip, and 1 PCIE port is electrically connected to the VPX connector.

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