Multiphase interlaced power carrier implementation circuit
By designing a multi-phase interleaved power carrier implementation circuit and using the cyclic circuit to form a closed-loop processing mechanism for pulse signals, the problem of poor carrier stability is solved, the stability and accuracy of carrier signals are achieved, and the performance and reliability of switching power supplies are improved.
Patent Information
- Application Number
- CN202421543947.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-02
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-07-02
AI Technical Summary
In multi-phase interleaving technology, the carrier stability is poor due to interference factors in the process of achieving accurate phase-shifting carriers, which increases the difficulty of implementation in switching power supply applications and limits its wider range of applications.
A multi-phase interleaved power carrier implementation circuit is designed, including a clock signal, a shift register and a cyclic circuit. It is connected to the data input terminal of the shift register through the signal output terminal of the cyclic circuit to form a closed-loop processing mechanism of the pulse signal. The interference signal is effectively processed in the cyclic circuit to ensure the stability and accuracy of the carrier signal.
Through the closed-loop processing mechanism, interfering signals are effectively identified and processed, which improves the stability and accuracy of power carrier transmission and reduces performance degradation due to interference or error accumulation.
Smart Images
Figure CN222928289U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of switching power supplies, and more specifically, to a multi-phase interleaved power carrier implementation circuit. Background Art
[0002] In the rapid development of power electronics technology, as the core component of power conversion and distribution, the performance of switching power supplies directly affects the stability and reliability of the entire electronic system. Especially in medium and high power applications, such as data centers, communication base stations, industrial control and other fields, extremely high requirements are imposed on the output performance of switching power supplies. Among them, the optimization of output current ripple, capacitor volume, and thermal and power distribution are important considerations in the design of switching power supplies.
[0003] Although traditional switching power supply design methods can meet basic power conversion requirements, they often seem inadequate when faced with application scenarios of large current and low ripple. Especially with the continuous progress of semiconductor technology and the improvement of the integration degree of electronic devices, the performance requirements for power systems are becoming increasingly strict, and traditional power supply design methods are difficult to meet the development needs of modern electronic systems.
[0004] As an advanced power electronics technology, multi-phase interleaved technology can effectively reduce the ripple of output current by introducing output currents of multiple phases, thereby reducing the volume of output capacitors and optimizing thermal and power distribution. This technology has been widely used in medium and high power applications, significantly improving the performance and reliability of switching power supplies.
[0005] However, the implementation of multi-phase interleaved technology is not easy. Among them, how to conveniently and accurately implement phase-shifted carriers is a rather difficult problem. In multi-phase interleaved technology, the phase difference of carrier signals determines the interleaving degree of each phase output current, which in turn affects the ripple of output current and capacitor volume. Therefore, ensuring that the carriers can be accurately phase-shifted is the key to implementing multi-phase interleaved technology.
[0006] At present, although there are some methods to implement phase-shifted carriers, there is a problem of poor carrier stability due to the existence of interference factors during the implementation of phase-shifted carriers. The problem of poor stability not only increases the implementation difficulty of multi-phase interleaved technology in switching power supply applications, but also limits its application in a wider range. Summary of the Utility Model
[0007] In order to overcome the problem of poor carrier stability caused by the existence of interference factors during the implementation of existing phase-shifted carriers, the utility model provides a multi-phase interleaved power carrier implementation circuit.
[0008] The technical solution of the utility model is as follows:
[0009] A multi-phase interleaved power carrier implementation circuit includes a clock signal Clk, a shift register, and a loop circuit. The clock signal Clk is connected to the data input terminal of the shift register. The signal output terminal of the shift register is connected to the signal input terminal of the loop circuit. A logic gate integrated circuit is provided in the loop circuit. The signal output terminal of the loop circuit is connected to the data input terminal of the shift register. When the pulse signal output by the shift register is an interference signal, it enters the loop circuit for logical processing and then is input to the data input terminal of the shift register to complete the circulation of the pulse signal.
[0010] For the present invention according to the above solution, the loop circuit includes a first logic gate 74HC132 and a second logic gate 74HC08. The input terminals of both the first logic gate 74HC132 and the second logic gate 74HC08 are connected to the signal input terminal of the shift register. And the output terminal of the first logic gate 74HC132 and the output terminal of the second logic gate 74HC08 are connected to the input terminal of another first logic gate 74HC132. The output terminal of another first logic gate 74HC132 is connected to the input terminal of another second logic gate 74HC08. The output terminal of another second logic gate 74HC08 is connected to the data input terminal of the shift register.
[0011] For the present invention according to the above solution, it further includes an RC differentiating circuit. One end of the RC differentiating circuit is connected to the signal output terminal of the shift register, and the other end of the RC differentiating circuit is connected to the second logic gate 74HC08. When the pulse signal output by the shift register is a normal signal, it is shaped by the RC differentiating circuit and the second logic gate 74HC08 to obtain a narrow pulse signal, which is used as the reset signal of the carrier signal.
[0012] For the present invention according to the above solution, the RC differentiating circuit includes a resistor and a capacitor, and the resistor and the capacitor are connected in parallel.
[0013] For the present invention according to the above solution, it further includes an auxiliary circuit. The input terminal of the auxiliary circuit is connected to the signal output terminal of the shift register, and the output terminal of the auxiliary circuit is connected to the loop circuit. When the pulse signal output by the shift register is an abnormal signal, it is forced into the loop state through the auxiliary circuit.
[0014] For the present utility model according to the above solution, the auxiliary circuit includes a first logic gate 74HC132 and a second logic gate 74HC08. The signal output terminal of the shift register is connected to the input terminals of two of the second logic gates 74HC08. And the output terminal of one of the second logic gates 74HC08 is connected to the input terminal of another second logic gate 74HC08. And the output terminal of the other second logic gate 74HC08 is connected to the input terminal of the first logic gate 74HC132. And the output terminal of the first logic gate 74HC132 is connected to the input terminal of another second logic gate 74HC08 of the loop circuit.
[0015] For the present utility model according to the above solution, the port where the clock signal Clk is connected to the shift register and the port where the loop circuit is connected to the shift register are different ports.
[0016] For the present utility model according to the above solution, its beneficial effects are as follows. The present utility model simplifies the complexity of the power carrier process. By connecting the signal output terminal of the loop circuit to the data input terminal of the shift register, a closed-loop processing mechanism for pulse signals is formed. Interference signals can be effectively processed in the loop circuit, enabling continuous monitoring and correction of pulse signals during transmission, and reducing performance degradation caused by interference or error accumulation. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is the circuit diagram of the present utility model;
[0018] Figure 2 is the waveform block diagram for the implementation of the present utility model.
[0019] In the figure, the reference numerals are as follows:
[0020] 1. Shift register; 2. Loop circuit; 3. RC differentiating circuit; 4. Auxiliary circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0021] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present utility model more clearly understood, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.
[0022] It should be noted that in the description and claims of the present utility model, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include steps or units not listed, or may optionally further include other steps or units inherent to these processes, methods, products, or devices. Terms such as "arranged" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components, unless otherwise clearly defined. The orientations or positions indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "bottom", etc. are based on the orientations or positions shown in the drawings, and are only for convenience of description and should not be construed as a limitation to the technical solution of the present invention.
[0023] It should be noted that currently, although there are already some methods to achieve phase-shifted carrier, during the process of achieving phase-shifted carrier, due to the existence of interference factors, there is a problem of poor carrier stability. The problem of poor stability not only increases the implementation difficulty of the multi-phase interleaving technology in the application of switching power supplies, but also limits its application in a larger range.
[0024] This patent takes a three-phase interleaving circuit as an example, and it is also applicable to other interleaving numbers.
[0025] As Figure 1 - Figure 2 shown, this embodiment provides a multi-phase interleaved power carrier implementation circuit, which simplifies the complexity of the power carrier process. By connecting the signal output end of the loop circuit 2 to the data input end of the shift register 1, a closed-loop processing mechanism for pulse signals is formed, and interference signals can be effectively processed in the loop circuit 2, so that the pulse signals can be continuously monitored and corrected during the transmission process, reducing the performance degradation caused by interference or error accumulation.
[0026] Specifically, it includes a clock signal Clk, a shift register 1, and a loop circuit 2. The clock signal Clk is connected to the data input end of the shift register 1, the signal output end of the shift register 1 is connected to the signal input end of the loop circuit 2. A logic gate integrated circuit is provided inside the loop circuit 2, and the signal output end of the loop circuit 2 is connected to the data input end of the shift register 1. When the pulse signal output by the shift register 1 is an interference signal, it enters the loop circuit 2 for logical processing and then is input to the data input end of the shift register 1 to complete the loop of the pulse signal, which can effectively identify and process interference signals, thereby ensuring the stability and accuracy of power carrier transmission.
[0027] Specifically, the designed clock signal Clk with three - times - frequency carrier is input into the shift register 1. The phase - shifted pulse signals after frequency division are respectively taken out from Q0, Q1, and Q2 at the output of the shift register 1. When the output pulse signal is an interference signal, it enters the loop circuit 2. After logical processing, it is cyclically input to the data input terminals DSA and DSB of the shift register 1 to complete the cycle of the pulse signal.
[0028] In one embodiment, the loop circuit 2 includes a first logic gate 74HC132 and a second logic gate 74HC08. The input terminals of the first logic gate 74HC132 and the input terminals of the second logic gate 74HC08 are both connected to the signal input terminal of the shift register 1. And the output terminal of the first logic gate 74HC132 and the output terminal of the second logic gate 74HC08 are connected to the input terminal of another first logic gate 74HC132. The output terminal of another first logic gate 74HC132 is connected to the input terminal of another second logic gate 74HC08. The output terminal of another second logic gate 74HC08 is connected to the data input terminal of the shift register 1. The first logic gate 74HC132 and the second logic gate 74HC08 perform operations according to the logical relationship of the input signals and generate corresponding output signals. These output signals will be fed back to the data input terminal of the shift register 1, thereby realizing the correction and optimization of the pulse signal, effectively suppressing the interference and error in the pulse signal, and improving the stability and accuracy of the power carrier transmission.
[0029] To achieve the cycle of states, the shift register 1 needs to continuously input data to ensure that the state cycle of Q0, Q1, and Q2 is 110→011→101→110.
[0030] When the initial state of Q0, Q1, and Q2 or due to interference is 000, this circuit also enters the state cycle 110→011→101→110 from 000→100→110;
[0031] When the initial state of Q0, Q1, and Q2 or due to interference is 001, this circuit also enters the state cycle 110→011→101→110 from 001→100→110;
[0032] When the initial state of Q0, Q1, and Q2 or due to interference is 010, this circuit also enters the state cycle 101→110→011→101 from 010→101.
[0033] In one embodiment, an RC differentiating circuit 3 is further included. One end of the RC differentiating circuit 3 is connected to the signal output end of the shift register 1, and the other end of the RC differentiating circuit 3 is connected to the second logic gate 74HC08. When the pulse signal output by the shift register 1 is a normal signal, a narrow pulse signal is obtained after shaping by the RC differentiating circuit 3 and the second logic gate 74HC08, which serves as the reset signal of the carrier signal.
[0034] The RC differentiating circuit 3 and the second logic gate 74HC08 together constitute a signal shaping and reset mechanism. When the shift register 1 outputs a normal pulse signal, the signal undergoes sharpening processing by the RC differentiating circuit 3 and then logical operations by the second logic gate 74HC08, finally obtaining an accurate reset signal. The reset signal can effectively control the generation and transmission of the carrier signal, improving the performance and stability of the entire power carrier system.
[0035] Specifically, the designed clock signal Clk of the carrier triple frequency is input into the shift register 1. After frequency division, the out-of-phase pulse signals are respectively taken out at Q0, Q1, and Q2 of the output of the shift register 1. When the output pulse signal is a normal signal, this pulse signal is then processed into a narrow pulse signal, which serves as the reset signal of the carrier signal respectively.
[0036] Preferably, the RC differentiating circuit 3 includes a resistor and a capacitor, and the resistor and the capacitor are connected in parallel.
[0037] In one embodiment, an auxiliary circuit 4 is further included. The input end of the auxiliary circuit 4 is connected to the signal output end of the shift register 1, and the output end of the auxiliary circuit 4 is connected to the loop circuit 2. When the pulse signal output by the shift register 1 is an abnormal signal, it is forced into a loop state via the auxiliary circuit 4.
[0038] Specifically, when the output signal of the shift register 1 is in an abnormal working state and cannot make the output state enter the loop state, it is forced into the loop state by the auxiliary circuit 4.
[0039] In one embodiment, the auxiliary circuit 4 includes a first logic gate 74HC132 and a second logic gate 74HC08. The signal output end of the shift register 1 is connected to the input ends of two second logic gates 74HC08, and the output end of one second logic gate 74HC08 is connected to the input end of another second logic gate 74HC08, and the output end of the other second logic gate 74HC08 is connected to the input end of the first logic gate 74HC132, and the output end of the first logic gate 74HC132 is connected to the input end of another second logic gate 74HC08 of the loop circuit 2.
[0040] There is an abnormal working state in the state machine of Q0, Q1, Q2 of the output of the shift register 1, and the output state cannot enter the cycle state, and the auxiliary circuit 4 forces it to enter the cycle state.
[0041] When Q0, Q1, Q2 are initially in the state of 111 or due to interference, the circuit cannot enter the state cycle 110→011→101→110 through the above two parts. Auxiliary circuit 4 forces the state 111 to enter the cycle state, that is, 111→011→101→110.
[0042] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.
[0043] The above is an exemplary description of the utility model patent in conjunction with the accompanying drawings. It is obvious that the implementation of the utility model patent is not limited to the above-mentioned method. As long as various improvements are made by adopting the method concept and technical solution of the utility model patent, or the concept and technical solution of the utility model patent are directly applied to other occasions without improvement, they are all within the protection scope of the utility model.
Claims
1. A multi-phase interleaved power supply carrier realization circuit, characterized in that: It includes a clock signal Clk, a shift register and a circulation circuit, wherein the clock signal Clk is connected to the data input end of the shift register, the signal output end of the shift register is connected to the signal input end of the circulation circuit, a logic gate integrated circuit is arranged in the circulation circuit, the signal output end of the circulation circuit is connected to the data input end of the shift register, when the pulse signal output by the shift register is an interference signal, it enters the circulation circuit for logic processing and then is input to the data input end of the shift register, thereby completing the circulation of the pulse signal.
2. A multi-phase interleaved power supply carrier realization circuit according to claim 1, characterized in that: The circulation circuit includes a first logic gate 74HC132 and a second logic gate 74HC08, wherein the input end of the first logic gate 74HC132 and the input end of the second logic gate 74HC08 are both connected to the signal input end of the shift register, and the output end of the first logic gate 74HC132 and the output end of the second logic gate 74HC08 are connected to the input end of another first logic gate 74HC132, the output end of another first logic gate 74HC132 is connected to the input end of another second logic gate 74HC08, and the output end of another second logic gate 74HC08 is connected to the data input end of the shift register.
3. A multi-phase interleaved power supply carrier realization circuit according to claim 1 or 2, characterized in that: It also includes an RC differential circuit, one end of which is connected to the signal output end of the shift register, and the other end of which is connected to the second logic gate 74HC08. When the pulse signal output by the shift register is a normal signal, a narrow pulse signal is obtained after being shaped by the RC differential circuit and the second logic gate 74HC08, which serves as a reset signal for the carrier signal.
4. A multi-phase interleaved power carrier realization circuit according to claim 3, characterized in that: The RC differential circuit includes a resistor and a capacitor, and the resistor and the capacitor are connected in parallel.
5. A multi-phase interleaved power carrier realization circuit according to claim 2, characterized in that: It also includes an auxiliary circuit, the input end of the auxiliary circuit is connected to the signal output end of the shift register, the output end of the auxiliary circuit is connected to the circulation circuit, and when the pulse signal output by the shift register is an abnormal signal, it is forced to enter a circulation state through the auxiliary circuit.
6. A multi-phase interleaved power supply carrier realization circuit according to claim 5, characterized in that: The auxiliary circuit includes a first logic gate 74HC132 and a second logic gate 74HC08, the signal output end of the shift register is connected to the input ends of two second logic gates 74HC08, and the output end of one second logic gate 74HC08 is connected to the input end of another second logic gate 74HC08, and the output end of another second logic gate 74HC08 is connected to the input end of the first logic gate 74HC132, and the output end of the first logic gate 74HC132 is connected to the input end of another second logic gate 74HC08 of the cyclic circuit.