Circuit for converting serial data input into parallel data output

Abstract

The utility model provides a circuit for converting serial data input into parallel data output. The circuit comprises a first shift register chip, a second shift register chip, a first latch chip, a second latch chip, a first resistor and a second resistor, the first end of the first resistor and the first end of the second resistor are used for being connected with a power supply respectively, a pin 12 of the first shifting register chip is connected with a pin 12 of the second shifting register chip, and a pin 14 and a pin 15 of the first shifting register chip are used for being connected with input of serial data; the output end of the first shift register chip is connected with the input end of the first latch chip, the output end of the second shift register chip is connected with the input end of the second latch chip, and the output end of the first latch chip and the output end of the second latch chip are respectively used for outputting parallel data. And a function of converting serial data input into parallel data output is realized. According to the utility model, data parallel output is strong in anti-interference capability and high in reliability.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, and particularly relates to a circuit for converting serial data input into parallel data output. Background Art

[0002] At present, the data transmission methods include serial data transmission and parallel data transmission. Serial data transmission is to transmit the code elements constituting data and characters bit by bit in sequence according to the time sequence, and parallel data transmission is to transmit fixed-bit data and character code elements to the receiving end simultaneously. Serial-to-parallel conversion is a technology to complete the conversion between these two transmission methods.

[0003] The serial-to-parallel conversion circuit in the prior art uses multiple flip-flops connected in series to form a shift register for serial-to-parallel conversion. In a memory system, there are usually multiple memory cell arrays. When controlling the read and write operations of multiple memory cell arrays, signal transmission needs to be realized through various signal transmission circuits. Because multiple memory cells are involved, sometimes the input signal of the signal transmission circuit is to input multiple signals in parallel simultaneously, but the output needs to output one by one. For example, the output of the read signal of the memory system. When reading, the signals of multiple memory cells are read simultaneously, but when outputting, the stored information of each memory cell needs to be output one by one. Therefore, it is necessary to design an input-output circuit with a simple structure and fast data transmission.

[0004] However, the above method using multiple memory cell arrays increases the complexity and design cost of circuit design. At the same time, it is easy to cause the problem of poor anti-interference ability of the overall circuit. Summary of the Utility Model

[0005] The utility model provides a circuit for converting serial data input into parallel data output, aiming to solve the problems of poor anti-interference ability and poor parallel output effect of the existing input-output circuit.

[0006] An embodiment of the present utility model provides a circuit for converting serial data input into parallel data output, including: a first shift register chip, a second shift register chip, a first latch chip, a second latch chip, a first resistor, and a second resistor; the first ends of the first resistor and the second resistor are respectively used to connect a power supply, the second end of the first resistor is connected to pin 10 of the first shift register chip, the second end of the second resistor is connected to pin 10 of the second shift register chip, pin 11 of the first shift register chip is connected to pin 11 of the second shift register chip, pin 9 of the first shift register chip is connected to pin 14 of the second shift register chip, pin 12 of the first shift register chip is connected to pin 12 of the second shift register chip, and pins 14 and 15 of the first shift register chip are used to connect the input of serial data; the output end of the first shift register chip is connected to the input end of the first latch chip, the output end of the second shift register chip is connected to the input end of the second latch chip, and the output ends of the first latch chip and the second latch chip are respectively used to output parallel data, realizing the function of converting serial data input into parallel data output.

[0007] Preferably, the first latch chip is grounded through connecting a first capacitor.

[0008] Preferably, the second latch chip is grounded through connecting a second capacitor.

[0009] Preferably, the first shift register chip is grounded through connecting a third capacitor.

[0010] Preferably, the second shift register chip is grounded through connecting a fourth capacitor.

[0011] Compared with the prior art, the beneficial effects of the present utility model are as follows: by connecting the first ends of the first resistor and the second resistor to the power supply respectively, connecting the second end of the first resistor to pin 10 of the first shift register chip, connecting the second end of the second resistor to pin 10 of the second shift register chip, connecting pin 11 of the first shift register chip to pin 11 of the second shift register chip, connecting pin 9 of the first shift register chip to pin 14 of the second shift register chip, connecting pin 12 of the first shift register chip to pin 12 of the second shift register chip, and using pin 14 and pin 15 of the first shift register chip to connect the input of serial data; connecting the output end of the first shift register chip to the input end of the first latch chip, connecting the output end of the second shift register chip to the input end of the second latch chip, and using the output ends of the first latch chip and the second latch chip to output parallel data respectively, realizing the function of converting serial data input to parallel data output; thus realizing a circuit for converting 16-bit serial data to parallel output, with a two-stage latching function to improve the anti-interference ability, and the reliability of the overall circuit is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present utility model will be described in detail below with reference to the accompanying drawings. Through the detailed description in combination with the following drawings, the above or other aspects of the present utility model will become clearer and easier to understand. In the drawings:

[0013] Figure 1 is the circuit diagram of the circuit for converting serial data input to parallel data output provided by the embodiment of the present utility model;

[0014] Figure 2 is the circuit diagram of the shift register chip provided by the embodiment of the present utility model;

[0015] Figure 3 is the circuit diagram of the latch chip provided by the embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] In order to make the objectives, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0017] Combined with the attached Figures 1 - 3As shown in the figure, an embodiment of the present invention provides a circuit for converting serial data input into parallel data output, including: a first shift register chip U1, a second shift register chip U2, a first latch chip U3, a second latch chip U4, a first resistor R1, and a second resistor R2; the first ends of the first resistor R1 and the second resistor R2 are respectively used to connect to a power supply, the second end of the first resistor R1 is connected to pin 10 of the first shift register chip U1, the second end of the second resistor R2 is connected to pin 10 of the second shift register chip U2, pin 11 of the first shift register chip U1 is connected to pin 11 of the second shift register chip U2, pin 9 of the first shift register chip U1 is connected to pin 14 of the second shift register chip U2, pin 12 of the first shift register chip U1 is connected to pin 12 of the second shift register chip U2, and pins 14 and 15 of the first shift register chip U1 are used to connect to the input of serial data; the output end of the first shift register chip U1 is connected to the input end of the first latch chip U3, the output end of the second shift register chip U2 is connected to the input end of the second latch chip U4, and the output ends of the first latch chip U3 and the second latch chip U4 are respectively used to output parallel data, realizing the function of converting serial data input into parallel data output. Thus, a circuit for converting 16-bit serial data into parallel output is realized, with a secondary latch function to improve the anti-interference ability, and the overall circuit has good reliability.

[0018] In this embodiment, the first latch chip U3 is grounded through connecting a first capacitor C1.

[0019] In this embodiment, the second latch chip U4 is grounded through connecting a second capacitor C2.

[0020] In this embodiment, the first shift register chip U1 is grounded through connecting a third capacitor C3.

[0021] In this embodiment, the second shift register chip U2 is grounded through connecting a fourth capacitor C4.

[0022] In specific implementation, 16-bit serial data is input from the DATA interface, and the CLK clock signal samples the data at each rising edge and sends it to the first shift register chip U1. The second shift register chip U2 stores the data. At the rising edge of the LOCK1 pin signal, the first shift register chip U1 and the second shift register chip U2 latch the stored serial data and send it out in parallel to obtain parallel data BIT0 - BIT15. Before the next rising edge of the LOCK1 signal arrives, no matter what data is input, the current output data will not change. This is the first-level latch.

[0023] The 16-bit parallel data sent out is transmitted to the first latch chip U3 and the second latch chip U4 through the first shift register chip U1 and the second shift register chip U2. When the latch signal LOCK2 of the first latch chip U3 and the second latch chip U4 is at a low level, no matter what data is input, the output will remain the current output state without change. Only when LOCK2 is at a high level, the latch will update the output to receive the data to obtain A0 - A15, thus realizing the two-stage latching function. The above completes the 16-bit serial-to-parallel data output circuit with two-stage latching.

[0024] It should be noted that in this article, the terms "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, article or device including that element.

[0025] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiments of the present invention, but the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can still make many equivalent changes in form without departing from the purpose of the present invention and the scope protected by the claims, and all of them belong to the protection scope of the present invention.

Claims

1. A circuit for converting serial data input to parallel data output, characterized in that: include: A first shift register chip, a second shift register chip, a first latch chip, a second latch chip, a first resistor and a second resistor; the first end of the first resistor and the first end of the second resistor are respectively used to connect to a power supply, the second end of the first resistor is connected to pin 10 of the first shift register chip, the second end of the second resistor is connected to pin 10 of the second shift register chip, pin 11 of the first shift register chip is connected to pin 11 of the second shift register chip, pin 9 of the first shift register chip is connected to pin 14 of the second shift register chip, pin 12 of the first shift register chip is connected to pin 12 of the second shift register chip, pin 14 and pin 15 of the first shift register chip are used to connect the input of serial data; the output end of the first shift register chip is connected to the input end of the first latch chip, the output end of the second shift register chip is connected to the input end of the second latch chip, the output end of the first latch chip and the output end of the second latch chip are respectively used to output parallel data, so as to realize the function of converting serial data input to parallel data output.

2. The circuit for converting serial data input to parallel data output as claimed in claim 1, characterized in that: The first latch chip is connected to a first capacitor and grounded.

3. The circuit for converting serial data input to parallel data output as claimed in claim 1, characterized in that: The second latch chip is connected to a second capacitor and grounded.

4. The circuit for converting serial data input to parallel data output as claimed in claim 1, characterized in that: The first shift register chip is connected to a third capacitor and grounded.

5. The circuit for converting serial data input to parallel data output as claimed in claim 1, characterized in that: The second shift register chip is connected to a fourth capacitor and grounded.

Images