Semiconductor device

Abstract

The utility model discloses a semiconductor device which comprises a source electrode, a drain electrode, a gate electrode, a channel structure, a supporting layer and a gate electrode dielectric layer. The drain electrode and the source electrode are stacked in the vertical direction, and the gate electrode is arranged between the drain electrode and the source electrode. The channel structure part is arranged in the gate electrode and is connected with the drain electrode and the source electrode. The supporting layer is arranged on the side wall of the channel structure. The gate dielectric layer is partially disposed between the channel structure and the gate in the horizontal direction and partially disposed between the support layer and the gate. Thus, by means of the arrangement of the supporting layer, the gate dielectric layer can be arranged around the gate, and the operation performance of the semiconductor device is effectively improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor devices, and more specifically, to a semiconductor device. Background Art

[0002] The technology of semiconductor integrated circuits has been continuously progressing and growing over time. Products under each new generation of manufacturing processes have smaller and more complex circuit designs than those of the previous generation. Due to the need for product innovation, the number and density of functional components on each wafer region must be continuously increased, and of course, the geometric dimensions of each component need to be smaller and smaller. Since the traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing process is difficult to continue shrinking, the industry has proposed to replace the traditional planar transistor components with three-dimensional or non-planar transistor components, so as to reduce the geometric dimensions of the transistor components and / or improve the operating performance of the transistor elements. Summary of the Utility Model

[0003] The purpose of the utility model is to provide a semiconductor device, in which a support layer is additionally arranged on the side wall of the channel structure, so that the gate dielectric layer can be arranged around the gate, thereby improving the structural stability and operating performance of the semiconductor device, and solving the problems that the structure of the semiconductor device in the related technology lacks stability and the operating performance is poor.

[0004] To achieve the above purpose, an embodiment of the utility model provides a semiconductor device, including a source electrode, a drain electrode, a gate electrode, a channel structure, a support layer, and a gate dielectric layer. The drain electrode and the source electrode are stacked in the vertical direction, and the gate electrode is arranged between the drain electrode and the source electrode. The channel structure is partially arranged in the gate electrode and connects the drain electrode and the source electrode. The support layer is arranged on the side wall of the channel structure. The gate dielectric layer is partially arranged horizontally between the channel structure and the gate electrode and partially arranged between the support layer and the gate electrode.

[0005] The semiconductor device of the utility model includes a source electrode, a drain electrode, a gate electrode, a channel structure, a support layer, and a gate dielectric layer. The drain electrode and the source electrode are stacked in the vertical direction, and the gate electrode is arranged between the drain electrode and the source electrode. Part of the channel structure is arranged in the gate electrode and connects the drain electrode and the source electrode. The support layer is arranged on the side wall of the channel structure. Part of the gate dielectric layer is arranged horizontally between the channel structure and the gate electrode, and part of the gate dielectric layer is arranged between the support layer and the gate electrode. Through the arrangement of the support layer, the gate dielectric layer can be arranged around the gate electrode, effectively improving the operating performance of the semiconductor device. Brief Description of the Drawings

[0006] The accompanying drawings provided offer a deeper understanding of the embodiments of the present utility model and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all the drawings are schematic diagrams, for the purpose of illustration and drawing convenience, and the relative dimensions and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figure 1 Shown is a cross-sectional schematic diagram of a semiconductor device according to the first embodiment of the present utility model;

[0008] Figure 2 is a top-view schematic diagram of the semiconductor device after forming the support material layer;

[0009] Figure 3 is a cross-sectional schematic diagram of the semiconductor device after forming the support material layer;

[0010] Figure 4 is a top-view schematic diagram of the semiconductor device after forming the via holes;

[0011] Figure 5 is a cross-sectional schematic diagram of the semiconductor device after forming the via holes;

[0012] Figure 6 is a cross-sectional schematic diagram of the semiconductor device after forming the channel structure;

[0013] Figure 7 is a cross-sectional schematic diagram of the semiconductor device after removing the sacrificial layer;

[0014] Figure 8 is a cross-sectional schematic diagram of the semiconductor device after forming the electrode material layer;

[0015] Figure 9 is a cross-sectional schematic diagram of the semiconductor device after forming the gate;

[0016] Figure 10 is a top-view schematic diagram of the semiconductor device after forming the insulating spacer;

[0017] Figure 11 is a cross-sectional schematic diagram of the semiconductor device after forming the insulating spacer;

[0018] Figure 12 Shown is a cross-sectional schematic diagram of a semiconductor device according to the second embodiment of the present utility model.

[0019] Among them, the reference numerals are explained as follows:

[0020] 10, 20 Semiconductor devices

[0021] 100 Dielectric layer

[0022] 102, 106, 136, 142 Metal Barrier Layers

[0023] 104, 138, 144 Electrode Layers

[0024] 108 Bottom Semiconductor Layer

[0025] 110 Bottom Dielectric Layer

[0026] 112 First Dielectric Layer

[0027] 112a First Dielectric Material Layer

[0028] 114 Second Dielectric Layer

[0029] 114a Second Dielectric Material Layer

[0030] 116 Sacrificial Layer

[0031] 118 Filling Layer

[0032] 120 Channel Layer

[0033] 122 Insulating Layer

[0034] 124 First Semiconductor Layer

[0035] 126 Second Semiconductor Layer

[0036] 130 Support Layer

[0037] 130a Support Material Layer

[0038] 132 First Gate Dielectric Layer

[0039] 132a First Gate Dielectric Material Layer

[0040] 134 Second Gate Dielectric Layer

[0041] 134a Second Gate Dielectric Material Layer

[0042] 136, 236 Metal Barrier Layers

[0043] 136a Electrode Barrier Material Layer

[0044] 138, 238 Electrode Layers

[0045] 138a Electrode Material Layer

[0046] 140, 240 Insulating Spacers

[0047] 146 Top Dielectric Layer

[0048] 236a Recess

[0049] 238a recess

[0050] 240a, 240b protrusions

[0051] D1 vertical direction

[0052] D2 horizontal direction

[0053] D3 horizontal direction

[0054] DE drain

[0055] GE gate

[0056] GD gate dielectric layer

[0057] OP via hole

[0058] R1, R2, R3 vias

[0059] SE source

[0060] SS channel structure

[0061] V1 void Detailed implementation manners

[0062] To enable those of ordinary skill in the art to which the present utility model pertains to further understand the present utility model, several preferred embodiments of the present utility model are specifically enumerated below, and in conjunction with the attached drawings, the technical solutions of the present utility model and the effects to be achieved are described in detail. Those skilled in the art to which the present utility model pertains can, without departing from the spirit of the present utility model, refer to the following embodiments and replace, recombine, and mix the features in several different embodiments to complete other embodiments.

[0063] Please refer to Figure 1 as shown Figure 1 which is a cross-sectional schematic view of the semiconductor device 10 according to the first embodiment of the present utility model. As Figure 1As shown, the semiconductor device 10 includes a source SE, a drain DE, a gate GE, a channel structure SS, a support layer 130, and a gate dielectric layer GD. The source SE and the drain DE are stacked in the vertical direction D1. The gate GE is located above the source SE and is disposed between the source SE and the drain DE. The channel structure SS is partially disposed within the gate GE and is also disposed between the source SE and the drain DE in the vertical direction D1 to electrically connect the source SE and the drain DE. It should be noted that the support layer 130 is disposed on a partial sidewall of the channel structure SS, and the gate dielectric layer GD covers the support layer 130, such that a part of the gate dielectric layer GD is disposed between the channel structure SS and the gate GE in the horizontal direction D2 / D3, and another part of the gate dielectric layer GD is disposed between the support layer 130 and the gate GE in the vertical direction D1. Thus, by means of the setting of the support layer 130, the gate dielectric layer GD covering the sidewall of the support layer 130 can be disposed around the gate GE, improving the structural stability between the gate GE and the channel structure SS, thereby enhancing the operation performance of the semiconductor device 10.

[0064] Furthermore, the semiconductor device 10 further includes a bottom dielectric layer 110 and an insulating spacer 140 sequentially disposed between the source SE and the drain GE, which for example include an insulating material the same as or different from the support layer 130. In one embodiment, the bottom dielectric layer 110, the insulating spacer 140, and the support layer 130 for example include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulating materials. Among them, it can be that the insulating spacer 140 and the support layer 130 include different materials, or the insulating spacer 140 and the bottom dielectric layer 110 include different materials. For example, when the insulating spacer 140 for example includes materials such as silicon oxide and silicon oxynitride, the bottom dielectric layer 110 and the support layer 130 for example include materials such as silicon nitride and silicon carbonitride, but this is not limiting. In another embodiment, the support layer 130 can also be selected to include the same material as the insulating spacer 140, such as silicon oxide and silicon oxynitride. Preferably, the bottom dielectric layer 110 specifically includes a first dielectric layer 112 and a second dielectric layer 114 sequentially disposed, which for example include different insulating materials. Among them, the first dielectric layer 112 preferably includes the same material as the insulating spacer 140, such as silicon oxide, and the second dielectric layer 114 preferably includes the same material as the support layer 130, such as silicon nitride, but this is not limiting.

[0065] The gate GE is disposed within the insulating spacer 140, and the bottom of the insulating spacer 140 further extends into the bottom dielectric layer 110 and has a bottom surface lower than that of the gate dielectric layer GD. Thus, the channel structure SS partially disposed within the gate GE is also partially disposed within the bottom dielectric layer 110 between the source SE and the gate GE and has a bottom surface flush with the bottom dielectric layer 110, asFigure 1 As shown. Accordingly, the setting of the gate dielectric layer GD can effectively isolate the gate GE and its adjacent components, optimizing the structure and function of the gate GE. It should be noted that the gate dielectric layer GD physically contacts the upper surface, the lower surface and one side wall of the gate GE at the same time, and also physically contacts the side wall and the lower surface of the support layer 130 at the same time, so that the gate dielectric layer GD is also partially disposed between the support layer 130 and the insulating spacer 140 in the horizontal directions D2 / D3, and is also partially located below the gate GE in the vertical direction D1, between the gate GE and the bottom dielectric layer 110. That is to say, the gate dielectric layer GD generally presents a ladle-shaped cross section as shown in Figure 1 shown, and is disposed around the gate GE. In one embodiment, the gate dielectric layer GD specifically includes a first gate dielectric layer 132 and a second gate dielectric layer 134 sequentially disposed between the channel structure SS and the gate GE in the horizontal directions D2 / D3. Among them, the first gate dielectric layer 132 and the second gate dielectric layer 134 respectively include, for example, different dielectric materials or high-k dielectric materials.

[0066] For another example Figure 1 As shown, the semiconductor device 10 further includes a dielectric layer 100, a bottom semiconductor layer 108, a via hole OP, and a top dielectric layer 146. The foregoing components such as the source SE, the drain DE, the gate GE, the channel structure SS, the support layer 130, and the gate dielectric layer GD are all disposed on the dielectric layer 100, and the dielectric layer 100 is disposed on a substrate (not shown). The substrate includes, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. Those skilled in the art should easily understand that various required active components and / or passive components can be further formed on or in the substrate according to the actual device requirements, not limited to the foregoing components.

[0067] Specifically, the bottom semiconductor layer 108 is disposed between the source electrode SE and the bottom dielectric layer 110 in the vertical direction D1, and the via hole OP penetrates through the support layer 130 and the bottom dielectric layer 110 in the vertical direction D1, exposing the bottom semiconductor layer 108 from its bottom. Thus, the bottom surface of the channel structure SS disposed within the via hole OP physically contacts the bottom semiconductor layer 108. The detailed structure of the channel structure SS includes a channel layer 120 and an insulating layer 122 stacked in sequence in the horizontal directions D2 / D3. Among them, the channel layer 120 further includes a first semiconductor layer 124 and a second semiconductor layer 126, and the insulating layer 122 can be used to indirectly control the composition of the channel structure SS and / or support the channel structure SS. The second semiconductor layer 126 is disposed between the insulating layer 122 and the drain electrode DE in the vertical direction D1, and the first semiconductor layer 124 is disposed around the second semiconductor layer 126 and the insulating layer 122 in the horizontal directions D2 / D3, and has a U-shaped cross-section as shown in Figure 1 In one embodiment, the bottom semiconductor layer 108, the first semiconductor layer 124, and the second semiconductor layer 126 all include, for example, semiconductor materials such as doped polysilicon, doped amorphous silicon, indium zinc oxide (IZO), aluminum zinc oxide (AZO), or indium gallium zinc oxide (IGZO), etc., but are not limited thereto. Moreover, the materials of the bottom semiconductor layer 108, the first semiconductor layer 124, and the second semiconductor layer 126 can be the same as or different from each other. In another embodiment, the dielectric layer 100 and the insulating layer 122 both include, for example, dielectric materials or high-k dielectric materials, and preferably both include silicon oxide, but are not limited thereto.

[0068] On the other hand, a top dielectric layer 146 is disposed on the insulating spacer 140 such that the insulating spacer 140 is sandwiched between the bottom dielectric layer 110 and the top dielectric layer 146 in the vertical direction D1, and the drain DE is disposed within the top dielectric layer 146, but not limited thereto. In detail, for example, the source SE, the gate GE, and the drain DE each include a composite layer structure. For example, the source SE preferably includes a metal barrier layer 102, an electrode layer 104, and a metal barrier layer 106 stacked in sequence in the vertical direction D1. The gate GE includes a metal barrier layer 136 and an electrode layer 138 disposed in sequence on the gate dielectric layer GD in the horizontal directions D2 / D3. The drain DE includes a metal barrier layer 142 and an electrode layer 144 stacked in sequence in the vertical direction D1. In one embodiment, the metal barrier layer 102, the metal barrier layer 106, the metal barrier layer 136, and the metal barrier layer 142, for example, include titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable metal barrier materials, and the materials of the metal barrier layer 102, the metal barrier layer 106, the metal barrier layer 136, and the metal barrier layer 142 may be the same or different from each other, preferably all include titanium nitride, but not limited thereto. In addition, the electrode layer 104, the electrode layer 138, and the electrode layer 144 all include copper (Cu), aluminum (Al), tungsten (W), or other suitable low-resistance metal materials, and the materials of the electrode layer 104, the electrode layer 138, and the electrode layer 144 may be the same or different from each other, preferably all include tungsten, but not limited thereto. In other embodiments, according to the actual device requirements, the setting of the metal barrier layer 102, the metal barrier layer 106, the metal barrier layer 136, and / or the metal barrier layer 142 may be selectively omitted, or alternatively, the metal barrier layer 102, the metal barrier layer 106, the metal barrier layer 136, and / or the metal barrier layer 142 may be selectively made to have a composite film layer, but not limited thereto.

[0069] Under this setting, the channel structure SS of the semiconductor device 10 presents a columnar cross-section extending along the vertical direction D1. Moreover, by means of the first semiconductor layer 124 of the channel layer 120 physically contacting the second semiconductor layer 126 and the bottom semiconductor layer 108 simultaneously, when the gate GE is applied with a threshold voltage, the drain DE and the source SE are electrically connected. The drain DE, the gate dielectric layer GD, the gate GE, the channel structure SS, and the source SE together form a three-dimensional transistor assembly, such that the channel structure SS serves as the vertical channel structure of the three-dimensional transistor assembly, and the gate GE surrounding the outside of the channel structure SS can achieve an effect similar to that of a gate-all-around (GAA). For the semiconductor device 10 according to this embodiment, by additionally providing a support layer 130 on the channel structure SS, the gate dielectric layer GD covering the support layer 130 is located between the gate GE and the channel structure SS in the horizontal directions D2 / D3, and in the vertical direction D1, it is partially located between the support layer 130 and the gate GE and partially located between the gate GE and the bottom dielectric layer 110, and generally presents a spoon-shaped cross-section. Thus, the gate dielectric layer GD can be arranged to surround the gate GE to improve the structural stability and component performance of the gate GE and the channel structure SS, and the semiconductor device 10 has a relatively short channel length, thereby improving its operating performance.

[0070] To enable those of ordinary skill in the technical field to which the present invention pertains to easily understand the semiconductor device of the present invention and implement it accordingly, the following will further describe the manufacturing method of the semiconductor device of the present invention.

[0071] Please refer to Figures 2 to 11 shown, which is a schematic diagram of the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention. First, as Figure 2 and Figure 3As shown, a film formation process is performed, for example, by chemical vapor deposition, physical vapor deposition, or other suitable methods, to sequentially form a source electrode SE (including a metal barrier layer 102, an electrode layer 104, and a metal barrier layer 106 stacked in sequence), a bottom semiconductor layer 108, a first dielectric material layer 112a, a second dielectric material layer 114a, a sacrificial layer 116, and a support material layer 130a on the dielectric layer 100. Then, a perforation R1 is formed that continuously penetrates the support material layer 130a and the sacrificial layer 116, and the second dielectric material layer 114a is exposed from the bottom portion of the perforation R1. In one embodiment, the dielectric layer 100, the first dielectric material layer 112a, the second dielectric material layer 114a, the sacrificial layer 116, and the support material layer 130a all include, for example, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or high-k dielectric materials. Among them, the materials of the dielectric layer 100, the first dielectric material layer 112a, and the sacrificial layer 116 preferably all include silicon oxide, while the materials of the support material layer 130a and the second dielectric material layer 114a preferably include materials different from those of the sacrificial layer 116, such as silicon nitride, etc., but not limited thereto. In another embodiment, the material of the sacrificial layer 116 can also be selected to include silicon nitride, etc., while the materials of the support material layer 130a and the second dielectric material layer 114a preferably include silicon oxide.

[0072] As Figure 4 and Figure 5 shown, another film formation process is performed, for example, by chemical vapor deposition, physical vapor deposition, or other suitable methods, to form a filling layer 118 in the perforation R1. Then, a dry etching process is performed with the aid of a mask (not shown) to partially remove Figure 3 the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a in it, to form at least one channel hole OP that penetrates the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a in the vertical direction D1, and the bottom semiconductor layer 108 is exposed from the bottom portion of the at least one channel hole OP. And when the at least one channel hole OP is formed, a support layer 130 located on the outer sidewall of the at least one channel hole OP is formed synchronously, and a first dielectric layer 112 and a second dielectric layer 114 located between the bottom semiconductor layer 108 and the filling layer 118 in sequence are formed, and then the mask is completely removed. The first dielectric layer 112 and the second dielectric layer 114 together form the bottom dielectric layer 110 of the semiconductor device 10. In one embodiment, the filling layer 118 includes, for example, a dielectric material different from those of the support material layer 130a and the sacrificial layer 116, and preferably all include tetraethyl orthosilicate (TEOS), but not limited thereto.

[0073] AsFigure 6 As shown, a channel structure SS is formed within at least one channel hole OP. The formation of the channel structure SS includes, but is not limited to, the following steps. First, a film formation process is performed again, such as chemical vapor deposition, physical vapor deposition, or other suitable methods, to form a first semiconductor material layer (not shown), which is partially located within at least one channel hole OP and partially outside at least one channel hole OP, such that the first semiconductor material layer conformally covers the top surfaces of the support layer 130 and the filling layer 118, and the side walls of the support layer 130, the sacrificial layer 116, and the bottom dielectric layer 110, and physically contacts the bottom semiconductor layer 108. Then, an insulating material layer (not shown) is formed to at least fill at least one channel hole OP. Next, a part of the insulating material layer is removed until at least one channel hole OP is not fully filled, forming an insulating layer 122 whose top surface is lower than the bottom surface of the support layer 130. Then, a second semiconductor material layer (not shown) is formed to fill the remaining space of at least one channel hole OP and further cover the top surfaces of the support layer 130 and the filling layer 118.

[0074] Then, a planarization process is performed, such as chemical mechanical polishing or other suitable methods, to simultaneously remove the second semiconductor material layer and the first semiconductor material layer formed outside at least one channel hole OP, forming a second semiconductor layer 126 and a first semiconductor layer 124. Thus, the second semiconductor layer 126, the insulating layer 122, and the first semiconductor layer 124 formed within at least one channel hole OP together form the channel structure SS of the semiconductor device 10, wherein the support layer 130 is formed on the side walls of the upper half of the channel structure SS and has a top surface flush with the channel structure SS, as Figure 6 shown. In one embodiment, the first semiconductor material layer and the second semiconductor material layer include, for example, doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide and other semiconductor materials. Preferably, they both include the same semiconductor material as the bottom semiconductor layer 108, but are not limited thereto. The insulating material layer includes, for example, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. Preferably, they all include silicon oxide, but are not limited thereto.

[0075] As Figure 7 shown, a wet etching process is performed to simultaneously remove Figure 6 the filling layer 118 and the sacrificial layer 116 with similar etching selectivity ratios in Figure 7a bottle-shaped cross-section as shown, but not limited thereto. Further, a first gate dielectric material layer 132a and a second gate dielectric material layer 134a are formed in sequence by a film-forming process such as chemical vapor deposition process, physical vapor deposition process or other suitable means, with part formed within the via R2 and part formed outside the via R2. In one embodiment, the first gate dielectric material layer 132a and the second gate dielectric material layer 134a include, for example, different dielectric materials or high-k dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., but not limited thereto.

[0076] As Figure 8 shown, a film-forming process such as chemical vapor deposition process, physical vapor deposition process or other suitable means is performed again to form an electrode barrier material layer 136a with part formed within the via R2 and part formed outside the via R2, and then an electrode material layer 138a that fills the via R2 and further covers the top surface of the support layer 130 and the channel structure SS is formed. In one embodiment, voids V1 can be formed in the electrode material layer 138a by adjusting the process conditions for forming the electrode material layer 138a and / or adjusting the aspect ratio of the via R2, but not limited thereto. The voids V1 formed in the electrode material layer 138a are, for example, lower than the bottom surface of the support layer 130 in the vertical direction D1, but not limited thereto. In another embodiment, the electrode barrier material layer 136a includes, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or other suitable metal barrier materials, and the electrode material layer 138a includes copper, aluminum, tungsten or other suitable low-resistance metal materials, but not limited thereto.

[0077] As Figure 9 shown, a planarization process such as chemical mechanical polishing process or other suitable means is performed to simultaneously remove Figure 8An electrode material layer 138a, an electrode barrier material layer 136a, a second gate dielectric material layer 134a, and a first gate dielectric material layer 132a are formed outside the perforation R2, exposing the bottom surface of the support layer 130. Then, an etching process is performed by means of the support layer 130 to partially remove the electrode material layer 138a, the electrode barrier material layer 136a, the second gate dielectric material layer 134a formed at the bottom of the perforation R2, the first gate dielectric material layer 132a, and a portion of the second dielectric layer 114 below it, forming a perforation R3 with a top surface lower than the top surface of the bottom dielectric layer 110. And when the perforation R3 is formed, a metal barrier layer 136, an electrode layer 138, a first gate dielectric layer 132, and a second gate dielectric layer 134 are simultaneously formed on both sides of the perforation R3. In this way, the metal barrier layer 136 and the electrode layer 138 together form the gate GE of the semiconductor device 10, while the first gate dielectric layer 132 and the second gate dielectric layer 134 together form the gate dielectric layer GD of the semiconductor device 10. It should be noted that the manufacturing method of this embodiment is to first form a channel structure SS with a columnar cross-section in the vertical direction D1 and a support layer 130 on the upper half sidewall of the channel structure SS, and then form the gate dielectric layer GD and the gate GE. Under this operation, the manufacturing of the gate GE does not require the formation of an additional etching mask, but the etching process is performed through the support layer 130. Moreover, the subsequently formed gate dielectric layer GD can also conformally cover the support layer 130 and the lower half sidewall of the channel structure SS, so that the gate dielectric layer GD is arranged around the gate GE, presenting a ladle-shaped cross-section as shown in Figure 9 shown. In this way, the gate dielectric layer GD is manufactured after the channel structure SS is formed, which can effectively avoid structural damage and has relatively optimized device stability. In addition, the gate dielectric layer GD is located between the gate GE and the channel structure SS in the horizontal direction D2 / D3, and is partially located between the support layer 130 and the gate GE and partially located between the gate GE and the bottom dielectric layer 110 in the vertical direction D1, which can provide relatively optimized structural stability and component efficiency for the gate GE.

[0078] As Figure 10 and Figure 11 shown, a film formation process is performed again, such as chemical vapor deposition, physical vapor deposition, or other suitable methods, to form a dielectric material layer (not shown) that is partially formed inside the perforation R3 and partially formed outside the perforation R3. Then, by performing a planarization process, such as chemical mechanical polishing or other suitable methods, the dielectric material layer formed outside the perforation R3 is removed to form an insulating spacer 140 with a bottom surface lower than the gate dielectric layer GD. Then, a drain DE is continuously formed so that the drain DE is formed on the channel structure SS and the support layer 130, and then a top dielectric layer 146 is formed, and the structure as shown inFigure 1 The semiconductor device 10 shown is fabricated to complete the semiconductor device 10 in this embodiment. Figures 5 to 11 Structures not mentioned in Figure 1 are consistent with the description and will not be repeated.

[0079] According to the fabrication method of this embodiment, a channel structure SS is formed in advance before fabricating the gate GE, and a support layer 130 is additionally formed on the sidewalls of the channel structure SS, enabling the fabrication of the gate GE to be etched through the support layer 130. Subsequently, the gate dielectric layer GD is formed to surround the gate GE, thereby conformally covering the support layer 130 and the lower half sidewalls of the channel structure SS, presenting a ladle-shaped cross-section. Thus, the gate dielectric layer GD is located between the gate GE and the channel structure SS in the horizontal directions D2 / D3, and in the vertical direction D1, it is partially located between the support layer 130 and the gate GE and partially located between the gate GE and the bottom dielectric layer 110, providing relatively optimized structural stability and component performance for the gate GE. Accordingly, the semiconductor device 10 fabricated by the fabrication method of this embodiment has a gate GE and a channel structure SS with more optimized component performance, thereby improving the operating performance of the semiconductor device 10.

[0080] Those of ordinary skill in the art to which the present utility model pertains should readily understand that, to meet the requirements of actual products, the semiconductor device and its fabrication method of the present utility model may also have other aspects or can be achieved by other means, not limited to the foregoing. The following will further describe other embodiments or variations of the semiconductor device and its fabrication method of the present utility model. And for simplicity of description, the following description mainly details the differences between each embodiment, and the same parts will not be repeated. In addition, the same components in each embodiment of the present utility model are labeled with the same reference numerals for easy comparison between embodiments.

[0081] Please refer to Figure 12 as shown Figure 12 which is a cross-sectional schematic view of the semiconductor device 20 according to the second embodiment of the present utility model. The structure of the semiconductor device 20 in this embodiment is generally the same as that of the semiconductor device 10 in the foregoing first embodiment, and also includes a source electrode SE, a drain electrode DE, a gate GE, a channel structure SS, a support layer 130, a gate dielectric layer GD, etc., and the same parts will not be repeated here. The main difference between the semiconductor device 20 in this embodiment and the foregoing first embodiment is that when forming as in the foregoing embodiment Figure 9When the perforation R3 shown is formed, by adjusting the process conditions of the etched electrode material layer 138a and the electrode barrier material layer 136a, the etching degrees of the electrode material layer 138a and the electrode barrier material layer 136a are made different, and at least one recessed portion 236a, 238a that is recessed toward the channel structure SS is formed on the gate GE.

[0082] Specifically, in one embodiment, for example, the etching selectivity of the electrode barrier material layer 136a relative to the electrode material layer 138a is adjusted such that the etching degree of the electrode barrier material layer 136a is relatively greater than that of the electrode material layer 138a, and a metal barrier layer 236 having a recessed portion 236a is formed, as Figure 12 shown on the left side. Among them, the recessed portion 236a is, for example, formed between the electrode layer 138 and the support layer 130 in the vertical direction D1, or formed between the bottom dielectric layer 110 and the electrode layer 138, and is located at the end of the gate GE. Thus, the subsequently formed insulating spacer 240 correspondingly has a protruding portion 240a that fills the recessed portion 236a at the end of the gate GE. In another embodiment, the etching selectivity of the electrode material layer 138a relative to the electrode barrier material layer 136a is adjusted such that the etching degree of the electrode material layer 138a is relatively greater than that of the electrode barrier material layer 136a, and an electrode layer 238 having a recessed portion 238a is formed, as Figure 12 shown on the right side. Among them, the recessed portion 238a is, for example, formed at the middle part of the pole GE in the vertical direction D1, such that the subsequently formed insulating spacer 240 correspondingly has a protruding portion 240b that fills the recessed portion 238a at the middle part of the gate GE.

[0083] Under this operation, the semiconductor device 20 fabricated by the manufacturing method of this embodiment can also, by virtue of the setting of the support layer 130, enable the gate dielectric layer GD covering the side wall of the support layer 130 to be disposed around the gate GE, improving the structural stability of the gate GE and the channel structure SS, thereby enhancing the operating performance of the semiconductor device 20.

[0084] In summary, the semiconductor device and its manufacturing method of the present utility model pre-form a channel structure before manufacturing the gate, and additionally form a support layer on the side wall of the channel structure, enabling the gate to be etched through the support layer, and the subsequently formed gate dielectric layer can be disposed around the gate, so as to conformally cover the support layer and the lower half side wall of the channel structure, presenting a ladle-shaped cross-section. In this way, the gate dielectric can provide relatively optimized structural stability and component efficiency for the gate, thereby enhancing the operating performance of the semiconductor device of this embodiment.

[0085] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. For those skilled in the art, the present utility model may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A semiconductor device, characterized in that: include: source; A drain electrode, wherein the source electrode and the drain electrode are stacked in a vertical direction; A gate, disposed between the source and the drain; a channel structure, partially disposed within the gate and connecting the drain and the source; A support layer, disposed on a side wall of the channel structure; as well as The gate dielectric layer is partially disposed between the channel structure and the gate in a horizontal direction, and partially disposed between the support layer and the gate.

2. The semiconductor device according to claim 1, wherein: The gate dielectric layer physically contacts the upper surface, the lower surface and the sidewalls of the gate.

3. The semiconductor device according to claim 1, wherein: The gate dielectric layer physically contacts the lower surface and sidewalls of the support layer.

4. The semiconductor device according to claim 1, wherein: Also includes: An insulating spacer is disposed between the drain and the source, wherein the gate dielectric layer is also partially disposed between the supporting layer and the insulating spacer.

5. The semiconductor device according to claim 4, characterized in that The insulating spacer and the supporting layer include different materials.

6. The semiconductor device according to claim 4, characterized in that The bottom surface of the insulating spacer is lower than the bottom surface of the gate dielectric layer.

7. The semiconductor device according to claim 4, characterized in that The insulating spacer includes at least one protrusion protruding toward the gate.

8. The semiconductor device according to claim 1, wherein: The gate includes at least one recessed portion recessed toward the channel structure.

9. The semiconductor device according to claim 8, characterized in that The at least one recessed portion is disposed at an end of the gate in the vertical direction.

10. The semiconductor device according to claim 8, characterized in that The at least one recessed portion is disposed at a middle portion of the gate in the vertical direction.

11. The semiconductor device according to claim 1, wherein: Also includes: A bottom dielectric layer is disposed between the source and the gate, wherein the channel structure is also partially disposed in the bottom dielectric layer, and the bottom dielectric layer and the support layer include the same material.

12. The semiconductor device according to claim 11, characterized in that The gate dielectric layer is also partially disposed between the gate and the bottom dielectric layer in the vertical direction.

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