Integrated device

Abstract

The embodiment of the utility model provides an integrated device. The integrated device comprises a first thin film transistor arranged above a substrate, a second thin film transistor arranged above the substrate, and a metal barrier layer arranged above the second thin film transistor, wherein the metal barrier layer is configured to block incident radiation from reaching the second thin film transistor, a Fresnel lens disposed over the first thin film transistor, where the Fresnel lens is configured to focus the incident radiation to the first thin film transistor, where the first thin film transistor and the second thin film transistor are configured to be coupled to a differential amplifier, the differential amplifier is operable to detect incident radiation by comparing a first leakage current from the first thin film transistor and a second leakage current from the second thin film transistor. The leakage current of the thin film transistor is relatively low, so that the power consumption of the intrusion detection circuit is also relatively low. The difference between the leakage currents caused by the Fresnel lens allows the intrusion detection circuit to detect intrusion of the electronic device.

Description

Technical Field

[0001] Embodiments of the present utility model relate to an integrated device, and particularly to an integrated device including an optical sensor for intrusion detection. Background Art

[0002] More and more modern electronic devices are integrated into the Internet of Things (IoT). These devices can access a wider network. This access and the information available to the electronic devices make them targets for intrusion attacks and reverse engineering. Intrusion detection is an important element in ensuring the security of the device. Intrusion detection is usually performed using optical detection techniques such that when light irradiates the detection circuit due to, for example, the removal of the outer cover, a signal is detected. Summary of the Utility Model

[0003] Embodiments of the present utility model provide an integrated device including: a first thin-film transistor disposed above a substrate, a second thin-film transistor disposed above the substrate, a metal barrier layer disposed above the second thin-film transistor, and a Fresnel lens disposed above the first thin-film transistor. The metal barrier layer is configured to block incident radiation from reaching the second thin-film transistor, and the Fresnel lens is configured to focus the incident radiation onto the first thin-film transistor. The first thin-film transistor and the second thin-film transistor are configured to be coupled to a differential amplifier, and the differential amplifier is operable to detect the incident radiation by comparing a first leakage current from the first thin-film transistor and a second leakage current from the second thin-film transistor.

[0004] Embodiments of the present utility model provide an integrated device including: a first gate structure and a second gate structure disposed above a substrate, a channel layer disposed above the first gate structure and the second gate structure, a first pair of source / drain regions disposed above the channel layer and along opposite sides of the first gate structure, a second pair of source / drain regions disposed above the channel layer and along opposite sides of the second gate structure, a metal barrier layer disposed above the first pair of source / drain regions, and a Fresnel lens disposed above the second pair of source / drain regions.

[0005] Based on the above, the degree of light focusing on the channel of the first thin-film transistor increases, thereby increasing the leakage current of the first thin-film transistor, such that the difference between the leakage current of the first thin-film transistor and the leakage current of the second thin-film transistor increases. Since the leakage current of the thin-film transistor is low, the power consumption of the intrusion detection circuit is also relatively low. In addition, despite the low power consumption, the increased difference between the leakage currents caused by the Fresnel lens allows the disclosed intrusion detection circuit to accurately detect unnecessary intrusions in the electronic device.

[0006] To make the above features and advantages of the embodiments of the present utility model more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0007] Figure 1A-1B The circuit diagrams and cross-sectional views of the intrusion detection circuits of some embodiments are shown. The intrusion detection circuit includes a first thin film transistor (TFT) and a second TFT covered by a metal barrier layer.

[0008] Figure 2A-2F The cross-sectional view of a TFT with a Fresnel lens of some embodiments is shown.

[0009] Figure 3A-3B The circuit diagrams and cross-sectional views of the intrusion detection circuits of some embodiments are shown. The intrusion detection circuit includes a TFT and a complementary metal-oxide-semiconductor (CMOS) transistor.

[0010] Figure 4A-4B The circuit diagram of the intrusion detection circuit of some embodiments is shown. The intrusion detection circuit includes an array of TFTs.

[0011] Figures 5 to 23 A series of cross-sectional views of a method for forming an intrusion detection circuit are shown. The intrusion detection circuit includes a first thin film transistor (TFT) and a second TFT covered by a metal barrier layer.

[0012] Figure 24 A method for forming an intrusion detection circuit of some embodiments is shown in the form of a flowchart. The intrusion detection circuit includes a first TFT and a second TFT covered by a metal barrier layer.

[0013] Description of the Reference Numerals

[0014] 100a, 300a, 400a, 400b: Circuit diagrams; 100b, 200a, 200b, 200c, 200d, 200e, 200f, 300b, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300: Cross-sectional views; 102: Substrate; 104: First TFT; 106: Second TFT; 108: Differential amplifier; 110a: First input; 110b: Second input; 112: Metal barrier layer; 114a: First gate; 114b: Second gate; 118: Gate dielectric layer; 120: Channel layer; 121a: First channel; 121b: Second channel; 122: Capping layer; 123a, 148a: First source / drain terminal; 123b, 148b: Second source / drain terminal; 124, 405: Fresnel lens; 126: Interconnection structure; 128: First metal wire layer; 130: Metal wire barrier layer; 132: First dielectric; 134: Second dielectric; 136: Third dielectric; 138: Fourth dielectric; 140: Fifth dielectric; 141: Etch stop layer; 144: Incident light; 146: Focused light; 201: Groove; 202: First depth; 203: Focus; 204: Second depth; 205, 208: Tilt angle; 206: Third depth; 207: Top surface; 210: Second interconnection structure; 211: Interconnection dielectric; 212, 316: Metal wire layer; 214, 318: Via layer; 302: First CMOS transistor; 304: Second CMOS transistor; 306: First capacitor; 308: Second capacitor; 402: First array of TFTs; 404: Second array of TFTs; 406: First array of CMOS transistors; 408: Second array of CMOS transistors; 502: First mask layer; 504: First opening; 602: First etching process; 702: Gate material; 1002: Bottom layer; 1004: Intermediate layer; 1006: Top layer; 1008: Second opening; 1102: Second etching process; 1202: Source / drain material; 1402: Third mask layer; 1404: Third opening; 1502: Third etching process; 1602: Metal barrier layer material; 1802: Lens material; 1902: Fourth mask layer; 1904: Fourth opening; 2002: Fourth etching process; 2102: Fifth mask layer; 2104: Fifth opening; 2106: Fifth etching process; 2202: Sixth mask layer; 2204: Sixth etching process; 2400: Method; 2402, 2404, 2406, 2408, 2410, 2412, 2414: Actions; Vdd: Operating voltage; Vg: Gate voltage. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, the formation of a first feature "on" or "above" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may reuse component numbers and / or letters in various examples. Such reuse is for the purpose of simplifying and clearly describing the present disclosure and is not intended to define the relationship between various embodiments and / or configurations.

[0016] In addition, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. In addition to the orientation depicted in the figures, the spatially relative terms also encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used may be interpreted in the same manner.

[0017] Modern electronic devices are increasingly capable of connecting to wireless networks, forming the Internet of Things (IoT). Through the IoT, since data can be exchanged between electronic devices, users can operate electronic devices without physically approaching them. Wireless networks in public places use base stations, repeaters, and other devices physically located near their usage spaces to better meet the growing needs of users. The physical presence of electronic device apparatuses connected to a wireless device network increases the risk of malicious entities accessing the physical components of the wireless device network. Accessing an electronic device connected to a network poses a security risk because the components of the electronic device may be damaged or subverted. Therefore, physical security in devices connected to a network is desired.

[0018] Intrusion detection is an important security component in electronic devices. For example, if a malicious entity gains physical access to an electronic device, the first step in resisting such an intrusion is to detect the occurrence of the intrusion. Some methods of intrusion detection include using light sensing devices such as photoresistors, photodiodes, etc. When the housing of an electronic device is opened, light shines on the light sensing device, sending a signal (such as a current). In some devices, the signal from the light sensing device is compared with a similar light sensing device that does not detect light (such as being covered by an obstruction). In these devices, the current between the two devices may be different before an intrusion. Additionally, in the case of an intrusion, the change in current may be small compared to the normal variation between the devices, making it difficult to detect the intrusion. Further, some light sensing devices have higher leakage currents than others, resulting in more power consumption during operation. Light sensing devices also typically depend on the temperature of the device. A change in the temperature of the device can change the output signal generated by the same input, which may lead to inaccurate readings. There is a need for an intrusion detection circuit that is low power and has a large change in current due to light detection and a small current difference when there is no light detection.

[0019] Various embodiments of the present invention relate to an intrusion detection circuit that includes a first thin film transistor (TFT) and a second TFT, which are respectively configured to function as a light sensing device and a covered non - light sensing device. A Fresnel lens is formed above the first TFT, increasing the degree of focusing of the light that irradiates the channel of the first TFT. A differential amplifier is coupled to the first TFT and the second TFT. The first TFT and the second TFT are configured to detect the leakage current difference between the first TFT and the second TFT. The increased degree of focusing of the light that irradiates the channel of the first TFT increases the leakage current of the first TFT (such as increasing by more than three orders of magnitude), making the difference between the leakage current of the first TFT and the leakage current of the second TFT larger. Since the leakage current of the TFT is low, the power consumption of the intrusion detection circuit is also relatively low. Additionally, despite the low power consumption, the increased difference between the leakage currents caused by the Fresnel lens allows the disclosed intrusion detection circuit to accurately detect an unnecessary intrusion in an electronic device.

[0020] Figure 1A-1B The circuit diagram and cross - sectional view of an intrusion detection circuit of some embodiments are shown. The intrusion detection circuit includes a first thin film transistor (TFT) and a second TFT covered by a metal barrier layer.

[0021] As Figure 1AAs shown in the circuit diagram 100a, the first TFT 104 and the second TFT 106 are coupled to the differential amplifier 108. The first source / drain terminal 123a of the first TFT 104 is coupled to the first input 110a of the differential amplifier 108. The first source / drain terminal 148a of the second TFT 106 is coupled to the second input 110b of the differential amplifier 108. The first gate 114a of the first TFT 104 and the second gate 114b of the second TFT 106 are coupled to the gate line. The gate line biases the gates of the first TFT 104 and the second TFT 106 at the gate voltage Vg. In some embodiments, the gate voltage Vg is between -30 volts and -1 volt, between -3 volts and -0.5 volt, between -10 volts and -2 volts, or another similar range. In some embodiments, the second source / drain terminal 123b of the first TFT 104 and the second source / drain terminal 148b of the second TFT 106 are coupled to the positive rail biased at the operating voltage Vdd. In some embodiments, the operating voltage Vdd is between 8 volts and 12 volts, between 5 volts and 15 volts, between 10 volts and 20 volts, or another similar range. The metal barrier layer 112 extends over the second TFT 106, preventing incident light from reaching the second TFT 106.

[0022] Figure 1B shows a cross-sectional view 100b corresponding to Figure 1A some embodiments. As shown in the cross-sectional view 100b, the first TFT 104 and the second TFT 106 are disposed above the substrate 102. The interconnect structure 126 including the first metal wire layer 128 extends under the first TFT 104. In some embodiments, the metal wire barrier layer 130 surrounds the outer sidewalls of the first metal wire layer 128. The first dielectric 132 surrounds the first metal wire layer 128 under the first gate 114a and the second gate 114b. In some embodiments, the etch stop layer 141 extends between the first gate 114a and the first dielectric 132. The second dielectric 134 surrounds the first gate 114a and the second gate 114b. The gate dielectric layer 118 overlies the first gate 114a and the second gate 114b. The channel layer 120 overlies the gate dielectric layer 118. The channel layer 120 includes a first channel 121a extending between the first source / drain terminal 123a and the second source / drain terminal 123b of the first TFT 104. The channel layer 120 further includes a second channel 121b extending between the first source / drain terminal 148a and the second source / drain terminal 148b of the second TFT 106.

[0023] In some embodiments, the top cover layer 122 extends over the first channel 121a and the second channel 121b. The top cover layer 122 is configured to improve the electrical characteristics of the first TFT 104 and the second TFT 106. For example, in some embodiments, the top cover layer 122 may include a material having a work function smaller than that of the channel layer 120 so as to inject electrons into the channel layer 120, thereby improving the electrical characteristics.

[0024] The first source / drain terminals 123a, 148a and the second source / drain terminals 123b, 148b are disposed over the channel layer 120 and surrounded by a third dielectric 136. A fourth dielectric 138 separates the first and second source / drain terminals (123a, 123b, 148a, 148b) from the Fresnel lens 124 and surrounds the metal barrier layer 112. The metal barrier layer 112 is disposed over the second TFT 106 and has an outer sidewall facing the first TFT 104. That is, the metal barrier layer 112 does not extend directly over the first TFT 104. The Fresnel lens 124 is located directly over the first TFT 104.

[0025] During operation, if an intrusion occurs, the incident light 144 may irradiate the intrusion detection circuit. The incident light 144 is blocked by the metal barrier layer 112 from reaching the second TFT and is focused by the Fresnel lens 124 onto the first channel 121a of the first TFT 104. Then the focused light 146 enters the first channel 121a and excites electrons into the conduction band, increasing the leakage current of the first TFT 104. The increased leakage current causes the voltage detected by the differential amplifier 108 in the first input 110a (see Figure 1A ) to rise, resulting in an output signal from the differential amplifier 108 and successfully detecting the intrusion. The similarity between the first TFT 104 and the second TFT 106 results in the leakage currents of the first TFT 104 and the second TFT 106 differing by less than an order of magnitude until an intrusion occurs.

[0026] The addition of the Fresnel lens further increases the amount of light gathered at the channel layer 120, thereby increasing the number of electrons entering the conduction band and the leakage of the first TFT 104 due to the incident light. The increase in incident light makes the device more sensitive to changes in the light level, and thus better able to detect intrusion. In addition, the duration of the change in leakage current caused by the changing light level is longer than the duration of the detected light level. That is, intrusion can be detected after the incident light stops illuminating the first TFT. This causes the intrusion detection circuit to detect intrusion after recovering from the "off" state or a temporary power outage. Compared with other light sensing technologies, using TFTs (such as the first TFT 104 and the second TFT 106) as light sensing devices has the advantage of reducing the influence of temperature changes. For example, in some configurations, between 30 degrees Celsius and 120 degrees Celsius, the change in the leakage current of the first TFT 104 in the case of intrusion is greater than three orders of magnitude.

[0027] Figure 2A-2F A cross-sectional view of a TFT with a Fresnel lens of some embodiments is shown. It should be understood that the Fresnel lens shown in the following figure is not drawn to scale. That is, the Fresnel lens can be larger and thicker than the following TFT and can be located directly above multiple TFTs.

[0028] As Figure 2A As shown in the cross-sectional view 200a, in some embodiments, the Fresnel lens 124 is a binary Fresnel lens (e.g., a Fresnel lens having an upper surface with two different heights above the bottom of the Fresnel lens). The binary Fresnel lens can be formed by performing one etching to form a groove 201 with a first depth 202 below the top surface 207 of the lens material. The groove 201 of the Fresnel lens 124 is designed to focus light on a selected spectrum and focal point 203. For example, the groove 201 of the Fresnel lens can be designed to focus light with a wavelength of 470 nanometers, 530 nanometers, or other similar wavelengths. In some embodiments, the focal point 203 of the Fresnel lens 124 is between the top surface of the top cover layer 122 and the bottom surface of the channel layer 120. The width of the groove decreases along the radius of the Fresnel lens 124, thereby increasing the angle of light refraction. That is, the farther the incident light is from the center of the Fresnel lens, the more the incident light is refracted. The groove 201 is a concentric ring around the center of the Fresnel lens 124. In some embodiments, other numbers of grooves 201 can be formed in the Fresnel lens 124. For example, two, five, ten, or twenty grooves 201 can be formed in the Fresnel lens 124.

[0029] As Figure 2BAs shown in the cross-sectional view 200b, in some embodiments, the Fresnel lens 124 is a continuous Fresnel lens. By performing multiple etching operations on the continuous lens, a plurality of concentric grooves 201 are formed on the upper surface of the lens, and a continuous Fresnel lens can be formed. The grooves 201 cause the Fresnel lens 124 to have inclined surfaces at different inclination angles 205. For the inclined surfaces near the outer edge of the Fresnel lens 124, the inclination angle 205 is larger, while for the center of the Fresnel lens 124, the inclination angle 205 is smaller. This change in the inclination angle 205 of the inclined surface causes the incident light incident on the inclined surface near the outer edge of the Fresnel lens to be refracted at a larger angle, thereby guiding the incident light to the focal point 203 of the Fresnel lens 124.

[0030] As Figure 2C shown in the cross-sectional view 200c, in some embodiments, the Fresnel lens 124 is a multi-level Fresnel lens. The multi-level Fresnel lens can be formed by performing multiple etching operations to form grooves 201 with a first depth 202, a second depth 204, and a third depth 206 below the top surface 207 of the lens material. The second depth 204 is less than the first depth 202, and the third depth 206 is less than the second depth 204. The multi-level Fresnel lens has an approximate inclination angle 208, which is measured between a horizontal line flush with the first depth 202 and a line between the outermost point of the groove 201 at the first depth 202 and the innermost point of the groove at the top surface of the Fresnel lens 124. The width of the groove 201 decreases when the distance from the center of the Fresnel lens 124 is larger, and the approximate inclination angle 208 increases when the distance from the center of the Fresnel lens 124 is larger. The changes in the groove width and the approximate inclination angle 208 cause the incident light impinging on the Fresnel lens near the outer edge to be refracted at a larger angle, thereby guiding the incident light to the focal point 203 of the Fresnel lens 124.

[0031] As Figure 2D shown in the cross-sectional view 200d, in some embodiments, the top cover layer (see Figure 1B ) is not arranged above the channel layer 120. In some embodiments, the material of the channel layer 120 can detect incident light in the visible light spectrum without including the top cover layer 122. The focal point 203 of the Fresnel lens 124 is between the top surface and the bottom surface of the channel layer 120.

[0032] As Figure 2E shown in the cross-sectional view 200e, in some embodiments, the first source / drain terminal 123a and the second source / drain terminal 123b extend directly above the top cover layer 122. The top cover layer contacts the outer sidewalls and the lower surface of the first source / drain terminal 123a and the second source / drain terminal 123b.

[0033] As shown Figure 2F in the cross-sectional view 200f, in some embodiments, the second inner connection structure 210 extends between the third dielectric 136 and the fourth dielectric 138. The second inner connection structure 210 includes one or more metal wire levels 212 and one or more via levels 214 in an inner connection dielectric 211. The first source / drain terminals 123a, 148a and the second source / drain terminals 123b, 148b are coupled to the one or more metal wire levels 212 through the one or more via levels 214. The one or more metal wire levels 212 electrically couple the first and second source / drain terminals (123a, 123b, 148a, 148b) to other components of the intrusion detection circuit, such as the positive rail biased at the operating voltage Vdd (see Figure 1A ) and the first and second inputs (see Figure 1A 110a and 110b of

[0034] Figure 3A-3B The circuit diagrams and cross-sectional views of the intrusion detection circuit in some embodiments are shown. The intrusion detection circuit includes TFTs and complementary metal oxide semiconductor (CMOS) transistors.

[0035] As shown Figure 3A in the circuit diagram 300a, the first CMOS transistor 302 is coupled to the first input 110a of the differential amplifier 108, and the second CMOS transistor 304 is coupled to the second input 110b of the differential amplifier 108. In addition, the first capacitor 306 is coupled to the first input 110a and the second capacitor 308 is coupled to the second input 110b. The gates of the first CMOS transistor 302 and the second CMOS transistor 304 have a negative bias voltage, causing the first CMOS transistor 302 and the second CMOS transistor 304 to transfer leakage current to the first and second inputs (110a, 110b). During operation, the first CMOS transistor 302 and the second CMOS transistor 304 have substantially equal leakage currents, which are greater than the leakage currents of the first TFT 104 and the second TFT 106. The mismatch of the leakage currents causes charge to accumulate at the first capacitor 306 and the second capacitor 308. The charges on the first capacitor 306 and the second capacitor 308 cause a voltage to be read at the differential amplifier. Since the charges on the first capacitor 306 and the second capacitor 308 are substantially equal, the voltages read by the differential amplifier at the first input 110a and the second input 110b are also equal.

[0036] If an intrusion occurs, incident light irradiates the first TFT 104 and the metal barrier layer 112. The incident light increases the leakage current of the first TFT 104 by three or more orders of magnitude. The leakage current reduces the charge at the first capacitor 306, thereby reducing the voltage read by the differential amplifier at the first input 110a. The metal barrier layer 112 prevents the second TFT 106 from being affected by the incident light, thereby maintaining the leakage current of the second TFT 106 before the intrusion. The charge at the second capacitor 308 remains unchanged, and the voltage read at the second input 110b also remains unchanged. The difference between the voltage read at the first input 110a and the voltage read at the second input 110b causes a signal to be output from the differential amplifier 108.

[0037] As Figure 3B shown in the cross-sectional view 300b, the first CMOS transistor 302 and the second CMOS transistor 304 are on the substrate 102. In other embodiments, the first CMOS transistor 302 and the second CMOS transistor 304 are above the substrate within the interconnect structure 126. In some embodiments, the first CMOS transistor 302 and the second CMOS transistor 304 are or include one of a planar FET, a finFET, and a gate-all-around (GAA) device. The first CMOS transistor 302 and the second CMOS transistor 304 are coupled to the interconnect structure 126. In some embodiments, the interconnect structure 126 includes one or more additional metal wire levels 316 and one or more via levels 318. The additional metal wire levels 316 provide lateral connections for components within the interconnect structure 126, and the via levels 318 provide vertical connections between components within the interconnect structure 126. In some embodiments, the first capacitor 306 and the second capacitor 308 are within the interconnect structure 126. It should be understood that the first capacitor 306 and the second capacitor 308 are not limited to three-dimensional MIM capacitors. In some embodiments, the first capacitor 306 and the second capacitor 308 may each be or include a metal oxide semiconductor capacitor (MOSCAP), a two-dimensional metal-insulator-metal (MIM) capacitor, or another type of capacitor. In a further embodiment, the first capacitor 306 and the second capacitor 308 are between the first CMOS transistor 302 and the first TFT 104. In some embodiments, the first CMOS transistor 302 and the second CMOS transistor 304 are formed simultaneously to reduce the difference in leakage current due to minor variations in the process used.

[0038] In some embodiments, the top cover layer 122 extends above the channel layer 120. The top cover layer 122 is or includes a material having a smaller bandgap than the material of the channel layer 120 within a certain wavelength range. The smaller bandgap of the top cover layer 122 can expand the spectrum of light detected by the first TFT 104. In other embodiments, the material of the channel layer 120 can detect incident light in the desired spectrum without including the top cover layer 122. In some embodiments, the desired spectrum is in the visible light range. In some embodiments, the channel layer 120 is or includes indium gallium zinc oxide (IGZO), indium tungsten zinc oxide (IWZO), etc. or a combination of the foregoing. In some embodiments, the top cover layer 122 is or includes selenium (Se), tin oxide (SnO), etc. or a combination of the foregoing. When the top cover layer 122 extends directly between the source / drain terminals and spans the channel layer 120, the material of the top cover layer 122 also affects the leakage current of the first and second TFTs (104, 106). The material of the top cover layer 122 is selected to maintain the temperature stability of the leakage current of the first and second TFTs. In other embodiments, the channel layer 120 is doped with a material having a smaller bandgap than the material of the channel layer 120 without forming the top cover layer 122.

[0039] Figure 4A-4B The circuit diagram of an intrusion detection circuit according to some embodiments is shown. The intrusion detection circuit includes an array of TFTs.

[0040] As Figure 4A shown in the circuit diagram 400a of, in some embodiments, the first array 402 of TFTs and the second array 404 of TFTs are coupled to a differential amplifier 108. The first array 402 of TFTs has a first combined leakage current, and the second array 404 of TFTs has a second combined leakage current. The first array 402 of TFTs and the second array 404 of TFTs have the same number of TFTs to reduce the difference between the first combined leakage current and the second combined leakage current. The metal barrier layer 112 is directly above the TFTs in the second array 404 of TFTs. During operation, if one TFT in the first array 402 of TFTs or the second array 404 of TFTs fails or becomes inoperable, the other TFTs in the array will maintain the operation of the intrusion detection circuit. In some embodiments, an array 405 of Fresnel lenses is arranged above the first array 402 of TFTs. In some embodiments, the number of Fresnel lenses in the array 405 of Fresnel lenses is less than the number of TFTs in the first array 402 of TFTs. In other embodiments, a single Fresnel lens (see Figure 1B 124 in) is formed above the first array 402 of TFTs.

[0041] As Figure 4BAs shown in the circuit diagram 400b, in some embodiments, the first array 406 of CMOS transistors and the second array 408 of CMOS transistors are coupled to the differential amplifier 108. The first array 406 of CMOS transistors has a third combined leakage current, and the second array 408 of CMOS transistors has a fourth combined leakage current. The number of CMOS transistors in the first array 406 of CMOS transistors and the second array 408 of CMOS transistors is equal to reduce the difference between the third combined leakage current and the fourth combined leakage current. During operation, if one of the CMOS transistors in the first array 406 of CMOS transistors or the second array 408 of CMOS transistors fails or becomes inoperable, the other CMOS transistors in the array will maintain the operation of the intrusion detection circuit.

[0042] Referring to Figures 5 to 23 , a cross-sectional view of a method of forming an intrusion detection circuit, the intrusion detection circuit including a first thin film transistor (TFT) and a second TFT covered by a metal barrier layer. Although Figures 5 to 23 described as a series of actions, it should be understood that these actions are not restrictive since the order of the actions can be changed in other embodiments and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted in whole or in part.

[0043] As Figure 5 shown in the cross-sectional view 500, provide, form, or otherwise obtain an interconnect structure 126 within a first dielectric 132 above a substrate 102. Then a first mask layer 502 is formed above a second dielectric 134. In some embodiments, the first mask layer 502 can be, for example, a photoresist. In some embodiments, the first mask layer 502 can be formed using one of a deposition process or a spin coating process. Then the first mask layer 502 is patterned to form a first opening 504 in the first mask layer 502. In some embodiments, the first mask layer 502 is patterned using lithography or the like. The first opening 504 overlies a first metal wire level 128 of the interconnect structure 126. In some embodiments, the first dielectric 132 and the second dielectric 134 are or include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), a low dielectric constant dielectric material, or an ultra-low dielectric constant dielectric material. In some embodiments, the interconnect structure 126 is or includes a metal, such as aluminum, copper, or a combination thereof.

[0044] As Figure 6As shown in the cross-sectional view 600, a first etching process 602 is performed to remove the portion of the second dielectric 134 exposed by the first opening 504, so as to extend the first opening 504 into the second dielectric 134. In some embodiments, the first etching process 602 is a dry etching (such as plasma dry etching). The first etching process 602 exposes the upper surface of the first metal line layer 128 of the interconnect structure 126. Subsequently, the first mask layer 502 is removed using, for example, a lift-off process or an ashing process.

[0045] As Figure 7 As shown in the cross-sectional view 700, a gate material 702 is formed in the first opening 504 (as shown by the dashed line). In some embodiments, the gate material 702 is or includes a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), etc. or a combination of the foregoing. The gate material 702 can be formed using one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0046] As Figure 8 As shown in the cross-sectional view 800, the portion of the gate material (such as Figure 7 702) above the upper surface of the second dielectric 134 is removed to form the first and second gates 114a, 114b. In some embodiments, a planarization process (such as a chemical mechanical planarization (CMP) process) is used to remove the said portion of the gate material.

[0047] As Figure 9 As shown in the cross-sectional view 900, the gate dielectric layer 118, the channel layer 120, the capping layer 122, and the third dielectric 136 are continuously deposited above the first gate 114a and the second gate 114b. In some embodiments, the gate dielectric layer 118, the channel layer 120, the capping layer 122, and the third dielectric 136 are deposited using one or more of ALD, CVD, PVD, etc.

[0048] As Figure 10As shown in the cross-sectional view 1000, a second mask layer is formed over the third dielectric 136. In some embodiments, the second mask layer may include a three-layer mask formed continuously over the third dielectric 136, the three-layer mask including a bottom layer 1002, an intermediate layer 1004, and a top layer 1006. In some embodiments, the bottom layer 1002, the intermediate layer 1004, and the top layer 1006 are formed using one or more deposition or spin-coating processes. In some embodiments, the bottom layer 1002 and the intermediate layer 1004 may include dielectrics (such as spin-on carbon, anti-reflective coatings, etc.) and the top layer 1006 is or includes a photoresist. The top layer 1006 may be patterned to form a second opening 1008 in the top layer 1006. In some embodiments, the top layer 1006 is patterned using photolithography or the like. The second opening 1008 overlies the outer sidewalls of the first and second gates (114a, 114b).

[0049] As Figure 11 As shown in the cross-sectional view 1100, a second etching process 1102 is performed to remove portions of the intermediate layer 1004, the bottom layer 1002, the third dielectric 136, and the top cover layer 122 directly beneath the second opening 1008 to extend the second opening 1008 into the top cover layer 122. In some embodiments, the second etching process 1102 is a dry etch (such as plasma dry etch). The second etching process 1102 exposes the upper surface of the channel layer 120. Subsequently, one or more of a lift-off process, an ashing process, or a planarization process is used to remove the top layer 1006, the intermediate layer 1004, and the bottom layer 1002.

[0050] As Figure 12 As shown in the cross-sectional view 1200, source / drain material 1202 is deposited in the second opening 1008 and over the third dielectric 136. In some embodiments, the source / drain material 1202 contacts the upper surface of the channel layer 120 and the outer sidewalls of the top cover layer 122. The source / drain material 1202 may be formed using one or more of ALD, CVD, PVD, etc.

[0051] As Figure 13 As shown in the cross-sectional view 1300, portions of the source / drain material (such as Figure 12 1202) above the upper surface of the third dielectric 136 are removed to form a first source / drain terminal (123a, 148a) and a second source / drain terminal (123b, 148b). In some embodiments, a planarization process (such as a CMP process) is used to remove the said portions of the source / drain material.

[0052] As Figure 14As shown in the cross-sectional view 1400, a fourth dielectric 138 and a third mask layer 1402 are formed over the third dielectric 136. In some embodiments, before forming the fourth dielectric 138, second interconnect structures 210 and interconnect dielectrics 211 are formed over the third dielectric 136. Then, the third mask layer 1402 is patterned to form a third opening 1404 corresponding to the metal barrier layer (see Figure 1B 112) over the fourth dielectric 138. In some embodiments, the third mask layer 1402 is patterned using photolithography or the like. In some embodiments, one or more metal line levels 212 and one or more via levels 214 are formed using one or a combination of CVD, ALD, PVD, electrochemical plating, one or more damascene processes, one or more dual damascene processes, etc.

[0053] As Figure 15 shown in the cross-sectional view 1500, a third etching process 1502 is performed to remove a portion of the fourth dielectric 138 corresponding to the third opening 1404 and extend the third opening 1404 into the fourth dielectric 138. In some embodiments, the third etching process 1502 is a dry etching (e.g., plasma dry etching). Subsequently, the third mask layer 1402 is removed using, for example, a lift-off process or an ashing process.

[0054] As Figure 16 shown in the cross-sectional view 1600, a metal barrier layer material 1602 is formed in the third opening 1404 (shown in dashed lines) and over the fourth dielectric 138. The metal barrier layer material 1602 can be formed using one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0055] As Figure 17 shown in the cross-sectional view 1700, a portion of the metal barrier layer material (e.g., Figure 16 1602) over the upper surface of the fourth dielectric 138 is removed to form the metal barrier layer 112. In some embodiments, a planarization process (e.g., a chemical mechanical planarization (CMP) process) is used to remove the said portion of the metal barrier layer material.

[0056] As Figure 18As shown in the cross-sectional view 1800, a lens material 1802 is formed over the fourth dielectric 138. The lens material 1802 is formed using a deposition process, a spin coating process, a spraying process, etc. In some embodiments, the lens material 1802 is or includes an i-line or deep ultraviolet (DUV) photoresist (non-limiting). In some embodiments, the fourth dielectric is or includes an acrylic resist, a polyimide resist, an epoxy resin resist, a polyorganosiloxane, a polyorganosilicate, etc. The absolute refractive index of the lens material 1802 is greater than 1.6.

[0057] As Figure 19 As shown in the cross-sectional view 1900, a fourth mask layer 1902 is formed over the lens material 1802. In some embodiments, the fourth mask layer 1902 can be, for example, a photoresist. In some embodiments, the fourth mask layer 1902 can be formed using one of a deposition process or a spin coating process. The fourth mask layer 1902 is then patterned to form a fourth opening 1904 in the fourth mask layer 1902. In some embodiments, the fourth mask layer 1902 is patterned using photolithography or the like.

[0058] As Figure 20 As shown in the cross-sectional view 2000, a fourth etching process 2002 is performed to remove the portion of the lens material 1802 that is exposed by the fourth opening 1904. In some embodiments, the fourth etching process 2002 is a dry etching (e.g., plasma dry etching). The lens material 1802 has a top surface, and the fourth etching process 2002 results in the upper surface of the lens material 1802 being at a third depth 206 below the top surface (see Figure 2C ). Subsequently, the fourth mask layer 1902 is removed using, for example, a lift-off process or an ashing process.

[0059] As Figure 21As shown in the cross-sectional view 2100, a fifth mask layer 2102 is formed over the lens material 1802. The fifth mask layer 2102 is then patterned to form a fifth opening 2104 in the fifth mask layer 2102. In some embodiments, the fifth mask layer 2102 is patterned using photolithography or the like. A fifth etching process 2106 is then performed to remove the portion of the lens material 1802 that is exposed by the fifth opening 2104. The portion of the lens material 1802 that is exposed by the fifth opening 2104 includes both the portion of the lens material 1802 at the top surface and the portion of the upper surface of the lens material 1802 that is at the third depth 206. The fifth etching process 2106 removes the exposed portion of the material such that the lens material 1802 has a portion with an upper surface at a second depth 204 that is greater than the third depth 206 and a portion at a first depth 202 that is greater than the second depth 204. The difference between the first height and the second height is substantially equal to the difference between the third height and the fourth height. The fifth mask layer 2102 is then removed using, for example, a lift-off process or an ashing process.

[0060] As Figure 22 shown in the cross-sectional view 2200, a sixth mask layer 2202 is formed over the lens material (e.g., Figure 21 1802). The sixth mask layer 2202 is then patterned to expose the portion of the lens material that is not part of the Fresnel lens 124. In some embodiments, the sixth mask layer 2202 is patterned using photolithography or the like. A sixth etching process 2204 is then performed to remove the exposed portion of the lens material and result in the formation of the Fresnel lens. The sixth mask layer 2202 is then removed using, for example, a lift-off process or an ashing process.

[0061] As Figure 23 shown in the cross-sectional view 2300, a fifth dielectric 140 is formed over the Fresnel lens 124. The fifth dielectric 140 can be formed using one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, a planarization process (e.g., a CMP process) is performed to remove the upper portion of the fifth dielectric 140, resulting in a substantially smooth upper surface.

[0062] Figure 24Method 2400 for forming an intrusion detection circuit is shown in the form of a flowchart. The intrusion detection circuit includes a first TFT and a second TFT covered by a metal barrier layer. Although this method and other methods shown and / or described in embodiments of the present invention are shown as a series of actions or events, it should be understood that the embodiments of the present invention are not limited to the shown order or actions. Therefore, in some embodiments, the actions may be performed in an order different from the shown order and / or may be performed simultaneously. In addition, in some embodiments, the shown actions or events may be subdivided into multiple actions or events, and these actions or events may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the shown actions or events may be omitted, and other actions or events not shown may be included.

[0063] In operation 2402, a first dielectric layer formed over a substrate is patterned to form a first gate opening and a second gate opening. For example, refer to Figure 5 and Figure 6 .

[0064] In operation 2404, a first gate is formed within the first gate opening and a second gate is formed within the second gate opening. For example, refer to Figure 7 and Figure 8 .

[0065] In operation 2406, a first channel is formed over the first gate and the second gate. For example, refer to Figure 9 .

[0066] In operation 2408, a first source / drain terminal is formed within a second dielectric layer on a top surface of the first channel. For example, refer to Figure 10 , 11 , 12 and 13.

[0067] In operation 2410, a blocking layer is formed over the second dielectric layer and directly over the first gate. For example, refer to Figure 14 , 15 , 16 and 17.

[0068] In operation 2412, a lens material is formed over the second dielectric layer and directly over the second gate. For example, refer to Figure 18 .

[0069] In operation 2414, one or more etching processes are performed on the lens material to form a Fresnel lens over the first channel, the Fresnel lens having a focal point above a bottom surface of the first channel. For example, refer to Figure 20 , 21 and 22.

[0070] Some embodiments relate to an integrated device, the integrated device comprising: a first thin film transistor (TFT) disposed above a substrate; a second TFT disposed above the substrate; a metal barrier layer disposed above the second TFT, wherein the metal barrier layer is configured to block incident radiation from reaching the second TFT; a Fresnel lens disposed above the first TFT, wherein the Fresnel lens is configured to focus the incident radiation onto the first TFT; and wherein the first TFT and the second TFT are configured to be coupled to a differential amplifier, the differential amplifier being operable to detect the incident radiation by comparing a first leakage current from the first TFT and a second leakage current from the second TFT.

[0071] In some embodiments, the first thin film transistor includes: a gate disposed above the substrate, a channel disposed above the gate, a first source / drain terminal, and a second source / drain terminal separated from the first source / drain terminal, wherein the channel includes a first material having a topmost surface below the first source / drain terminal and the second source / drain terminal, and the channel is configured to laterally receive the incident radiation between the first source / drain terminal and the second source / drain terminal. In some embodiments, the integrated device further includes a top cover layer including a second material disposed above the channel and between the first source / drain terminal and the second source / drain terminal, wherein the first material is different from the second material and the second material has a smaller bandgap than the first material within a wavelength range. In some embodiments, the Fresnel lens has a focal point within the first thin film transistor. In some embodiments, the Fresnel lens includes a top surface, a first upper surface at a first depth below the top surface, and a second upper surface at a second depth less than the first depth. In some embodiments, the first upper surface and the second upper surface are substantially parallel to the top surface. In some embodiments, the first thin film transistor includes a channel disposed below the Fresnel lens and a top cover layer disposed between the channel and the Fresnel lens, wherein the focal point of the Fresnel lens is between the top surface of the top cover layer and the bottom surface of the channel. In some embodiments, the integrated device further includes: a first input of the differential amplifier coupled to the first thin film transistor, a first complementary metal oxide semiconductor transistor coupled to the first input, a second input of the differential amplifier coupled to the second thin film transistor, a second complementary metal oxide semiconductor transistor coupled to the second input, a first capacitor coupled to the first input, and a second capacitor coupled to the second input. In some embodiments, the integrated device further includes: a first array of thin film transistors in parallel with the first thin film transistor and a second array of thin film transistors in parallel with the second thin film transistor, wherein the Fresnel lens overlies the first array of thin film transistors and the metal barrier layer covers the second array of thin film transistors.

[0072] Other embodiments relate to an integrated device, the integrated device including: a first gate structure and a second gate structure disposed above a substrate; a channel layer disposed above the first gate structure and the second gate structure; a first pair of source / drain regions disposed above the channel layer and along opposite sides of the first gate structure; a second pair of source / drain regions disposed above the channel layer and along opposite sides of the second gate structure; a metal barrier layer disposed above the first pair of source / drain regions; and a Fresnel lens disposed above the second pair of source / drain regions.

[0073] In some embodiments, the integrated device further includes: a first complementary metal-oxide semiconductor transistor coupled to a first input of a differential amplifier, a second complementary metal-oxide semiconductor transistor coupled to a second input of the differential amplifier, a first capacitor coupled to the first input, and a second capacitor coupled to the second input, wherein a first source / drain region of the first pair of source / drain regions is coupled to the first input, and a second source / drain region of the second pair of source / drain regions is coupled to the second input. In some embodiments, the first capacitor and the second capacitor are configured to collect leakage currents of the first complementary metal-oxide semiconductor transistor and the second complementary metal-oxide semiconductor transistor, respectively, thereby generating the first input having a first voltage and the second input having a second voltage. In some embodiments, the channel layer is configured to absorb incident light between the first pair of source / drain regions. In some embodiments, the Fresnel lens extends above the first pair of source / drain regions at a first height measured from the substrate, and the metal barrier layer extends above the second pair of source / drain regions at a second height less than the first height.

[0074] Another embodiment relates to a method of forming an integrated device, including: patterning a first dielectric layer formed over a substrate to form a first gate opening and a second gate opening; forming a first gate in the first gate opening and a second gate in the second gate opening; forming a first channel over the first gate and the second gate; forming a first source / drain terminal in a second dielectric layer on a top surface of the first channel; forming a blocking layer over the second dielectric layer and directly over the first gate; forming a lens material over the second dielectric layer and directly over the second gate; and performing one or more etching processes on the lens material to form a Fresnel lens over the first channel, the Fresnel lens having a focal point above a bottom surface of the first channel.

[0075] In some embodiments, the method further includes forming a top cover layer over the first channel before forming the source / drain terminals, wherein the source / drain terminals extend along the sidewalls of the top cover layer, and the focus of the Fresnel lens is between the top surface of the top cover layer and the bottom surface of the first channel. In some embodiments, the source / drain terminals extend over the top cover layer. In some embodiments, the barrier layer is formed in the third dielectric layer and has a top surface flush with the top surface of the third dielectric layer, and the lens material is formed on the top surface of the third dielectric layer. In some embodiments, the method further includes forming a differential amplifier over the substrate, the differential amplifier having a first input and a second input and forming an interconnect structure that couples a first source / drain terminal of the source / drain terminals to the first input and couples a second source / drain terminal of the source / drain terminals to the second input. In some embodiments, the source / drain terminals extend over the first gate.

[0076] It should be understood that in the description of the embodiments of the present invention and the appended claims, the terms "first", "second", "second", "third", etc. are only general identifiers used for convenience of description to distinguish different terms for convenience of description to distinguish different components of a figure or a series of figures. As such, these terms do not imply any chronological order or structural proximity of these components and are not intended to describe corresponding components in different illustrated embodiments and / or unillustrated embodiments. For example, the "first dielectric layer" described in connection with the first figure may not necessarily correspond to the "first dielectric layer" described in connection with another figure and may not necessarily correspond to the "first dielectric layer" in an unillustrated embodiment.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and not to limit them; although the embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated device, characterized in that: include: A first thin film transistor is arranged above the substrate; A second thin film transistor is arranged above the substrate; a metal barrier layer disposed above the second thin film transistor, wherein the metal barrier layer is configured to block incident radiation from reaching the second thin film transistor; as well as a Fresnel lens disposed above the first thin film transistor, wherein the Fresnel lens is configured to focus the incident radiation onto the first thin film transistor; as well as The first thin film transistor and the second thin film transistor are configured to be coupled to a differential amplifier, the differential amplifier being operable to detect the incident radiation by comparing a first leakage current from the first thin film transistor and a second leakage current from the second thin film transistor.

2. The integrated device according to claim 1, characterized in that: The first thin film transistor comprises: A gate, disposed above the substrate; A channel, disposed above the gate; a first source / drain terminal; and a second source / drain terminal separated from the first source / drain terminal; Wherein the channel comprises a first material having a topmost surface below the first source / drain terminal and the second source / drain terminal, the channel being configured to receive the incident radiation laterally between the first source / drain terminal and the second source / drain terminal.

3. The integrated device according to claim 1, characterized in that: The Fresnel lens has a focal point within the first thin film transistor.

4. The integrated device according to claim 3, characterized in that: The Fresnel lens includes a top surface, a first upper surface at a first depth below the top surface, and a second upper surface at a second depth less than the first depth.

5. The integrated device according to claim 3, characterized in that: The first thin film transistor comprises: a channel arranged below the Fresnel lens; and A top cover layer is arranged between the channel and the Fresnel lens, wherein the focus of the Fresnel lens is between the top surface of the top cover layer and the bottom surface of the channel.

6. The integrated device according to claim 1, characterized in that: Also includes: A first input of the differential amplifier is coupled to the first thin film transistor; a first complementary metal oxide semiconductor transistor coupled to the first input; A second input of the differential amplifier is coupled to the second thin film transistor; a second complementary metal oxide semiconductor transistor coupled to the second input; a first capacitor coupled to the first input; as well as A second capacitor is coupled to the second input.

7. The integrated device according to claim 1, characterized in that: Also includes: a first array of thin film transistors connected in parallel with the first thin film transistors, wherein the Fresnel lens overlies the first array of thin film transistors; as well as A second array of thin film transistors is connected in parallel with the second thin film transistors, wherein the metal barrier layer covers the second array of thin film transistors.

8. An integrated device, characterized in that: include: A first gate structure and a second gate structure are arranged above the substrate; A channel layer, disposed above the first gate structure and the second gate structure; a first pair of source / drain regions disposed above the channel layer and along opposite sides of the first gate structure; a second pair of source / drain regions disposed above the channel layer and along opposite sides of the second gate structure; a metal barrier layer disposed above the first pair of source / drain regions; as well as A Fresnel lens is arranged above the second pair of source / drain regions.

9. The integrated device according to claim 8, characterized in that Also includes: a first complementary metal oxide semiconductor transistor coupled to a first input of the differential amplifier; a second complementary metal oxide semiconductor transistor coupled to a second input of the differential amplifier; a first capacitor coupled to the first input; as well as A second capacitor is coupled to the second input, wherein a first source / drain region of the first pair of source / drain regions is coupled to the first input, and a second source / drain region of the second pair of source / drain regions is coupled to the second input.

10. The integrated device according to claim 8, characterized in that The Fresnel lens extends over the first pair of source / drain regions at a first height measured from the substrate, and the metal barrier layer extends over the second pair of source / drain regions at a second height less than the first height.

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