Conversion circuit, conversion system and electronic equipment

Abstract

The utility model provides a conversion circuit, a conversion system and electronic equipment, and relates to the technical field of electronic circuits. The conversion circuit comprises a conversion module, a first buffer module and a second buffer module, the conversion module is connected with the half-duplex communication interface through the first buffer module and is connected with the full-duplex communication interface through the second buffer module; the conversion module is configured to convert a first signal sent by the full-duplex communication interface into a signal adaptive to the half-duplex communication interface, and send the signal adaptive to the half-duplex communication interface to the half-duplex communication interface; the first buffer module is configured to buffer interaction data between the conversion module and the half-duplex communication interface; the conversion module is further configured to convert a second signal sent by the half-duplex communication interface into a signal adaptive to the full-duplex communication interface, and send the signal adaptive to the full-duplex communication interface to the full-duplex communication interface; the second buffer module is configured to buffer interaction data between the conversion module and the full duplex communication interface.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a conversion circuit, a conversion system and an electronic device. Background Art

[0002] SIM (Subscriber Identity Module) cards have been widely used in various mobile phone chip interfaces. Currently, some chips do not have interfaces that can directly support SIM, thus limiting the application scope of SIM cards. Utility Model Content

[0003] The present application provides a conversion circuit, a conversion system and an electronic device to solve the problem in the prior art that some chips do not have an interface that can directly support SIM cards, thereby limiting the application scope of SIM cards.

[0004] In the first aspect, the present application provides a conversion circuit for connecting a full-duplex communication interface and a half-duplex communication interface, the conversion circuit comprising: a conversion module, a first buffer module, and a second buffer module; the conversion module is connected to the half-duplex communication interface through the first buffer module, and is connected to the full-duplex communication interface through the second buffer module; the conversion module is configured to convert a first signal sent by the full-duplex communication interface into a signal adapted to the half-duplex communication interface, and send the signal adapted to the half-duplex communication interface to the half-duplex communication interface; the first buffer module is configured to cache the interaction data between the conversion module and the half-duplex communication interface; the conversion module is also configured to convert a second signal sent by the half-duplex communication interface into a signal adapted to the full-duplex communication interface, and send the signal adapted to the full-duplex communication interface to the full-duplex communication interface; the second buffer module is configured to cache the interaction data between the conversion module and the full-duplex communication interface.

[0005] In the embodiment of the present application, the first signal sent by the full-duplex communication interface is converted into the signal required by the opposite end through the conversion module, and the second signal sent by the opposite end is converted into the signal required by the full-duplex communication interface, so that the full-duplex communication interface and the half-duplex communication interface can communicate normally. Therefore, the chip and the SIM card can communicate normally, and the application range of the SIM card is improved.

[0006] In combination with the technical solution provided in the first aspect above, in some possible implementations, the conversion module includes: a first signal conversion module and a second signal conversion module; the first signal conversion module is respectively connected to the first buffer module and the second buffer module, and the second signal conversion module is respectively connected to the first buffer module and the second buffer module; the first signal conversion module is used to connect the full-duplex communication interface, and the first signal conversion module is configured to send the first signal sent by the full-duplex communication interface to the second signal conversion module via the first buffer module, and convert the second signal sent by the second signal conversion module via the first buffer module into a signal adapted to the full-duplex communication interface, and send it to the full-duplex communication interface; the second signal conversion module is used to connect the half-duplex communication interface, and the second signal conversion module is configured to convert the first signal into a signal adapted to the half-duplex communication interface, and send it to the half-duplex communication interface, and send the second signal sent by the half-duplex communication interface to the first signal conversion module via the first buffer module.

[0007] In an embodiment of the present application, the first signal conversion module is used to convert the second signal sent by the second signal conversion module via the first buffer module into a signal adapted to the full-duplex communication interface, and the second signal conversion module is used to convert the first signal into a signal adapted to the half-duplex communication interface, thereby realizing the separate execution of the two signal conversions and preventing signal conversion errors.

[0008] In combination with the technical solution provided in the first aspect above, in some possible implementations, the conversion module includes: a first signal conversion module and a second signal conversion module; the first signal conversion module is respectively connected to the first buffer module and the second buffer module, and the second signal conversion module is respectively connected to the first buffer module and the second buffer module; the first signal conversion module is used to connect the full-duplex communication interface, and the first signal conversion module is configured to convert the first signal sent by the full-duplex communication interface into a signal adapted to the half-duplex communication interface, and send it to the second signal conversion module via the first buffer module, and send the first signal sent by the second signal conversion module via the first buffer module to the full-duplex communication interface; the second signal conversion module is used to connect the half-duplex communication interface, and the second signal conversion module is configured to send the first signal to the half-duplex communication interface, and convert the second signal sent by the half-duplex communication interface into a signal adapted to the full-duplex communication interface, and send it to the first signal conversion module via the second buffer module.

[0009] In the embodiment of the present application, the first signal conversion module is used to convert the first signal sent by the full-duplex communication interface into a signal adapted to the half-duplex communication interface, and the second signal conversion module is used to convert the second signal sent by the half-duplex communication interface into a signal adapted to the full-duplex communication interface. Thus, the two signal conversions are performed separately, thereby preventing signal conversion errors.

[0010] In combination with the technical solution provided in the first aspect above, in some possible implementations, the conversion circuit also includes: a baud rate conversion module, a first input end of the baud rate conversion module is used to receive an initial baud rate, a second input end of the baud rate conversion module is used to receive a clock signal, and an output end of the baud rate conversion module is respectively connected to the first buffer module and the second buffer module; the baud rate conversion module is configured to convert the initial baud rate into a target baud rate required for the operation of the conversion circuit according to the received clock signal and the initial baud rate, and transmit the target baud rate and the clock signal to the first buffer module and the second buffer module, so that the first buffer module and the second buffer module perform data transmission according to the target baud rate and the clock signal.

[0011] In the embodiment of the present application, the initial baud rate is converted to the target baud rate by the baud rate conversion module, so that the converted target baud rate meets the requirements of the conversion circuit, thereby eliminating the need for special restrictions on the acquired baud rate, thereby improving the applicability of the present solution.

[0012] In combination with the technical solution provided in the first aspect above, in some possible implementations, the first input end of the baud rate conversion module is used to connect to the full-duplex communication interface and receive the initial baud rate output by the full-duplex communication interface, and the second input end of the baud rate conversion module is used to connect to the full-duplex communication interface and receive the clock signal output by the full-duplex communication interface.

[0013] In the embodiment of the present application, by receiving the initial baud rate from the full-duplex communication interface, there is no need to set up other circuits to obtain the initial baud rate, thereby reducing the complexity of the circuit.

[0014] In combination with the technical solution provided in the first aspect above, in some possible implementations, the conversion circuit also includes: a signal feedback module; a first counter, respectively connected to the designated signal conversion module and the signal feedback module, the first counter being configured to collect the number of bits of the first signal received in the designated signal conversion module to obtain a first quantity; wherein the designated signal conversion module is the first signal conversion module or the second signal conversion module; a second counter, respectively connected to the designated signal conversion module and the signal feedback module, the second counter being configured to collect the number of bits of the second signal received in the designated signal conversion module to obtain a second quantity; the signal feedback module is configured to determine the type of feedback signal based on the first quantity, the second quantity and a preset threshold, wherein the type of feedback signal includes a feedback signal indicating that a signal is being sent and a feedback signal indicating that signal reception is complete.

[0015] In the embodiment of the present application, the first number and the second number are recorded respectively by two counters, so that it is possible to judge whether a signal is being sent and whether the signal sending is completed based on the obtained first number and second number and a preset threshold.

[0016] In combination with the technical solution provided in the first aspect above, in some possible implementations, the preset threshold includes a first threshold and a second threshold, and the signal feedback module is specifically configured to, when the first number is greater than the first threshold, determine that the feedback signal is a feedback signal representing that the signal is being sent, and clear the count value of the first counter; when the second number remains less than the second threshold for a period longer than a preset time threshold, determine that the feedback signal is a feedback signal representing that signal reception is completed.

[0017] In the embodiment of the present application, if the first number is greater than the first threshold, it indicates that the first signal is still being sent, so the count value of the first counter is cleared to continue recording the first number. When the second number remains less than the second threshold for a period longer than a preset time threshold, it indicates that the second signal is not being sent continuously, so the feedback signal is determined to be a feedback signal indicating that signal reception is complete.

[0018] In combination with the technical solution provided in the first aspect above, in some possible implementations, the first signal conversion module is specifically configured to extract the data of the valid data bits in the second signal when it is determined that the received signal is the second signal, and send the extracted valid data bits to the full-duplex communication interface in a signal format adapted to the full-duplex communication interface.

[0019] In the embodiment of the present application, since the formats of the first signal and the second signal are different, the first signal conversion module can convert the second signal sent by the second signal conversion module via the first buffer module into a signal adapted to the full-duplex communication interface by extracting the valid data bits from the second signal and then sending it using a signal format adapted to the full-duplex communication interface.

[0020] In combination with the technical solution provided in the first aspect above, in some possible implementations, the second signal conversion module is specifically configured to extract the data of the valid data bits in the first signal when it is determined that the received signal is the first signal, and send the extracted valid data bits to the half-duplex communication interface in a signal format adapted to the half-duplex communication interface.

[0021] In the embodiment of the present application, since the formats of the first signal and the second signal are different, the second signal conversion module can convert the first signal into a signal adapted to the half-duplex communication interface by extracting the valid data bits in the first signal and then sending it using the signal format adapted to the full-duplex communication interface.

[0022] In a second aspect, the present application provides a conversion system, comprising: a designated chip, a SIM card, and a conversion circuit as described in the first aspect above and / or in combination with any possible implementation of the first aspect above; wherein the designated chip and the SIM card are connected via the conversion circuit.

[0023] In a third aspect, the present application provides an electronic device, comprising the conversion system as described in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 This is a schematic diagram of the structure of a first conversion circuit shown in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the structure of a second conversion circuit shown in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of a format of a second signal shown in an embodiment of the present application;

[0028] Figure 4A schematic diagram of a format of a first signal shown in an embodiment of the present application;

[0029] Figure 5 This is a schematic diagram of the structure of a third conversion circuit shown in an embodiment of the present application;

[0030] Figure 6 This is a schematic diagram of the structure of a fourth conversion circuit shown in an embodiment of the present application;

[0031] Figure 7 A structural block diagram of a conversion system shown in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The terms “first”, “second”, “third”, etc. are only used for distinguishing descriptions and do not indicate the order of arrangement, nor can they be understood as indicating or implying relative importance.

[0033] In the description of this application, unless otherwise clearly specified and limited, the terms "setting" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements.

[0034] The technical solution of the present application will be described clearly and completely below in conjunction with the accompanying drawings.

[0035] In order to solve the problem in the prior art that some chips do not have an interface that can directly support SIM, thereby limiting the application scope of SIM cards, the present application provides a conversion circuit to achieve normal communication between the chip and the SIM card, thereby improving the application scope of the SIM card.

[0036] Since the signal output interface of the chip is usually a full-duplex communication interface, and the communication interface of the SIM card is a half-duplex communication interface, the conversion circuit is used to connect the full-duplex communication interface and the half-duplex communication interface.

[0037] The conversion circuit includes a conversion module, a first buffer module, and a second buffer module. Figure 1 As shown, a conversion module, a first buffer module, and a second buffer module; the conversion module is connected to the half-duplex communication interface through the first buffer module, and is connected to the full-duplex communication interface through the second buffer module.

[0038] The conversion module is configured to convert the first signal sent by the full-duplex communication interface into a signal adapted to the half-duplex communication interface, and send the signal adapted to the half-duplex communication interface to the half-duplex communication interface. The first buffer module is configured to cache the interactive data between the conversion module and the half-duplex communication interface.

[0039] The conversion module is further configured to convert the second signal sent by the half-duplex communication interface into a signal adapted to the full-duplex communication interface, and send the signal adapted to the full-duplex communication interface to the full-duplex communication interface. The second buffer module is configured to cache the interactive data between the conversion module and the full-duplex communication interface.

[0040] See also Figure 2 , Figure 2 This is a schematic diagram of a conversion circuit shown in an embodiment of the present application. Figure 2 Its specific structure is described.

[0041] like Figure 2 As shown, the conversion module includes: a first signal conversion module and a second signal conversion module.

[0042] The first signal conversion module is connected to the first buffer module and the second buffer module respectively, and the second signal conversion module is connected to the first buffer module and the second buffer module respectively.

[0043] The first buffer module and the second buffer module may be electronic components having a storage function and capable of sending stored data to the first signal conversion module or the second signal conversion module.

[0044] Optionally, the first buffer module and the second buffer module may be shift registers of any type.

[0045] The first signal conversion module and the second signal conversion module may be electronic components such as an arithmetic logic unit, a CPLD (Complex Programmable Logic Device), or the like.

[0046] The specific functions of the first signal conversion module and the second signal conversion module can be implemented in the following two ways.

[0047] In the first embodiment, the first signal conversion module is used to connect to the full-duplex communication interface, and the first signal conversion module is configured to send the first signal sent by the full-duplex communication interface to the second signal conversion module via the first buffer module, and convert the second signal sent by the second signal conversion module via the first buffer module into a signal adapted to the full-duplex communication interface, and send it to the full-duplex communication interface.

[0048] The second signal conversion module is used to connect to the half-duplex communication interface. The second signal conversion module is configured to convert the first signal into a signal adapted to the half-duplex communication interface and send it to the half-duplex communication interface, and to send the second signal sent by the half-duplex communication interface to the first signal conversion module via the first buffer module.

[0049] Optionally, the first signal conversion module is specifically configured to extract data of valid data bits in the second signal when determining that the received signal is the second signal, and send the extracted valid data bits to the full-duplex communication interface in a signal format adapted to the full-duplex communication interface.

[0050] For ease of understanding, Figure 3 The signal format shown is the format of the second signal. Figure 4 The signal format shown is a format of the first signal for illustration.

[0051] like Figure 3 As shown, each data frame of the second signal is composed of a start bit, 8 valid data bits, a parity bit, protection data and a stop bit arranged in sequence. Each data frame of the first signal is composed of a start bit, 6 valid data bits, a parity bit and a stop bit arranged in sequence.

[0052] Therefore, when the first signal conversion module needs to convert the second signal into a signal format that is adapted to the full-duplex communication interface (that is, the signal format of the first signal), the 8 valid data bits in the second signal can be extracted first, and then reassembled into a new data frame according to the format of the first signal, and the newly assembled data frame can be sent to the full-duplex communication interface.

[0053] Since there are 8 valid data bits in each data frame of the second signal, and there are only 6 valid data bits in each data frame of the first signal, the 8 valid data bits can be split into two parts, each part forming a new data frame of the first signal format, and the redundant valid data bits (4 valid data bits) can be filled with empty bits.

[0054] For example, 8 valid data bits can be split into the first 4 valid data bits and the last 4 valid data bits, and then the first 4 valid data bits are combined into a data frame of the first signal format, and the remaining 2 valid data bits are filled with empty bits; and the last 4 valid data bits are combined into a data frame of the first signal format, and the remaining 2 valid data bits are filled with empty bits.

[0055] Alternatively, the 8-bit valid data bits may be split into the first 6 valid data bits and the last 2 valid data bits, and then the first 6 valid data bits may be combined into a data frame in the first signal format; and the last 2 valid data bits may be combined into a data frame in the first signal format, and the remaining 4 valid data bits may be filled with empty bits.

[0056] Optionally, the first 6 of the 8 valid data bits may be used as valid data bits to form a new data frame in the first signal format, and the remaining two valid data bits and the first 4 valid data bits of the data frame of the second signal received next may form a data frame, and so on, until all the data frames of the second signal are converted into data frames in the first signal format. If the valid data bits in the data frame of the first signal format obtained by the last conversion are insufficient, they can be filled with empty bits.

[0057] Optionally, the second signal conversion module is specifically configured to extract data of valid data bits in the first signal when determining that the received signal is the first signal, and send the extracted valid data bits to the half-duplex communication interface in a signal format adapted to the half-duplex communication interface.

[0058] For ease of understanding, Figure 3 The signal format shown is the format of the second signal. Figure 4 The signal format shown is the format of the first signal for illustration. Figure 3 As shown, each data frame of the second signal is composed of a start bit, 8 valid data bits, a parity bit, protection data and a stop bit arranged in sequence. Each data frame of the first signal is composed of a start bit, 6 valid data bits, a parity bit and a stop bit arranged in sequence.

[0059] Therefore, when the second signal conversion module needs to convert the first signal into a signal format adapted to the full-duplex communication interface (that is, the signal format of the second signal), it can first extract the 6 valid data bits in the first signal, and then reassemble the new data frame according to the format of the second signal, and send the newly assembled data frame to the half-duplex communication interface.

[0060] Since there are 6 valid data bits in each data frame of the first signal and 8 valid data bits in each data frame of the second signal, the 6 valid data bits can be directly packaged into a data frame of the second signal format, and the insufficient two valid data bits can be filled with empty bits.

[0061] Alternatively, the 6 valid data bits and the first two valid data bits in the next first signal data frame may be encapsulated into a data frame in the second signal format. This process is repeated until all data frames of the first signal are converted into data frames in the second signal format. If the valid data bits in the data frame in the second signal format obtained by the last conversion are insufficient, the bits may be filled with empty spaces.

[0062] In the second implementation, the first signal conversion module is used to connect to the full-duplex communication interface, and the first signal conversion module is configured to convert the first signal sent by the full-duplex communication interface into a signal adapted to the half-duplex communication interface, and send it to the second signal conversion module via the first buffer module, and send the first signal sent by the second signal conversion module via the first buffer module to the full-duplex communication interface.

[0063] The second signal conversion module is used to connect to the half-duplex communication interface. The second signal conversion module is configured to send the first signal to the half-duplex communication interface, and convert the second signal sent by the half-duplex communication interface into a signal adapted to the full-duplex communication interface, and send it to the first signal conversion module via the second buffer module.

[0064] Optionally, the first signal conversion module is specifically configured to extract the valid data bits in the first signal when determining that the received signal is the first signal, and send the extracted valid data bits to the second signal conversion module via the first buffer module in a signal format adapted to the half-duplex communication interface.

[0065] The specific method and principle of extracting the valid data bits in the first signal and converting them into a signal having a signal format adapted to the half-duplex communication interface have been clearly described in the previous text and will not be repeated here for the sake of simplicity.

[0066] Optionally, the second signal conversion module is specifically configured to extract the valid data bits in the second signal when determining that the received signal is the second signal, and send the extracted valid data bits to the first signal conversion module via the second buffer module in a signal format adapted to the full-duplex communication interface.

[0067] The specific method and principle of extracting the valid data bits in the second signal and converting it into a signal format adapted to the full-duplex communication interface have been clearly described in the previous text and will not be repeated here for the sake of brief description.

[0068] In one implementation manner, the conversion circuit may further include a baud rate conversion module.

[0069] like Figure 5 As shown, the first input end of the baud rate conversion module is used to receive the initial baud rate, the second input end of the baud rate conversion module is used to receive the clock signal, and the output end of the baud rate conversion module is connected to the first buffer module and the second buffer module respectively.

[0070] The baud rate conversion module is configured to convert the initial baud rate into the target baud rate required for the conversion circuit to work according to the received clock signal and the initial baud rate, and transmit the target baud rate and the clock signal to the first buffer module and the second buffer module, so that the first buffer module and the second buffer module perform data transmission according to the target baud rate and the clock signal.

[0071] The baud rate refers to the baud rate or modulation rate, which refers to the rate at which the effective data signal modulates the carrier, that is, the number of times the carrier modulation state changes per unit time.

[0072] During data transmission, the baud rate and clock signal are required. Therefore, after the initial baud rate is converted into the target baud rate, the first buffer module and the second buffer module can perform data transmission according to the target baud rate and clock signal.

[0073] The specific principle of baud rate conversion is well known to those skilled in the art and will not be described in detail here for the sake of brevity.

[0074] Optionally, the first input end of the baud rate conversion module is used to connect to the full-duplex communication interface to receive the initial baud rate output by the full-duplex communication interface, and the second input end of the baud rate conversion module is used to connect to the full-duplex communication interface to receive the clock signal output by the full-duplex communication interface.

[0075] By receiving the initial baud rate from the full-duplex communication interface, it is unnecessary to set other circuits to obtain the initial baud rate, thereby reducing the complexity of the circuit.

[0076] In one implementation manner, the conversion circuit further includes a signal feedback module, a first counter and a second counter.

[0077] The first counter is connected to the designated signal conversion module and the signal feedback module respectively, and the second counter is connected to the designated signal conversion module and the signal feedback module respectively.

[0078] The designated signal conversion module is the first signal conversion module or the second signal conversion module.

[0079] The first counter is configured to collect the number of bits of the first signal received in the designated signal conversion module to obtain a first quantity.

[0080] The first counter may be any type of counter, and its specific type is not limited here.

[0081] The second counter is configured to collect the number of bits of the second signal received in the designated signal conversion module to obtain a second number.

[0082] The second counter may be any type of counter, and its specific type is not limited here.

[0083] The signal feedback module is configured to determine the type of the feedback signal according to the first number, the second number and a preset threshold, wherein the type of the feedback signal includes a feedback signal indicating that the signal is being sent and a feedback signal indicating that the signal has been received.

[0084] After determining the type of the feedback signal, the signal feedback module may also send the determined feedback signal to a chip corresponding to the full-duplex communication interface.

[0085] In one implementation, the preset threshold may include a first threshold and a second threshold. The signal feedback module is specifically configured to determine that the feedback signal is a feedback signal representing that the signal is being sent, and clear the count value of the first counter when the first number is greater than the first threshold. When the second number remains less than the second threshold for a period greater than the preset time threshold, the feedback signal is determined to be a feedback signal representing that the signal is received.

[0086] If the first number is greater than the first threshold, it indicates that the first signal is still being sent, so the count value of the first counter is cleared to continue recording the first number. When the second number remains less than the second threshold for a period longer than a preset time threshold, it indicates that the second signal is not being sent continuously, so the feedback signal is determined to be a feedback signal indicating that signal reception is complete.

[0087] The specific values ​​of the first threshold and the second threshold can be set according to actual needs, for example, they can be 1kb, 2kb, 3kb, 4kb, etc. The first threshold and the second threshold can be the same or different, and their specific sizes are not limited here.

[0088] The preset time threshold can be set according to actual needs, for example, it can be 10ms, 20ms, 30ms, etc., and the specific size of the preset time threshold is not limited here.

[0089] The signal feedback module can be any type of circuit function module with signal comparison and selection, as long as it can achieve the above functions.

[0090] To understand the above conversion circuit, please refer to Figure 6 .

[0091] like Figure 6 As shown, the conversion circuit includes a first signal conversion module, a second signal conversion module, a first buffer module, a second buffer module, a baud rate conversion module, a signal feedback module, a first counter, and a second counter.

[0092] The first signal conversion module is connected to the first buffer module and the second buffer module respectively, and the second signal conversion module is connected to the first buffer module and the second buffer module respectively.

[0093] The first signal conversion module is used to connect to the full-duplex communication interface, and the second signal conversion module is used to connect to the half-duplex communication interface.

[0094] The first input end of the baud rate conversion module is used to receive the initial baud rate, the second input end of the baud rate conversion module is used to receive the clock signal, and the output end of the baud rate conversion module is connected to the first buffer module and the second buffer module respectively.

[0095] The first counter is connected to the first signal conversion module and the signal feedback module respectively. The second counter is connected to the first signal conversion module and the signal feedback module respectively. The signal feedback module is configured to be connected to an electronic device corresponding to the full-duplex communication interface.

[0096] Optionally, the first counter may also be connected to the second signal conversion module and the signal feedback module respectively. The second counter may also be connected to the second signal conversion module and the signal feedback module respectively.

[0097] in, Figure 6 The specific functions and implementation principles of each module shown have been clearly described in the previous text. For the sake of brief description, they will not be repeated here.

[0098] Based on the same technical concept, the present application also provides a conversion system. Figure 7 As shown, the conversion system includes a designated chip, a SIM card and a conversion circuit.

[0099] Wherein, the designated chip and the SIM card are connected via the conversion circuit.

[0100] The specific implementation method and working principle of the conversion circuit have been clearly described in the previous article. For the sake of brief description, they will not be repeated here.

[0101] The designated chip may be any type of chip having a full-duplex communication interface, and the specific type of the designated chip is not limited here.

[0102] Based on the same technical concept, the present application also provides an electronic device, which includes the above-mentioned conversion system.

[0103] The specific implementation method and working principle of the conversion system have been clearly described in the previous article. For the sake of brevity, they will not be repeated here.

[0104] The above-mentioned electronic devices include but are not limited to personal computers, servers, etc.

[0105] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A conversion circuit, characterized in that: Used to connect a full-duplex communication interface and a half-duplex communication interface, the conversion circuit includes: A conversion module, a first buffer module, and a second buffer module; the conversion module is connected to the half-duplex communication interface through the first buffer module, and is connected to the full-duplex communication interface through the second buffer module; The conversion module is configured to convert the first signal sent by the full-duplex communication interface into a signal adapted to the half-duplex communication interface, and send the signal adapted to the half-duplex communication interface to the half-duplex communication interface; The first buffer module is configured to cache the interaction data between the conversion module and the half-duplex communication interface; The conversion module is further configured to convert the second signal sent by the half-duplex communication interface into a signal adapted to the full-duplex communication interface, and send the signal adapted to the full-duplex communication interface to the full-duplex communication interface; The second buffer module is configured to cache interactive data between the conversion module and the full-duplex communication interface.

2. The conversion circuit according to claim 1, characterized in that: The conversion module comprises: A first signal conversion module and a second signal conversion module; the first signal conversion module is connected to the first buffer module and the second buffer module respectively, and the second signal conversion module is connected to the first buffer module and the second buffer module respectively; The first signal conversion module is used to connect the full-duplex communication interface, and the first signal conversion module is configured to send a first signal sent by the full-duplex communication interface to the second signal conversion module via the first buffer module, and convert a second signal sent by the second signal conversion module via the first buffer module into a signal adapted to the full-duplex communication interface, and send the signal to the full-duplex communication interface; The second signal conversion module is used to connect the half-duplex communication interface. The second signal conversion module is configured to convert the first signal into a signal adapted to the half-duplex communication interface and send it to the half-duplex communication interface, and to send the second signal sent by the half-duplex communication interface to the first signal conversion module via the first buffer module.

3. The conversion circuit according to claim 1, characterized in that: The conversion module further includes: A first signal conversion module and a second signal conversion module; the first signal conversion module is connected to the first buffer module and the second buffer module respectively, and the second signal conversion module is connected to the first buffer module and the second buffer module respectively; The first signal conversion module is used to connect to the full-duplex communication interface, and the first signal conversion module is configured to convert the first signal sent by the full-duplex communication interface into a signal adapted to the half-duplex communication interface, and send it to the second signal conversion module via the first buffer module, and send the first signal sent by the second signal conversion module via the first buffer module to the full-duplex communication interface; The second signal conversion module is used to connect the half-duplex communication interface. The second signal conversion module is configured to send the first signal to the half-duplex communication interface, and convert the second signal sent by the half-duplex communication interface into a signal adapted to the full-duplex communication interface, and send it to the first signal conversion module via the second buffer module.

4. The conversion circuit according to claim 2, characterized in that: The conversion circuit also includes: A baud rate conversion module, wherein a first input end of the baud rate conversion module is used to receive an initial baud rate, a second input end of the baud rate conversion module is used to receive a clock signal, and an output end of the baud rate conversion module is connected to the first buffer module and the second buffer module respectively; The baud rate conversion module is configured to convert the initial baud rate into a target baud rate required for the operation of the conversion circuit according to the received clock signal and the initial baud rate, and transmit the target baud rate and the clock signal to the first buffer module and the second buffer module, so that the first buffer module and the second buffer module perform data transmission according to the target baud rate and the clock signal.

5. The conversion circuit according to claim 4, characterized in that: The first input end of the baud rate conversion module is used to connect to the full-duplex communication interface to receive the initial baud rate output by the full-duplex communication interface, and the second input end of the baud rate conversion module is used to connect to the full-duplex communication interface to receive the clock signal output by the full-duplex communication interface.

6. The conversion circuit according to claim 2, characterized in that: The conversion circuit also includes: Signal feedback module; A first counter is connected to the designated signal conversion module and the signal feedback module respectively, and the first counter is configured to collect the number of bits of the first signal received in the designated signal conversion module to obtain a first quantity; wherein the designated signal conversion module is the first signal conversion module or the second signal conversion module; A second counter is connected to the designated signal conversion module and the signal feedback module respectively, and the second counter is configured to collect the number of bits of the second signal received in the designated signal conversion module to obtain a second number; The signal feedback module is configured to determine the type of the feedback signal according to the first number, the second number and a preset threshold, wherein the type of the feedback signal includes a feedback signal indicating that the signal is being sent and a feedback signal indicating that the signal has been received.

7. The conversion circuit according to claim 6, characterized in that: The preset threshold includes a first threshold and a second threshold. The signal feedback module is specifically configured to, when the first number is greater than the first threshold, determine that the feedback signal is a feedback signal representing that a signal is being sent, and clear the count value of the first counter; when the second number remains less than the second threshold for a period longer than a preset time threshold, determine that the feedback signal is a feedback signal representing that signal reception is complete.

8. The conversion circuit according to claim 2, characterized in that: The first signal conversion module is specifically configured to extract the valid data bits in the second signal when determining that the received signal is the second signal, and send the extracted valid data bits to the full-duplex communication interface in a signal format adapted to the full-duplex communication interface.

9. The conversion circuit according to claim 2, characterized in that: The second signal conversion module is specifically configured to extract the valid data bits in the first signal when determining that the received signal is the first signal, and send the extracted valid data bits to the half-duplex communication interface in a signal format adapted to the half-duplex communication interface.

10. A conversion system, characterized in that: include: A designated chip, a SIM card and a conversion circuit as claimed in any one of claims 1 to 9; Wherein, the designated chip and the SIM card are connected via the conversion circuit.

11. An electronic device, characterized in that: Comprising the conversion system as claimed in claim 10.

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