Array chip cover plate and packaging structure

Abstract

The utility model relates to the technical field of semiconductors, and discloses an array chip cover plate and a packaging structure. The array chip cover plate comprises a plurality of cover plates, each cover plate is provided with a containing cavity, and the cover plates are of an integrated plane structure arranged in an array mode. The cover plates are connected and fixed through connecting pieces, and the distance between every two cover plates is equal. According to the array chip cover plate, a plurality of chips can be laminated and packaged by an integral large plate, so that the packaging efficiency of the chip cover plate is improved; on the other hand, the utility model further provides an array chip packaging structure, the array chip packaging structure comprises the array chip cover plate and the PCB attached to the lower portion of the array chip cover plate, the multiple chips are arranged on the PCB in an array mode, the multiple chips are packaged at the same time through the array chip cover plate, and the packaging efficiency of the chips is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to an array chip cover plate and a packaging structure. Background Art

[0002] The chip cover is one of the important components of the chip package, usually located on the top of the chip; its main function is to protect the chip from external factors, and it can also enhance the structural strength of the chip package to improve the reliability of the chip. On the other hand, the chip will generate a lot of heat when it is in operation. In order to ensure the normal operation of the chip, a dedicated integrated heat sink is required to dissipate the heat of the chip. However, this integrated heat sink cannot be directly fixed on the PCB circuit board. At this time, a chip cover is needed to support and fix the integrated heat sink; that is to say, the chip cover can not only protect the chip, but also conduct heat.

[0003] In the existing chip cover packaging technology, the chip cover is usually processed into a separate body first, and then the single chip is individually bonded and packaged. The chip cover of this structure has high requirements on the equipment used for packaging the chip during the packaging process, and the packaging efficiency is very low.

[0004] Therefore, there is an urgent need for an array chip cover and a packaging structure to solve the above problems. Utility Model Content

[0005] Based on the above, the purpose of the present invention is to provide an array chip cover and a packaging structure to solve the problem of low chip packaging efficiency.

[0006] In order to solve the above technical problems, the utility model adopts the following technical solutions:

[0007] The utility model provides an array chip cover plate comprising:

[0008] A cover plate, wherein a plurality of the cover plates are provided, each of the plurality of cover plates is provided with a containing cavity, and the plurality of cover plates are arranged in an array to form an integrated planar structure;

[0009] A connecting piece, provided between each of the cover plates, and used for connecting and fixing the multiple cover plates;

[0010] Wherein, the spacing between each of the cover plates is equal.

[0011] As an optional technical solution for an array chip cover plate and a packaging structure, the accommodating cavity is: a void-avoiding cavity opened on the bottom surface of the cover plate.

[0012] As an optional technical solution for an array chip cover plate and a packaging structure, the accommodating cavity is: a hollow space opened in the middle of the cover plate.

[0013] As an optional technical solution for an array chip cover and packaging structure, the accommodating cavity is: a raised portion provided on the top surface of the cover, and an inner cavity of the raised portion is connected to the bottom surface of the cover.

[0014] As an optional technical solution for an array chip cover plate and packaging structure, the corners of the cover plate are provided with chamfers, the connector is a "cross" shaped connector, and the "cross" shaped connector is connected to the chamfers of multiple cover plates.

[0015] As an optional technical solution for an array chip cover and packaging structure, at least one air avoidance portion is provided on the side of the cover, and the connecting piece is an "I"-shaped connecting piece, and the two ends of the "I"-shaped connecting piece are respectively connected to the air avoidance portions on the two sides of the cover.

[0016] On the other hand, the utility model also provides an array chip packaging structure, including the array chip cover plate mentioned above and a PCB board attached to the bottom of the array chip cover plate, wherein a plurality of chips are arranged in an array on the PCB board, wherein when the array chip cover plate is attached to the PCB board, the chip is placed in the accommodating cavity.

[0017] As an optional technical solution for an array chip cover plate and a packaging structure, a glue layer is further provided on the PCB board, and the array chip cover plate is glued and connected to the PCB board through the glue layer.

[0018] As an optional technical solution for an array chip cover and packaging structure, a heat conducting layer is provided on the upper end surface of the chip.

[0019] As an optional technical solution for an array chip cover and packaging structure, the heat-conducting layer is an indium sheet or a heat-conducting silica gel.

[0020] The beneficial effects of the utility model are:

[0021] The utility model provides an array chip cover plate, including: a cover plate, a plurality of cover plates, each of which is provided with a receiving cavity, and the plurality of cover plates are arranged in an array-like integrated planar structure; the plurality of cover plates are connected and fixed by connecting pieces, and the spacing between each cover plate is equal. Under the above structure, the array chip cover plate is a large plate formed by connecting a plurality of single cover plates in an array, which can realize the bonding and packaging of multiple chips on the overall large plate at the same time, thereby improving the packaging efficiency of the chip cover plate; at the same time, the structure in which the individual chip cover plates are connected by connecting pieces only needs to cut the connection points in the subsequent slitting process, thereby simplifying the cutting process after chip packaging, which can protect the chip and support and fix the installation of the heat dissipation component.

[0022] On the other hand, the utility model also provides an array chip packaging structure, including an array chip cover and a PCB board attached to the bottom of the array chip cover, wherein a plurality of chips are arranged in an array on the PCB board, and the plurality of chips are packaged simultaneously through the array chip cover, thereby improving the chip packaging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the overall structure of the array chip cover in the first embodiment of the utility model;

[0024] Figure 2 for Figure 1 The enlarged schematic diagram of point A in the middle;

[0025] Figure 3 This is a schematic diagram of the overall structure of another form of the array chip cover in the first embodiment of the utility model;

[0026] Figure 4 for Figure 3 The enlarged schematic diagram of point B in the middle;

[0027] Figure 5 This is a schematic diagram of the overall structure of the array chip cover plate in the second embodiment of the present utility model;

[0028] Figure 6 for Figure 5 The enlarged schematic diagram of the center C;

[0029] Figure 7 This is a schematic diagram of the overall structure of another form of the array chip cover in the second embodiment of the utility model;

[0030] Figure 8 for Figure 7 The enlarged schematic diagram of point D in the middle;

[0031] Fig. 9 for Figure 7 A cross-sectional view of the middle cover;

[0032] Fig.10 This is a schematic diagram of the overall structure of the array chip cover in the third embodiment of the present utility model;

[0033] Fig.11 for Fig.10 The enlarged schematic diagram of point E in the middle;

[0034] Fig.12 This is a schematic diagram of the overall structure of another form of the array chip cover in the third embodiment of the present utility model;

[0035] Fig.13 for Fig.12 The enlarged schematic diagram of F in the middle;

[0036] Fig.14 for Fig.12 A cross-sectional view of the middle cover;

[0037] Fig.15 It is a schematic diagram of the exploded view of the array chip packaging structure in the fourth embodiment of the present utility model.

[0038] In the figure:

[0039] 1. Cover plate; 2. Avoidance position; 3. Avoidance cavity; 4. Raised part; 5. "X" shaped connector; 6. "I" shaped connector; 7. One array core and one cover plate; 8. PCB board; 9. Chip; 10. Indium sheet. DETAILED DESCRIPTION

[0040] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0041] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0042] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0043] In the description of this embodiment, terms such as "up", "down", "left", and "right" and other orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present utility model.

[0044] In the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more than two. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.

[0045] like Figure 1-15 As shown, the utility model provides an array chip cover plate and packaging structure, the array chip cover plate 7 comprises a cover plate 1, the cover plate 1 is provided with a plurality of, the plurality of cover plates 1 are provided with a receiving cavity, the plurality of cover plates 1 are arranged in an array-like integrated planar structure; a connector is provided between each cover plate 1, the connector is used for connecting and fixing the plurality of cover plates 1; wherein the spacing between each cover plate 1 is equal. The array chip packaging structure comprises an array chip cover plate 7 and a PCB board 8 attached to the bottom of the array chip cover plate 7, the PCB board 8 is provided with a plurality of chips 9 in an array, wherein when the array chip cover plate 7 is attached to the PCB board 8, the chip 9 is placed in the receiving cavity.

[0046] The array chip cover plate 7 provided by the utility model is a large plate formed by connecting a plurality of single cover plates 1 in an array, which can realize the bonding and packaging of a plurality of chips 9 on the overall large plate at the same time, thereby improving the packaging efficiency of the chip cover plate; at the same time, the structure in which the individual cover plates 1 are connected by connecting pieces only needs to cut the connection points in the subsequent slitting process, thereby simplifying the cutting process after the chip 9 is packaged, which can protect the chip 9 and also support and fix the installation of the heat dissipation component. The utility model provides an array chip packaging structure including an array chip cover plate 7 and a PCB board 8 bonded to the bottom of the array chip cover plate 7, wherein a plurality of chips 9 are arranged in an array on the PCB board 8, and the array chip cover plate 7 is used to package a plurality of chips 9 at the same time, thereby improving the packaging efficiency of the chip 9.

[0047] Embodiment 1

[0048] In this embodiment, if Figure 1-4 As shown, the array chip cover plate 7 is composed of a number of single cover plates 1 distributed in an array, and each single cover plate 1 is connected and fixed by a connector. The spacing between each single cover plate 1 is equal, which is beneficial to the accuracy of the array chip cover plate 7 when packaging multiple chips 9 at the same time. The array chip cover plate 7 is an integrally formed planar structure, so that when packaging the chip 9, it is ensured that each individual cover plate 1 can be relatively sealed and fitted with the PCB board 8 for packaging.

[0049] Specifically, Figure 1 and Figure 2As shown, each individual cover plate 1 is provided with a accommodating cavity for accommodating the chip 9, and at least one avoidance portion is opened on the side of each cover plate 1, preferably one avoidance portion, and the avoidance portion is arc-shaped. A connecting piece is provided between the sides of each two individual cover plates 1, and the connecting piece is an "I"-shaped connecting piece 6, and the two ends of the "I"-shaped connecting piece 6 are respectively connected to the avoidance grooves on the sides of the two individual cover plates 1, and the "I"-shaped connecting piece 6 is integrally formed with the cover plate 1.

[0050] In this embodiment, if Figure 3 and Figure 4 As shown, the accommodating cavity is a hollow avoidance position 2 opened in the middle of the cover plate 1, that is to say, in this embodiment, the single cover plate 1 is a hollow dam structure. After the array chip cover plate 7 encapsulates the chip 9, the chip 9 is in the hollow avoidance position 2, and the height of the chip 9 is lower than the height of the cover plate 1, so that the cover plate 1 can protect the chip 9 and provide support for the installation of the heat dissipation component above the chip 9; in addition, the connector can also be set as a "cross"-shaped connector 5, and the corners of each single cover plate 1 are set as chamfers, and the four connection points of the "cross"-shaped connector 5 are respectively connected to the chamfers on different cover plates 1, and the "cross"-shaped connector 5 and The cover plates 1 are formed as an integral structure; of course, the shape and connection method of the connector are not limited to the "cross"-shaped connector 5 or the "I"-shaped connector 6, and a sink groove can be provided between each individual cover plate 1 to realize the connection and fixation of the array arrangement of the cover plates 1. Since the connection points between the connector and the individual cover plates 1 are all point connections, after the array chip cover plate 7 encapsulates multiple chips 9, it is only necessary to divide the connection points between the connector and the individual cover plates 1 to divide the array chip cover plate 7 into multiple independent bodies, and the setting of the air avoidance part and the chamfer is more convenient for the subsequent division of the connection points; this structure simplifies the subsequent division process and improves production efficiency;

[0051] Embodiment 2

[0052] In this embodiment, if Figure 5-9 As shown, the difference from the first embodiment is that the accommodating cavity is a cavity 3 opened upward from the bottom surface of the cover plate 1. After the array chip cover plate 7 encapsulates the chip 9, the chip 9 is in the cavity 3, and the top surface of the cavity 3 and the top surface of the cover plate 1 are an integrated closed structure, so the chip 9 can be heat-conducted through the cover plate 1.

[0053] Embodiment 3

[0054] In this embodiment, if Figure 10-14 As shown, the difference from the first and second embodiments is that the accommodating cavity is: a raised portion 4 arranged on the top surface of the cover plate 1, and the inner cavity of the raised portion 4 is connected to the bottom surface of the cover plate 1. When the array chip cover plate 7 packages the chip 9, the chip 9 is in the raised portion 4.

[0055] Embodiment 4

[0056] like Fig.15 As shown, this embodiment provides an array chip 9 packaging structure, which includes the array chip cover plate 7 described in the above embodiment and a PCB board 8 attached to the bottom of the array chip cover plate 7. A plurality of chips 9 are arranged in an array on the PCB board 8. When the array chip cover plate 7 is attached to the PCB board 8, the chip 9 is placed in the accommodating cavity. A glue layer is also provided on the PCB board 8 surrounding the chip 9. The array chip cover plate 7 is attached to the PCB board 8 through the glue layer, and a heat-conducting layer is provided on the chip 9. The heat-conducting layer can be an indium sheet 10, a heat-conducting silica gel or other materials with good thermal conductivity. At the same time, a gold-plated layer is provided on the top of the avoidance cavity 3 and the top of the inner cavity of the protrusion 4. The arrangement of the gold-plated layer and the heat-conducting layer enables the array chip cover plate 7 to conduct heat well to the chip 9. In addition, the position where the array chip cover plate 7 and the PCB board 8 are attached is roughened to further improve the strength of the attachment of the array chip cover plate 7 and the PCB board 8.

[0057] The above is only a preferred embodiment of the utility model, and does not limit the utility model in any form. Although the utility model is disclosed as a preferred embodiment as above, it is not used to limit the utility model. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes by using the technical content disclosed above without departing from the scope of the technical solution of the utility model. However, any simple modification, equivalent change and modification made to the above embodiments according to the technology of the utility model, which does not depart from the content of the technical solution of the utility model, belongs to the scope of the technical solution of the utility model.

Claims

1. An array chip cover plate, characterized in that: include: A cover plate, wherein a plurality of the cover plates are provided, each of the plurality of cover plates is provided with a containing cavity, and the plurality of cover plates are arranged in an array to form an integrated planar structure; A connecting piece, provided between each of the cover plates, and used for connecting and fixing the multiple cover plates; Wherein, the spacing between each of the cover plates is equal.

2. The array chip cover according to claim 1, characterized in that: The accommodating cavity is: a cavity formed on the bottom surface of the cover plate.

3. The array chip cover according to claim 1, characterized in that: The accommodating cavity is a hollow space opened in the middle of the cover plate.

4. The array chip cover according to claim 1, characterized in that: The accommodating cavity is a raised portion provided on the top surface of the cover plate, and the inner cavity of the raised portion is connected to the bottom surface of the cover plate.

5. An array chip cover according to any one of claims 1 to 4, characterized in that: The corners of the cover plate are all provided with chamfers, and the connecting piece is a "cross"-shaped connecting piece, and the "cross"-shaped connecting piece is connected to the chamfers of multiple cover plates.

6. An array chip cover according to any one of claims 1 to 4, characterized in that: At least one avoidance portion is provided on the side of the cover plate, and the connecting member is an "I"-shaped connecting member, and the two ends of the "I"-shaped connecting member are respectively connected to the avoidance portions on the two sides of the cover plate.

7. An array chip packaging structure, comprising the array chip cover plate according to any one of claims 1 to 6, characterized in that: It also includes a PCB board attached to the bottom of the array chip cover plate, and a plurality of chips are arranged on the PCB board in an array. When the array chip cover plate is attached to the PCB board, the chips are placed in the accommodating cavity.

8. The array chip packaging structure according to claim 7, characterized in that: The PCB board is also provided with a glue coating layer, and the array chip cover plate is bonded and connected to the PCB board through the glue coating layer.

9. The array chip packaging structure according to claim 8, characterized in that: The upper end surface of the chip is provided with a heat conducting layer.

10. The array chip packaging structure according to claim 9, characterized in that: The heat-conducting layer is an indium sheet or a heat-conducting silica gel.

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