Passivation contact battery with selective polycrystalline silicon layer

Abstract

The utility model discloses a passivation contact cell with a selective polycrystalline silicon layer. A selective polycrystalline silicon layer doping technology is adopted in the cell, doped polycrystalline silicon layers are arranged in a local area of a polycrystalline silicon layer at intervals, local grooves are formed in a back passivation antireflection layer at intervals, metal grid lines are in contact with the doped polycrystalline silicon layers only in groove areas and in non-local opening areas, and the metal grid lines are suspended on an antireflection film layer. And no contact with the doped polycrystalline silicon layer is formed. As the intrinsic polycrystalline silicon layer does not have a free carrier absorption phenomenon, parasitic absorption cannot be formed on photons of which the wavelength is greater than 950nm, and optical loss can be remarkably reduced. The arrangement of the local opening grooves can reduce the absorption of the metal grid lines to long-wave photons, the metal grid lines in the non-local opening area and the antireflection film layer can form a back reflector, the long-wave photons can be reflected back to the silicon substrate more effectively to be absorbed and utilized again, and the utilization rate of the long-wave photons is improved.

Description

Technical Field

[0001] The utility model relates to a passivation contact battery with a selective polysilicon layer. Background Art

[0002] According to the difference in the conductivity type of the silicon wafer substrate, crystalline silicon cells are divided into P-type cells and N-type cells. N-type cells have become the trend of market development due to their advantages such as no light-induced degradation, low LeTID degradation, low temperature coefficient and good weak light response. Currently, commercialized N-type crystalline silicon cells are mainly divided into: tunnel oxide passivated contact cells (TOPCon), heterojunction cells (HJT), and all-back contact cells (IBC).

[0003] TOPCon cells are composed of a boron-doped emitter and a tunneling oxide layer / doped polysilicon layer, of which the tunneling oxide layer / doped polysilicon layer belongs to a passivation contact structure, which can significantly reduce the metal composite and contact resistivity of the metal-semiconductor contact area, giving the cell excellent open circuit voltage (Voc) and fill factor (FF) performance; moreover, the preparation process of TOPCon cells is compatible with the preparation process of P-type cells, which can be achieved by transforming the production line of P-type cells. In March 2024, statistics from ITRPV, an international authoritative trend forecasting agency, showed that this year, TOPCon cells will account for 49% of the crystalline silicon cell market share, exceeding the 40% market share of P-type PERC cells to become the mainstream product of crystalline silicon cells, while HJT market share is ~8%, and IBC cells account for ~4%, which is much lower than TOPCon cells.

[0004] The front surface of the commercial TOPCon cell is a boron-doped emitter, and the back side uses a passivation contact structure composed of a tunneling oxide layer / doped polysilicon layer. Considering that the doped polysilicon layer has severe absorption of both short-wave and long-wave light, the passivation contact structure is only used on the back side of the cell, and the front surface is a homojunction structure formed by boron diffusion. The tunneling oxide layer on the back side of the commercial TOPCon cell is an ultra-thin silicon dioxide with a thickness of 1 to 2nm, and the polysilicon layer is a phosphorus-doped polysilicon layer with a thickness of 100 to 150nm. The passivation contact structure composed of the two is evenly distributed on the entire back surface of the silicon wafer. The metal electrodes on the front and back surfaces are formed by screen printing metal paste and sintering. The metal grid lines on the front surface account for about 3%, and the metal grid lines on the back account for 4 to 5%.

[0005] However, this type of commercial TOPCon has the following three disadvantages:

[0006] 1) When sunlight irradiates TOPCon cells, photons with wavelengths greater than 950nm will reach the back of the cell. Since the doped polysilicon layer is evenly distributed on the entire back surface, these photons will be "parasitically absorbed" by the heavily doped polysilicon layer and will not contribute to the photocurrent, resulting in a loss of short-circuit current (Isc).

[0007] 2) The metal grid lines on the back of this type of TOPCon battery account for 4-5%. The metal grid lines are in direct contact with the doped polysilicon layer. Some long-wave photons that pass through the doped polysilicon layer will be absorbed by the metal electrode, which will also lead to the loss of Isc.

[0008] 3) This type of commercial TOPCon cell uses screen-printed metal paste to form metal grid lines on the back surface. During the sintering process, the metal paste will etch away the passivation anti-reflection film and directly form contact with the doped polysilicon layer. Metal "puncture" phenomenon will occur in the local contact area, that is, the metal burns through the polysilicon layer to the silicon wafer substrate, resulting in metal recombination and loss of the open circuit voltage (Voc) of the cell.

[0009] In order to solve the above-mentioned disadvantage 1), in the prior art, differentiated polysilicon layer thickness is usually used on the back of the TOPCon cell, that is, the thickness of the polysilicon layer in the metal gate area is maintained unchanged, and the thickness of the polysilicon layer in the non-metal gate area is thinned to reduce the "parasitic absorption" of the doped polysilicon layer on the back. However, this method can only reduce the optical loss caused by the doped polysilicon layer to a certain extent. The reason is that on the one hand, in order to ensure the passivation effect of the passivation contact structure, the thickness of the polysilicon layer in the non-metal contact area cannot be less than 40nm, and further thinning the thickness will lead to a decrease in passivation performance; on the other hand, the polysilicon layer in the non-metal gate area is heavily doped and still has "parasitic absorption". Summary of the invention

[0010] In view of the shortcomings and deficiencies of the prior art, the utility model provides an improved passivation contact cell with a selective polysilicon layer, which can significantly reduce optical losses, improve the utilization rate of long-wave photons, and improve the Voc value and conversion efficiency of the cell.

[0011] In order to achieve the above purpose, the technical solution adopted by the utility model is as follows:

[0012] A passivation contact cell comprises a silicon wafer body, a front structural layer, a back structural layer, a front metal electrode and a back metal electrode, wherein the back structural layer comprises a tunneling oxide layer, a polysilicon layer and a back passivation anti-reflection layer formed in sequence from the inside to the outside on the back of the silicon wafer body; the polysilicon layer consists of a first region and a second region, the first region is made of intrinsic polysilicon, and the second region is made of doped polysilicon; in the polysilicon layer, a plurality of the second regions are arranged at intervals along the length direction of the back electrode grid line; the back passivation anti-reflection layer has a plurality of grooves arranged at intervals, the grooves are filled with a conductive material, the first opening of the grooves contacts the second region, and the second opening of the grooves contacts the back metal electrode.

[0013] In the utility model, the polysilicon layer is composed of a first region and a second region, and a plurality of the second regions are arranged at intervals along the length direction of the back electrode gate line, that is, two second regions are separated by the first region.

[0014] In the present invention, intrinsic polysilicon refers to undoped polysilicon. Doped polysilicon refers to polysilicon doped with other elements such as phosphorus, boron, etc.

[0015] In some embodiments, the projection of the first opening on the silicon wafer body falls within the projection of the second region on the silicon wafer body, that is, the area of ​​the first opening is smaller than the area of ​​the corresponding contacting second region.

[0016] In some embodiments, a projection of the back metal electrode on the silicon wafer body at least partially overlaps with a projection of the second region on the silicon wafer body.

[0017] Furthermore, the second region and the first opening are both centrally symmetrical, and a projection of the first opening on the silicon wafer body falls within a projection of the back metal electrode on the silicon wafer body.

[0018] Furthermore, the projection of the center position of each first opening on the silicon wafer body overlaps with the projection of the center position of the second area corresponding to the first opening on the silicon wafer body, and the projection of the center position of each second area on the silicon wafer body overlaps with the projection of the center position of the back metal electrode corresponding to the area on the silicon wafer body.

[0019] Furthermore, the projection of the first opening on the silicon wafer body overlaps with the projection of the second opening on the silicon wafer body, that is, the width of the groove is uniform.

[0020] In some embodiments, the conductive material and the back metal electrode are obtained by integral molding. Preferably, both can be integrally molded by sintering a conductive silver paste.

[0021] In some embodiments, the polysilicon layer completely covers the back side of the tunnel oxide layer.

[0022] In some embodiments, the first region and the second region have the same thickness.

[0023] In some embodiments, the thickness of the polysilicon layer is 100-200 nm.

[0024] In some embodiments, in a direction perpendicular to the length of the back electrode grid line, the width of the first opening is less than or equal to the width of the back metal electrode; in the length direction of the back electrode grid line, the length of the first opening is less than or equal to the length of the second region.

[0025] In some embodiments, in a direction perpendicular to the length of the back electrode grid lines, the first openings are evenly spaced in the back passivation anti-reflection layer; in the length direction of the back electrode grid lines, the first openings are evenly spaced in the back passivation anti-reflection layer.

[0026] Furthermore, in the direction perpendicular to the length of the back electrode grid lines, the distance between two adjacent second regions is the same as the distance between two corresponding adjacent back metal grid lines; in the length direction of the back electrode grid lines, the distance between two adjacent second regions is 400-1000 μm.

[0027] Furthermore, in a direction perpendicular to the length of the back electrode grid lines, the width of each second region is 100-200 μm; in a direction of the length of the back electrode grid lines, the length of each second region is 100-200 μm.

[0028] Furthermore, in a direction perpendicular to the length of the back electrode grid lines, the width of each first opening is 10-30 μm; in a direction of the length of the back electrode grid lines, the length of each first opening is 10-100 μm.

[0029] Furthermore, in a direction perpendicular to the length of the back electrode grid lines, the width of the back electrode grid lines is 30-50 μm.

[0030] Furthermore, in a direction perpendicular to the length of the back electrode grid lines, a distance between two adjacent back electrode grid lines is 0.9-1.1 mm.

[0031] In some embodiments, the shape of the second region is selected from a rectangle, a diamond, a circle, and a triangle.

[0032] In the present invention, a rectangle may include a square and a rectangle.

[0033] In some embodiments, the shape of the first opening is selected from a rectangle, a diamond, a circle, and a triangle.

[0034] In some embodiments, the shape of the second region is the same as the shape of the first opening.

[0035] In some embodiments, the doped polysilicon is phosphorus-doped polysilicon; the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon is 3.0×10 20 ~8.0×10 20 / cm 3 , the square resistance is 40~100Ω / sq.

[0036] In some embodiments, the area of ​​the back electrode grid lines accounts for 4% to 5% of the back area of ​​the battery; the area of ​​the first opening accounts for less than or equal to 1% of the back area of ​​the battery.

[0037] In some embodiments, the silicon wafer body is an N-type single crystal silicon substrate.

[0038] In some embodiments, the resistivity of the silicon wafer body is 0.8 to 1.5 Ω·cm, and the thickness is 100 to 180 μm.

[0039] In some embodiments, the tunnel oxide layer is SiO x layer, and the thickness is 0.5 to 2.5 nm, preferably 1.0 to 1.5 nm.

[0040] In some embodiments, the front side of the silicon wafer body is velvet, and the front side structure layer includes a boron-doped emitter, AlO x layer and front passivation layer.

[0041] In some embodiments, the front passivation layer is a combination of two or three of aluminum oxide, silicon nitride, silicon oxynitride, silicon dioxide, and magnesium fluoride. Preferably, the front passivation layer adopts a three-layer film system of aluminum oxide / silicon nitride / silicon oxynitride, wherein the aluminum oxide has a thickness of 2 to 8 nm, the silicon nitride has a refractive index of 2.0 to 2.1 and a thickness of 20 to 40 nm, and the silicon oxynitride has a refractive index of 1.5 to 1.6 and a thickness of 60 to 100 nm.

[0042] In some embodiments, the back side passivation anti-reflection layer is a laminated film consisting of two of aluminum oxide, titanium dioxide, silicon nitride, and silicon oxynitride.

[0043] In some embodiments, the back passivation anti-reflection layer is an aluminum oxide / silicon nitride stacked layer, wherein the aluminum oxide has a thickness of 15 to 30 nm, and the silicon nitride has a refractive index of 2.1 to 2.2 and a thickness of 50 to 65 nm.

[0044] The aforementioned passivated contact cell of the utility model can be used in a photovoltaic module. A photovoltaic module generally includes a front encapsulation layer, a photovoltaic cell and a back encapsulation layer. Among them, the photovoltaic cell includes the aforementioned passivated contact cell.

[0045] Compared with the prior art, the utility model has the following advantages:

[0046] The utility model adopts selective polysilicon layer doping technology on TOPCon cells. Most of the polysilicon layer is an intrinsic polysilicon layer, and a local area is a doped polysilicon layer. The local area is used to contact the metal grid line to form a good "ohmic contact" without affecting the collection and transmission of carriers. Since the intrinsic polysilicon layer does not have the phenomenon of free carrier absorption, it will not form "parasitic" absorption of photons with a wavelength greater than 950nm, which can significantly reduce optical losses.

[0047] The utility model sets local grooves (local openings) on the back passivation anti-reflection layer of the TOPCon cell, and the metal grid lines only form contact with the doped polysilicon layer in the area of ​​the local openings. In the non-local opening area, the metal grid lines "float" on the anti-reflection film layer and do not form contact with the doped polysilicon layer. The setting of the local grooves can not only reduce the absorption of long-wave photons by the metal grid lines, but also the metal grid lines and the anti-reflection film layer in the non-local opening area will form a "back reflector", which can more effectively reflect the long-wave photons back to the silicon substrate, be reabsorbed and utilized, and improve the utilization rate of long-wave photons.

[0048] The back metal grid line of the utility model only contacts the doped polysilicon layer in the area of ​​the local opening. The area of ​​the local opening area accounts for a small proportion, and the contact area between the metal grid line and the doped polysilicon layer is significantly lower than the conventional level. The "puncture" phenomenon of the metal grid line on the doped polysilicon layer can be significantly alleviated, reducing metal recombination, improving passivation performance, and improving the Voc value of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a schematic structural diagram of a passivated contact battery according to Example 1 of the utility model;

[0050] Figure 2 It is a schematic plan view of a passivated contact battery according to Example 1 of the utility model;

[0051] Figure 3 The result diagram of the reflectivity and quantum efficiency of photons in the back metal grid line area of ​​the battery of Example 1 and Comparative Example 1 in the wavelength range of 900 to 1200 nm;

[0052] Among them: 1. silicon wafer body, 2. boron-doped emitter, 3. tunneling oxide layer, 42. first region, 43. second region, 6. front passivation layer, 7. back passivation anti-reflection layer, 8. groove, 81. first opening, 82. second opening, 9. front metal electrode, 10. back metal electrode. DETAILED DESCRIPTION

[0053] The passivation contact structure composed of the tunneling oxide layer and the phosphorus-doped polysilicon layer on the back of the traditional commercial TOPCon cell is evenly distributed on the entire back surface of the silicon wafer. When sunlight irradiates the TOPCon cell, photons with a wavelength greater than 950nm will reach the back of the cell. These photons will be "parasitically absorbed" by the heavily doped polysilicon layer, which will not contribute to the photocurrent and will lead to the loss of short-circuit current (Isc).

[0054] The metal grid lines on the back of traditional commercial TOPCon cells are in direct contact with the doped polysilicon layer. Some long-wave photons that pass through the doped polysilicon layer will be absorbed by the metal electrode, further leading to the loss of Isc.

[0055] During the sintering process of traditional commercial TOPCon cells to form metal grid lines, the metal paste will etch away the passivation anti-reflection film and directly form contact with the doped polysilicon layer. Metal "puncture" phenomenon will occur in the local contact area, that is, the metal burns through the polysilicon layer to the silicon wafer substrate, resulting in metal recombination and loss of the open circuit voltage (Voc) of the cell.

[0056] The main concept of the utility model is: (1) using selective polysilicon layer doping technology, most of the polysilicon layer is an intrinsic polysilicon layer, and the local area is a doped polysilicon layer. The local area is used to contact the metal gate line to form a good "ohmic contact" without affecting the collection and transmission of carriers. Since there is no free carrier absorption phenomenon in the intrinsic polysilicon layer, it will not form "parasitic" absorption for photons with a wavelength greater than 950nm, which can significantly reduce optical losses; compared with the prior art, the thickness of the heavily doped polysilicon layer in the non-metallic gate line area cannot be less than 40nm and there is still some "parasitic absorption", the structure of the utility model is more thorough, and the intrinsic polysilicon layer in the non-metallic gate line area has no "parasitic absorption"; in addition, the structure of the differentiated polysilicon layer thickness requires the heavily doped polysilicon in the non-metallic gate line area to be The silicon layer is thinned, and this thinning process requires precise control at the nanometer level, which has extremely high requirements on the equipment and low production capacity. The thickness of the polysilicon layer on the back of the utility model is the same, and the laser film opening or hole opening process is relatively mature, which is suitable for large-scale mass production; (2) Local grooves (local openings) are set on the passivation anti-reflection film layer on the back of the TOPCon battery, and the metal grid wire only forms contact with the doped polysilicon layer in the area of ​​the local opening. In the non-local opening area, the metal grid wire is "suspended" on the anti-reflection film layer and does not form contact with the doped polysilicon layer. The setting of local openings can not only reduce the absorption of long-wave photons by the metal grid lines, but also the metal grid lines and the anti-reflection film layer in the non-local opening area will form a "back reflector", which can more effectively reflect the long-wave photons back to the silicon substrate, so that they are reabsorbed and utilized, thereby improving the utilization rate of long-wave photons; (3) The metal grid lines on the back side only form contact with the doped polysilicon layer in the area of ​​the local openings. The area of ​​the local openings accounts for a small proportion, and the contact area between the metal grid lines and the doped polysilicon layer is significantly lower than the conventional level, which can significantly alleviate the "puncture" phenomenon of the metal grid lines on the doped polysilicon layer, reduce metal recombination, improve the passivation performance, and improve the Voc value of the battery.

[0057] The conversion efficiency of crystalline silicon cells is jointly determined by the open circuit voltage Voc, the short circuit current density Jsc and the fill factor FF. The back of the TOPCon cell of the utility model adopts selective polysilicon layer doping technology, and most of the back area is an intrinsic polysilicon layer. The intrinsic polysilicon layer will not produce "parasitic absorption" of long-wave photons, which can reduce optical losses and improve Isc. The TOPCon cell of the utility model is provided with local openings on the anti-reflection film layer on the back, and the metal grid lines on the back only form contact with the doped polysilicon layer in the area of ​​the local openings, reducing the metal contact area from the conventional 4-5% to less than 1%, which not only reduces the absorption of long-wave photons by the metal, but also the 3-4% of the metal grid lines that are not in contact form a "back reflector" with the anti-reflection film, which improves the utilization rate of long-wave photons and can further improve Isc. At the same time, the reduction in the proportion of metal contact area can significantly alleviate the "puncture" phenomenon of the metal grid lines on the doped polysilicon layer, reduce metal recombination, improve passivation performance, and improve the Voc value of the cell. Although the change from full-surface doping to local doping in a small area on the back polysilicon layer will affect the lateral transmission of carriers in the polysilicon layer, and the reduction in the contact area of ​​the metal gate line will increase the contact resistance; however, the silicon substrate and the doped polysilicon layer are both phosphorus-doped and have the same conductivity type, so the carriers can complete the lateral transmission in the silicon substrate without over-relying on the doped polysilicon layer; secondly, the heavily doped polysilicon layer is a "degenerate semiconductor", similar to metal, and has an extremely low contact resistivity with the metal gate line (~0.3mΩcm 2 ), the contact area becomes smaller, which has little effect on the overall contact resistance and only leads to a slight decrease in the fill factor (~0.1%). Therefore, considering Voc, Jsc and FF, the battery structure of the utility model has a higher conversion efficiency.

[0058] The present invention is further described below in conjunction with the embodiments. However, the present invention is not limited to the following embodiments. The implementation conditions used in the embodiments can be further adjusted according to the different requirements of specific use, and the implementation conditions not specified are conventional conditions in the industry. The technical features involved in each embodiment of the present invention can be combined with each other as long as they do not conflict with each other.

[0059] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0061] In the present invention, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0062] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0063] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0064] Hereinafter, the x-axis direction refers to the direction perpendicular to the length of the back electrode grid lines, and the y-axis direction refers to the length direction of the back electrode grid lines.

[0065] Example 1

[0066] like Figure 1As shown, the passivation contact cell with a selective polysilicon layer provided in this embodiment includes a silicon wafer body 1, a front structure layer, a back structure layer, a front metal electrode 9 and a back metal electrode 10. The back structure layer includes a tunneling oxide layer 3, a polysilicon layer and a back passivation anti-reflection layer 7 formed on the back of the silicon wafer body 1 from the inside to the outside. The polysilicon layer fully covers the back of the tunneling oxide layer 3.

[0067] Specifically, the polysilicon layer is composed of a first region 42 and a second region 43, the material of the first region 42 is intrinsic polysilicon, and the material of the second region 43 is doped polysilicon; in the polysilicon layer, a plurality of second regions 43 are arranged at intervals along the length direction of the back electrode grid line; the back passivation anti-reflection layer 7 has a plurality of grooves 8 arranged at intervals, the grooves 8 are filled with a conductive material, the first opening 81 of the grooves 8 is in contact with the second region 43, and the second opening 82 of the grooves 8 is in contact with the back metal electrode 10. The material of the second region 43 arranged at intervals is doped polysilicon, and the first opening 81 of the grooves 8 is in contact with the doped polysilicon in the second region 43, which reduces its contact with the intrinsic polysilicon and reduces the "parasitic absorption" of the intrinsic polysilicon.

[0068] Furthermore, the projection of the first opening 81 on the silicon wafer body 1 falls within the projection of the second region 43 on the silicon wafer body 1. That is, the area where the first opening 81 contacts the second region 43 is entirely within the range of the second region 43, and the first opening 81 contacts the doped polysilicon of the second region 43 entirely, but not the intrinsic polysilicon, so that sufficient electrical contact can be ensured.

[0069] The projection of the back metal electrode 10 on the silicon wafer body 1 at least partially overlaps with the projection of the second region 43 on the silicon wafer body 1 .

[0070] The second region 43 and the first opening 81 are both centrally symmetrical, and the projection of the first opening 81 on the silicon wafer body 1 falls within the projection of the back metal electrode 10 on the silicon wafer body 1 .

[0071] The projection of the center position of each first opening 81 on the silicon wafer body 1 overlaps with the projection of the center position of the second region 43 corresponding to the first opening 81 on the silicon wafer body 1, and the projection of the center position of each second region 43 on the silicon wafer body 1 overlaps with the projection of the center position of the back metal electrode 10 corresponding to the region on the silicon wafer body 1. That is, the contact area of ​​the groove 8 with the doped polysilicon, the back metal electrode 10, and the center of each doped polysilicon region in the interval are aligned up and down.

[0072] The projection of the first opening 81 on the silicon wafer body 1 overlaps with the projection of the second opening 82 on the silicon wafer body 1. That is, the width of the groove 8 is consistent from top to bottom.

[0073] The conductive material and the back metal electrode 10 are obtained by integral molding. For example, the conductive paste is injected into the groove 8 and the outside of the back passivation anti-reflection layer 7, and then sintered to obtain the integrally formed conductive material and the back metal electrode 10.

[0074] Furthermore, the first region 42 and the second region 43 have the same thickness, and the thickness of both regions may be, for example, 100-200 nm.

[0075] like Figure 2 As shown, the direction perpendicular to the length of the back electrode grid line is the x-axis direction, and the length direction of the back electrode grid line is the y-axis direction. In the x-axis direction, the width of the first opening 81 is less than or equal to the width of the back metal electrode 10; in the y-axis direction, the length of the first opening 81 is less than or equal to the length of the second region 43. In the x-axis direction, the first openings 81 are evenly spaced in the back passivation anti-reflection layer 7; in the y-axis direction, the first openings 81 are evenly spaced in the back passivation anti-reflection layer 7.

[0076] Preferably, in the x-axis direction, the spacing between two adjacent second regions 43 is the same as the spacing between two corresponding adjacent back metal grid lines; in the y-axis direction, the spacing between two adjacent second regions 43 is 400-1000 μm. In the x-axis direction, the width of each second region 43 is 100-200 μm; in the y-axis direction, the length of each second region 43 is 100-200 μm. In the x-axis direction, the width of each first opening 81 is 10-30 μm; in the y-axis direction, the length of each first opening 81 is 10-100 μm. In the x-axis direction, the width of the back electrode grid lines is 30-50 μm; and / or, in the y-axis direction, the spacing between two adjacent back electrode grid lines is 0.9-1.1 mm.

[0077] Preferably, the area of ​​the back electrode grid lines accounts for 4% to 5% of the back area of ​​the battery; the area of ​​the first opening 81 accounts for less than or equal to 1% of the back area of ​​the battery.

[0078] The shape of the second area 43 is selected from a rectangle, a rhombus, a circle and a triangle; the shape of the first opening 81 is selected from a rectangle, a rhombus, a circle and a triangle. Preferably, the shapes of the two are the same. Figure 2 The display is a rectangle, but the utility model is not subject to Figure 2 restrictions.

[0079] Furthermore, the doped polysilicon is phosphorus-doped polysilicon; the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon is 3.0×10 20 ~8.0×10 20 / cm 3 , the square resistance is 40~100Ω / sq.

[0080] Furthermore, the silicon wafer body 1 is an N-type single crystal silicon substrate, with a resistivity of 0.8-1.5Ω·cm and a thickness of 100-180μm. The tunneling oxide layer 3 is SiO x layer, and the thickness is 0.5 to 2.5 nm, preferably 1.0 to 1.5 nm.

[0081] Furthermore, the front surface of the silicon wafer body 1 is velvet, and the front structural layer includes a boron-doped emitter 2, AlO x Layer and front passivation layer 6. Preferably, the front passivation layer 6 is a combination of two or three of aluminum oxide, silicon nitride, silicon oxynitride, silicon dioxide, and magnesium fluoride. More preferably, the front passivation layer 6 adopts a three-layer film system of aluminum oxide / silicon nitride / silicon oxynitride, wherein the thickness of aluminum oxide is 2 to 8 nm, the refractive index of silicon nitride is 2.0 to 2.1, the thickness is 20 to 40 nm, and the refractive index of silicon oxynitride is 1.5 to 1.6, and the thickness is 60 to 100 nm.

[0082] Further, the back passivation anti-reflection layer 7 is a laminated film composed of two of aluminum oxide, titanium dioxide, silicon nitride, and silicon oxynitride. Preferably, the back passivation anti-reflection layer 7 is an aluminum oxide / silicon nitride laminated film, wherein the aluminum oxide has a thickness of 15 to 30 nm, and the silicon nitride has a refractive index of 2.1 to 2.2 and a thickness of 50 to 65 nm.

[0083] In some specific embodiments, the silicon wafer body 1 is an N-type single crystal silicon substrate, and the N-type single crystal silicon substrate is wet cleaned to remove the damaged layer on the surface of the silicon wafer, clean the surface metal impurities and oil stains and make a velvet surface, and polish and clean the back to form a plane. Then a boron diffusion treatment is performed to form a boron-doped emitter 2 on the front surface and the back surface of the N-type silicon wafer. Then the emitter on the back surface of the N-type silicon wafer is removed, and the back surface is polished. Then a tunneling oxide layer 3 and an intrinsic amorphous silicon layer are grown on the back surface by conventional methods in the art. The intrinsic amorphous silicon layer is a complete layer. In order to form intrinsic polysilicon (i.e., the first region 42) in most of its area and doped polysilicon (i.e., the second region 43) in a small part of the separated area, the above-mentioned back surface can be placed on a graphite carrier with a mask pattern, and the graphite carrier has a hollow area and a mask area. The shape of the hollow area is the same as the shape of the required second area 43, and the mask area is the same as the shape of the required first area 42. The graphite carrier is then transferred into the chamber of the ion implantation equipment, and phosphorus atoms are implanted into the entire surface. The phosphorus atoms injected into the mask area of ​​the graphite carrier are blocked, and the phosphorus atoms injected into the hollow area of ​​the graphite carrier can enter the intrinsic amorphous silicon layer through the hollow area to form phosphorus-doped amorphous silicon. Then a high-temperature annealing treatment is performed. During the annealing process, the intrinsic amorphous silicon and phosphorus-doped amorphous silicon will all be crystallized and transformed into polycrystalline silicon phase. At the same time, the ion-implanted phosphorus atoms can be activated by high temperature to form substitutional doping. After the annealing is completed, the intrinsic amorphous silicon layer is transformed into the first area 42 of the intrinsic polycrystalline silicon layer, and the phosphorus-doped amorphous silicon is transformed into the second area 43 of doped polycrystalline silicon. AlO is then deposited on the positive surface. x The front surface is provided with a passivation layer and a front passivation layer 6, and a back passivation anti-reflection layer 7 is deposited on the back surface. A groove 8 is formed in the back passivation anti-reflection layer 7 by laser opening. A conductive paste is printed on the front surface, the groove 8 and the back surface, and sintered to obtain a front metal electrode 9, a conductive material and a back metal electrode 10 respectively. Finally, the above-mentioned entire passivation battery is obtained.

[0084] Comparative Example 1

[0085] This comparative example provides a comparative passivation contact cell, which is a conventional structure in the prior art. Specifically, it includes a silicon wafer body, a front structural layer, a back structural layer, a front metal electrode and a back metal electrode. The back structural layer includes a tunneling oxide layer, a phosphorus-doped polysilicon layer and a back passivation anti-reflection layer formed on the back of the silicon wafer body from the inside to the outside. The phosphorus-doped polysilicon layer fully covers the back of the tunneling oxide layer, and the thickness of the entire layer is the same. The silicon wafer body is an N-type single crystal silicon substrate with a resistivity of 0.8 to 1.5Ω·cm and a thickness of 100 to 180μm. The tunneling oxide layer is SiO xThe area of ​​the back electrode grid line accounts for 4% to 5% of the back area of ​​the battery. The front side of the silicon wafer body is velvety, and the front structural layer includes a boron-doped emitter, AlO x layer and front passivation layer.

[0086] The reflectivity and quantum efficiency of the photons in the wavelength range of 900 to 1200 nm of the cells of Example 1 and Comparative Example 1 were tested at the metal grid line area on the back side. Figure 3 As shown in the figure, it can be seen that the "back reflector" composed of the "suspended" metal grid line and the anti-reflection film layer in Example 1 can increase the reflectivity of 1200nm wavelength photons from 37% to 79%, and can increase the spectral response value of the 900-1200nm band from 8.3mA / cm 2 Increased to 9.1mA / cm 2 , increased by 0.8mA / cm 2 , the utilization rate of long-wave photons can be significantly improved.

[0087] Performance Test:

[0088] The batteries obtained in the above-mentioned Example 1 and Comparative Example 1 were subjected to the following performance tests, and the testing method was: using an IV tester to test the battery photoelectric conversion efficiency and related electrical performance parameters under standard light power under a simulated solar light source.

[0089] The specific test results are shown in Table 1 (Eta: conversion efficiency, Voc: open circuit voltage, Jsc: short circuit current density, FF: fill factor).

[0090] Table 1 Performance results

[0091] Eta(%) Voc(mV) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) Example 1 25.55 738 41.10 84.25 Comparative Example 1 25.25 735 40.70 84.40

[0092] It can be seen from Table 1 that the conversion efficiency of the battery with a selective polycrystalline silicon layer using the utility model has been significantly improved. Compared with the comparative example 1, the conversion efficiency of Example 1 is improved by 0.3%. For crystalline silicon solar cells, a change of 0.1% is usually a huge improvement. The battery of the utility model can significantly reduce optical losses, improve the utilization rate of long-wave photons, and improve the Voc value and conversion efficiency of the battery.

[0093] The above embodiments are only for illustrating the technical concept and features of the utility model, and their purpose is to enable people familiar with the technology to understand the content of the utility model and implement it accordingly, and they cannot be used to limit the protection scope of the utility model. Any equivalent changes or modifications made according to the spirit of the utility model should be included in the protection scope of the utility model.

[0094] The endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article.

Claims

1. A passivation contact cell, comprising a silicon wafer body, a front structural layer, a back structural layer, a front metal electrode and a back metal electrode, characterized in that: The back structural layer includes a tunneling oxide layer, a polysilicon layer and a back passivation anti-reflection layer which are sequentially formed on the back of the silicon wafer body from the inside to the outside; the polysilicon layer is composed of a first region and a second region, the material of the first region is intrinsic polysilicon, and the material of the second region is doped polysilicon; in the polysilicon layer, a plurality of the second regions are arranged at intervals along the length direction of the back electrode grid line; the back passivation anti-reflection layer has a plurality of grooves arranged at intervals, the grooves are filled with a conductive material, the first opening of the grooves is in contact with the second region, and the second opening of the grooves is in contact with the back metal electrode.

2. The passivated contact cell according to claim 1, characterized in that: The projection of the first opening on the silicon wafer body falls within the projection of the second region on the silicon wafer body; and / or the projection of the back metal electrode on the silicon wafer body at least partially overlaps with the projection of the second region on the silicon wafer body.

3. The passivated contact cell according to claim 2, characterized in that: The second region and the first opening are both centrally symmetrical, and a projection of the first opening on the silicon wafer body falls within a projection of the back metal electrode on the silicon wafer body.

4. The passivated contact cell according to claim 3, characterized in that: The projection of the center position of each first opening on the silicon wafer body overlaps with the projection of the center position of the second area corresponding to the first opening on the silicon wafer body, and the projection of the center position of each second area on the silicon wafer body overlaps with the projection of the center position of the back metal electrode corresponding to the area on the silicon wafer body.

5. The passivated contact cell according to claim 3, characterized in that: The projection of the first opening on the silicon wafer body overlaps with the projection of the second opening on the silicon wafer body.

6. The passivated contact cell according to claim 1, characterized in that: The conductive material and the back metal electrode are obtained by integral molding; and / or the polysilicon layer completely covers the back side of the tunneling oxide layer.

7. The passivated contact cell according to claim 1, characterized in that: The first region and the second region have the same thickness; and / or the polysilicon layer has a thickness of 100-200 nm.

8. The passivated contact cell according to claim 1, characterized in that: In a direction perpendicular to the length of the back electrode grid line, the width of the first opening is less than or equal to the width of the back metal electrode; in the length direction of the back electrode grid line, the length of the first opening is less than or equal to the length of the second region.

9. The passivated contact cell according to claim 1, characterized in that: In a direction perpendicular to the length of the back electrode grid lines, the first openings are evenly spaced in the back passivation anti-reflection layer; in a direction perpendicular to the length of the back electrode grid lines, the first openings are evenly spaced in the back passivation anti-reflection layer.

10. The passivated contact cell according to claim 9, characterized in that: In the direction perpendicular to the length of the back electrode grid lines, the distance between two adjacent second regions is the same as the distance between two corresponding adjacent back metal grid lines; in the length direction of the back electrode grid lines, the distance between two adjacent second regions is 400-1000 μm.

11. The passivated contact cell according to claim 9, characterized in that: In the direction perpendicular to the length of the back electrode grid lines, the width of each second region is 100 to 200 μm; in the length direction of the back electrode grid lines, the length of each second region is 100 to 200 μm; and / or, in the direction perpendicular to the length of the back electrode grid lines, the width of each first opening is 10 to 30 μm; in the length direction of the back electrode grid lines, the length of each first opening is 10 to 100 μm.

12. The passivated contact cell according to claim 9, characterized in that: In a direction perpendicular to the length of the back electrode grid lines, the width of the back electrode grid lines is 30-50 μm; and / or, in a direction perpendicular to the length of the back electrode grid lines, the spacing between two adjacent back electrode grid lines is 0.9-1.1 mm.

13. The passivated contact cell according to claim 1, characterized in that: The shape of the second area is selected from a rectangle, a rhombus, a circle and a triangle; the shape of the first opening is selected from a rectangle, a rhombus, a circle and a triangle.

14. The passivated contact cell according to claim 1, characterized in that: The area of ​​the back electrode grid lines accounts for 4% to 5% of the back area of ​​the battery; the area of ​​the first opening accounts for less than or equal to 1% of the back area of ​​the battery.

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