Mining mechanical state monitoring and fault diagnosis analysis device

Abstract

The utility model relates to the technical field of fault diagnosis equipment, in particular to a mining machinery state monitoring and fault diagnosis analysis device, which comprises a 12V intrinsic safety power supply, an acquisition mainboard, an external 8-path vibration temperature sensor and an external 2-path rotating speed sensor, the acquisition mainboard is composed of a system power supply module, an ARM + FPGA core board, a vibration temperature acquisition module, a rotating speed acquisition module, an Ethernet module and an RS485 module. According to the utility model, the intrinsically safe design is adopted, so that a safety barrier, optical coupler isolation and related fuses are omitted, the volume of the product is reduced, and the cost is saved; the sensor adopts a 12V version, so that the signal anti-interference capability is improved; an ARM and FPGA heterogeneous architecture design is adopted, block collection and algorithm processing of physical quantities are facilitated, edge computing power and system response time are improved, and system iteration upgrading is facilitated; under the working condition of variable rotating speed, hardware is used for sampling at equal angles, and real-time analysis of signals is met.

Description

Technical Field

[0001] The utility model relates to the technical field of diagnostic fault equipment, in particular to a mine mechanical state monitoring and fault diagnosis and analysis device. Background Technique

[0002] The mechanical fault diagnosis and analysis device is used to monitor the running state of the motor of mechanical equipment and analyze faults, including the acquisition and processing of physical quantity signals such as vibration, temperature, and speed. Electrical equipment related to the coal mine industry must meet specific safety specifications, namely the GB 3836.4-2021 and GB3836.14-2021 standards. Most existing mine mechanical fault diagnosis and analysis devices adopt the explosion-proof and intrinsically safe type. Most external sensors of existing mine mechanical fault diagnosis and analysis devices adopt the 5V low-voltage version. For existing explosion-proof and intrinsically safe mechanical fault diagnosis and analysis devices, signals are isolated by optocouplers, and sensors and related interfaces adopt safety isolators. This method has a large volume and high cost. For the mechanical fault diagnosis and analysis device using 5V low-voltage version sensors, the cost and volume are controlled, but the anti-interference ability of the low-voltage version sensors is weakened. Content of the Utility Model

[0003] The purpose of the utility model is to provide a mine mechanical state monitoring and fault diagnosis and analysis device to solve the problems of large volume and high cost in the explosion-proof and intrinsically safe mechanical fault diagnosis and analysis device proposed in the above background technique, where signals are isolated by optocouplers, and sensors and related interfaces adopt safety isolators.

[0004] To achieve the above purpose, the utility model provides the following technical solutions:

[0005] A mine mechanical state monitoring and fault diagnosis and analysis device includes a 12V intrinsically safe power supply, an acquisition main board, an external 8-channel vibration and temperature sensor, and an external 2-channel speed sensor;

[0006] The acquisition main board consists of a system power supply module, an ARM+FPGA core board, a vibration and temperature acquisition module, a speed acquisition module, an Ethernet module, and an RS485 module;

[0007] The system power supply module is divided into 4 power supplies in total, including: 12V power supply for vibration and temperature sensors, 12V power supply for speed sensors, power supply for the gain amplifier, and power supply for the core board and 24-bit ADC;

[0008] The vibration and temperature acquisition module includes a temperature signal acquisition circuit and a vibration signal acquisition circuit.

[0009] Preferably, the 12V intrinsically safe power supply uses the Coal Science KDW220 / 12D, which has several groups of voltage limiting circuits built in. The parameters of the intrinsically safe power supply are Uo = 12.5V, Io = 1.5A, Co = 25uF, and Lo = 0.1mH.

[0010] Preferably, the voltages Ui of each path in the first stage of the system power supply module are as follows: the voltage Ui of the vibration temperature sensor is 13V, the voltage Ui of the rotational speed sensor is 13V, the voltage Ui of the DC / DC LT8471 is 50V, and the voltage Ui of the DC / DC LT8650 is 42V. The voltages Ui of each path satisfy the specification of Uo ≤ Ui. The currents Ii of each path in the first stage of the system power supply module are as follows: the current Ii of the vibration temperature sensor is 1.66A, the current Ii of the rotational speed sensor is 1.66A, the current Ii of the DC / DC LT8471 is 2A, and the current Ii of the DC / DC LT8650 is 4A. The currents Ii of each path satisfy the specification of Io ≤ Ii.

[0011] Preferably, the total capacitance value of the first stage of the system power supply module plus the total capacitance value of the sensors C is 21.34uF, and the capacitance accuracy is 10%. Therefore, Ci = 21.34uF * 1.1 = 23.474uF, which satisfies the specification of Co ≥ Ci. The total inductance value of the maximum loop of the system power supply module Li is 15.22uH, which satisfies the specification of Lo ≥ Li.

[0012] Preferably, the voltage limiting circuit uses a two-stage voltage limiting circuit composed of a voltage stabilizing diode and a thyristor MCR106-6. When the output voltage of the DC / DC exceeds the voltage of the voltage stabilizing diode, the voltage stabilizing diode works. The voltage obtained by the working current of the voltage stabilizing diode and the resistor R113 controls the thyristor to start working, thereby protecting the subsequent circuit.

[0013] Preferably, the ARM+FPGA core board adopts the heterogeneous system design architecture of NXP quad-core ARM Cortex-A53 and Xilinx FPGA. The ARM+FPGA core board is used for collecting physical quantity signals such as vibration, temperature, and rotational speed and algorithm processing, and transmitting relevant index data and waveform data to the background for diagnostic analysis.

[0014] Preferably, in the temperature signal acquisition circuit, the temperature signal passes through a conditioning circuit composed of voltage division by R100 and R101 and the LMV321 operational amplifier to increase the signal input impedance; then it is sent to an 8-to-1 multiplexer RS2251, which is connected to 8-channel temperature signals and performs switching; the switched signal is sent to a dual-channel 16-bit ADC MCP3427, and the signal is finally sent to the ARM for linear conversion of voltage and temperature; the vibration and temperature acquisition module uses the high-precision 24-bit Σ-Δ type AD7768 from ADI. This ADC has 8-channel synchronous sampling, a maximum output rate of 256 kSPS, and a bandwidth of 110.8 kHz. The Xilinx FPGA is used to perform logic control and data reading on the AD7768.

[0015] Preferably, the vibration signal acquisition circuit includes a vibration and temperature sensor, a filter circuit, a gain amplifier, and a third-order low-pass filter.

[0016] Preferably, the rotation speed acquisition module is used for data acquisition of the rotation speed sensor and outputting a fixed-angle sampling synchronization signal to the vibration and temperature acquisition module to achieve equal-angle sampling. The rotation speed sensor signal converts the 12V rotation speed pulse signal into a 3.3V pulse signal through a high-speed optocoupler, and after waveform shaping and conditioning through a Schmitt trigger, it is transmitted to the FPGA for waveform counting.

[0017] Preferably, the equal-angle data acquisition module uses hardware to achieve equal-angle sampling. The hardware equal-angle sampling is realized by a hardware circuit composed of a phase-locked loop, a frequency divider, a multiplexer, an AD7768, and an FPGA. The voltage-controlled oscillation output of the phase-locked loop CD4046 is sent to the clock input terminal of the frequency divider CD4040. After frequency division, it enters the multiplexer. After the FPGA sets the frequency division coefficient, the frequency-divided signal f1 returns to the phase comparison input terminal of the CD4046 to compare the phase with the rotation speed signal f0 to be frequency-doubled. When the frequencies and phases of f0 and f1 input to the CD4046 are the same, the frequency output by the phase-locked loop CD4046 is the equal-angle synchronous sampling signal f2. f2 is input to the synchronous sampling pin of the AD7768. Under the action of the synchronous signal, the AD7768 starts synchronous sampling, acquires the vibration signal of the vibration sensor at this time, and transmits the converted digital signal to the FPGA, where f2 = f0 * f1, F2 is the AD7768 synchronous sampling signal, f2 = M * RPM / 60 = M * rotation frequency, and M is the rotation speed sampling point.

[0018] Compared with the prior art, the beneficial effects of the present utility model are:

[0019] This mine mechanical state monitoring and fault diagnosis analysis device adopts intrinsically safe design, eliminating the safety barrier, optocoupler isolation and related fuses, reducing the product volume and saving costs. The sensor uses a 12V version, improving the signal anti-interference ability. It adopts a heterogeneous architecture design of ARM and FPGA, which is conducive to the block acquisition of various physical quantities and algorithm processing, improving the edge computing ability and system response time, and facilitating system iteration and upgrade. Under variable speed conditions, hardware equal-angle sampling is used to meet the real-time analysis of signals.

[0020] This mine mechanical state monitoring and fault diagnosis analysis device designs a set of 12V intrinsically safe mechanical fault diagnosis analysis device based on the relevant safety specifications of mining equipment and from a practical perspective. The device designs the circuit according to intrinsically safe design, strictly controls voltage and current, and the loop capacitance and inductance values meet the specification requirements, and corresponding overvoltage protection measures are taken for the voltage. This solution eliminates the safety barrier, optocoupler isolation and related fuses, reduces the product volume and saves costs. The external sensor of this solution uses a 12V version, improving the signal anti-interference ability.

[0021] This mine mechanical state monitoring and fault diagnosis analysis device adopts a heterogeneous system design architecture of NXP quad-core ARM Cortex-A53 and Xilinx FPGA. Through this design, the system edge computing ability is improved, the index data refresh time is shortened, sufficient computing power is reserved for later complex working conditions and complex algorithms, and flexibility is provided for the domestic substitution of each module in the later stage. Description of the Drawings

[0022] The drawings are used to provide a further understanding of the present utility model, and constitute a part of the specification, and are further explained in detail together with the embodiments of the present utility model, but do not constitute a limitation to the present utility model.

[0023] Figure 1 It is the system composition block diagram of the mine mechanical state monitoring and fault diagnosis analysis device of the present utility model;

[0024] Figure 2 It is the system composition block diagram of the system power supply module in the present utility model;

[0025] Figure 3 It is the circuit schematic diagram of the overvoltage limiting circuit in the present utility model;

[0026] Figure 4 It is the signal link diagram of the vibration temperature acquisition module and speed acquisition in the present utility model;

[0027] Figure 5 It is the vibration signal acquisition circuit diagram in the present utility model;

[0028] Figure 6 This is the temperature signal acquisition circuit diagram in the present utility model;

[0029] Figure 7 This is the equal-angle sampling circuit diagram in the present utility model. Specific embodiments

[0030] Next, in combination with the embodiments of the present utility model and the accompanying drawings of the specification, the technical solutions in the embodiments of the present utility model will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0031] A mine mechanical state monitoring and fault diagnosis and analysis device, as Figures 1-7 shown, includes a 12V intrinsically safe power supply, an acquisition main board, an external 8-channel vibration and temperature sensor, and an external 2-channel rotational speed sensor; the acquisition main board is composed of a system power supply module, an ARM+FPGA core board, a vibration and temperature acquisition module, a rotational speed acquisition module, an Ethernet module, and an RS485 module; the system power supply module is divided into a total of 4 power supplies, including: 12V vibration and temperature sensor power supply, 12V rotational speed sensor power supply, gain amplifier power supply, and core board and 24-bit ADC power supply; the vibration and temperature acquisition module includes a temperature signal acquisition circuit and a vibration signal acquisition circuit.

[0032] Further, the 12V intrinsically safe power supply uses the coal science KDW220 / 12D, with several groups of voltage limiting circuits built in. The parameters of the intrinsically safe power supply are Uo = 12.5V, Io = 1.5A, Co = 25uF, and Lo = 0.1mH.

[0033] Among them, the voltages Ui of each stage of the system power supply module are: the Ui voltage of the vibration and temperature sensor is 13V, the Ui voltage of the rotational speed sensor is 13V, the Ui voltage of the DC / DC LT8471 is 50V, and the Ui voltage of the DC / DC LT8650 is 42V. The voltages Ui of each stage satisfy the specification of Uo ≤ Ui; the currents Ii of each stage of the system power supply module are: the Ii current of the vibration and temperature sensor is 1.66A, the Ii current of the rotational speed sensor is 1.66A, the Ii current of the DC / DC LT8471 is 2A, and the Ii current of the DC / DC LT8650 is 4A. The currents Ii of each stage satisfy the specification of Io ≤ Ii; the total capacitance value of the first stage of the system power supply module plus the total capacitance value of the sensor C is 21.34uF, and the capacitance accuracy is 10%. Therefore, Ci = 21.34uF * 1.1 = 23.474uF, which satisfies the specification of Co ≥ Ci; the total maximum loop inductance value Li of the system power supply module is 15.22uH, which satisfies the specification of Lo ≥ Li.

[0034] It should be noted that the voltage-limiting circuit adopts a two-stage voltage-limiting circuit composed of a voltage-regulator diode and a thyristor MCR106-6. When the output voltage of the DC / DC exceeds the voltage of the voltage-regulator diode, the voltage-regulator diode works. The voltage obtained from the working current of the voltage-regulator diode and the resistor R113 controls the thyristor to start working, thereby protecting the subsequent circuit.

[0035] Specifically, the ARM+FPGA core board adopts the heterogeneous system design architecture of NXP's quad-core ARM Cortex-A53 and Xilinx FPGA. The ARM+FPGA core board is used for collecting physical quantity signals such as vibration, temperature, and rotation speed and algorithm processing, and transmitting relevant index data and waveform data to the background for diagnostic analysis.

[0036] Among them, the vibration and temperature acquisition module adopts the ADI high-precision 24-bit Σ-Δ type AD7768. This ADC has 8-channel synchronous sampling, the highest output rate of 256 kSPS, a bandwidth of 110.8 kHz, and Xilinx FPGA is used for logical control and data reading of AD7768.

[0037] It should be noted that the vibration signal acquisition circuit includes a vibration and temperature sensor, a filter circuit, a gain amplifier, and a third-order low-pass filter. The vibration signal of the vibration and temperature sensor first passes through a DC-blocking capacitor to filter out the DC component; then it passes through a low-pass filter composed of RC to suppress signal aliasing; this signal is sent to the programmable gain amplifier LTC6373 for amplification or reduction, and the single-ended signal is converted into a differential signal. This amplifier has a high-impedance input, low noise, and low distortion; after being attenuated by 0.5 times by the gain amplifier, signals of 2mV - 17V can be measured, and the maximum acceleration signal that can be measured is 80g. The signal attenuated by LTC6373 passes through a third-order low-pass filter composed of a second-order RC and the feedback network of the differential driver ADA4945 for anti-aliasing filtering to achieve out-of-band suppression of the signal; the differential driver ADA4945 improves the signal dynamic range, reduces second harmonic distortion, and at the same time provides a stable signal input for the subsequent AD7768.

[0038] Among them, in the temperature signal acquisition circuit, the temperature signal passes through a conditioning circuit composed of voltage division by R100 and R101 and the LMV321 operational amplifier to increase the signal input impedance; then it is sent to an 8-to-1 multiplexer RS2251. This switch connects 8-channel temperature signals and performs switching; the switched signal is sent to the dual-channel 16-bit ADC MCP3427, and the signal is finally sent to the ARM for linear conversion of voltage and temperature; the rotation speed acquisition module is used for collecting rotation speed sensor data and outputting a fixed-angle sampling synchronization signal to the vibration and temperature acquisition module to achieve equal-angle sampling. The rotation speed sensor signal converts the 12V rotation speed pulse signal into a 3.3V pulse signal through a high-speed optocoupler, and after waveform shaping and conditioning through a Schmitt trigger, it is transmitted to the FPGA for waveform counting.

[0039] In addition, to meet the application requirements under variable speed conditions, the system uses hardware to achieve equal-angle sampling instead of software interpolation resampling for equal-angle sampling.

[0040] In the interpolation resampling process, the rotational speed is estimated based on the rotational speed pulse sequence, and then the time sequence of the occurrence moments of equal-angle sampling is calculated using this estimated rotational speed. The original noise signal sampled synchronously is interpolated and resampled within the time interval near the equal-angle sampling moment to obtain the steady-state signal in the angular domain required for order analysis. This method has a prediction deviation.

[0041] Hardware equal-angle sampling is implemented using a hardware circuit composed of a phase-locked loop, a frequency divider, a multiplexer switch, an AD7768, and an FPGA. The voltage-controlled oscillator output of the phase-locked loop CD4046 is sent to the clock input of the frequency divider CD4040. After frequency division, it enters the multiplexer switch. After the frequency division coefficient (number of sampling points) is set by the FPGA, the divided signal f1 returns to the phase comparison input of the CD4046 and is phase-compared with the rotational speed signal f0 to be frequency-doubled. When the frequencies and phases of f0 and f1 input to the CD4046 are the same, the frequency output by the phase-locked loop CD4046 is the equal-angle synchronous sampling signal f2. The f2 is input to the synchronous sampling pin of the AD7768. Under the action of the synchronous signal, the AD7768 starts synchronous sampling, collects the vibration signal of the vibration sensor at this time, and transmits the converted digital signal to the FPGA.

[0042] f2 = f0 * f1, where F2 is the synchronous sampling signal of the AD7768.

[0043] f2 = M * RPM / 60 = M * rotational frequency, where M is the rotational speed sampling point.

[0044] It can be seen from the above formula that the sampling frequency F2 is proportional to the rotational frequency. That is to say, at low rotational speeds, the sampling frequency is low, and at high rotational speeds, the sampling rate is high, so as to meet the requirement of equal sampling points per revolution and thus achieve equal-angle sampling.

[0045] This hardware method does not require predicting the rotational speed like software interpolation resampling and can meet the application requirements under variable speed conditions.

[0046] This mine machinery condition monitoring and fault diagnosis analysis device adopts intrinsically safe design, eliminating the safety barrier, optocoupler isolation and related fuses, reducing the volume of the product and saving costs; including using a 12V version for the sensor, improving the signal anti-interference ability; adopting a heterogeneous architecture design of ARM and FPGA, which is conducive to block-by-block acquisition of various physical quantities and algorithm processing, improving the edge computing ability and system response time, and facilitating system iteration and upgrade; under variable speed conditions, using hardware equal-angle sampling to meet the real-time analysis of signals.

[0047] Based on the relevant safety specifications of mining equipment and starting from practicality, this mine mechanical status monitoring and fault diagnosis analysis device has designed a set of intrinsically safe mechanical fault diagnosis analysis devices with a voltage of 12V. The device designs the circuit according to intrinsic safety, strictly controls the voltage and current, and the values of loop capacitance and inductance meet the specification requirements, and corresponding overvoltage protection measures are taken for the voltage. This solution eliminates the safety barrier, optocoupler isolation and related fuses, reduces the volume of the product, and saves costs. The external sensors of this solution adopt the 12V version, which improves the signal anti-interference ability.

[0048] This mine mechanical status monitoring and fault diagnosis analysis device adopts the heterogeneous system design architecture of NXP quad-core ARM Cortex-A53 and Xilinx FPGA. Through this design, the edge computing ability of the system is improved, the refresh time of index data is shortened, sufficient computing power is reserved for later complex working conditions and complex algorithms, and flexibility is provided for the domestic substitution of each module in the later stage.

[0049] The above has shown and described the basic principles, main features and advantages of the present utility model. Those skilled in the art should understand that the present utility model is not limited by the above embodiments. The above embodiments and the descriptions in the specification are only preferred examples of the present utility model and are not used to limit the present utility model. Without departing from the spirit and scope of the present utility model, the present utility model will have various changes and improvements, and these changes and improvements all fall within the scope of the present utility model claimed. The scope of protection claimed by the present utility model is defined by the appended claims and their equivalents.

Claims

1. A mining machinery status monitoring and fault diagnosis and analysis device, characterized in that: Includes 12V intrinsically safe power supply, acquisition mainboard, external 8-channel vibration and temperature sensor, external 2-channel speed sensor; The acquisition mainboard consists of system power module, ARM+FPGA core board, vibration temperature acquisition module, speed acquisition module, Ethernet module, and RS485 module; The system power supply module is divided into 4 power supplies, including: 12V vibration temperature sensor power supply, 12V speed sensor power supply, gain amplifier power supply, core board and 24-bit ADC power supply; The vibration and temperature acquisition module includes a temperature signal acquisition circuit and a vibration signal acquisition circuit.

2. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 1 is characterized in that: The 12V intrinsically safe power supply adopts Meike KDW220 / 12D, which has several sets of built-in voltage limiting circuits. The parameters of the intrinsically safe power supply are Uo is 12.5V, Io is 1.5A, Co is 25uF, and Lo is 0.1mH. The first-level Ui of the system power module is: the vibration temperature sensor Ui voltage is 13V, the speed sensor Ui voltage is 13V, the DC / DC LT8471 Ui voltage is 50V, and the DC / DC LT8650 Ui voltage is 42V. The Ui voltage of each channel meets the Uo≤Ui specification.

3. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 2 is characterized in that: The first-level Ii of the system power module is: the vibration temperature sensor Ii current is 1.66A, the speed sensor Ii current is 1.66A, the DC / DC LT8471 Ii current is 2A, and the DC / DC LT8650 Ii current is 4A. The Ii current of each channel meets the Io≤Ii specification.

4. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 2 is characterized in that: The total value of the first-level capacitance of the system power module plus the total value of the sensor capacitance C is 21.34uF, and the capacitance accuracy is 10%. Therefore, Ci=21.34uF*1.1=23.474uF, which meets the Co≥Ci specification; the maximum total loop inductance Li of the system power module is 15.22uH, which meets the Lo≥Li specification.

5. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 2 is characterized in that: The voltage limiting circuit adopts a two-stage voltage limiting circuit composed of a voltage regulator tube and a thyristor MCR106-6. When the DC / DC output voltage exceeds the voltage regulator tube voltage, the voltage regulator tube works, and the voltage obtained by the voltage regulator tube working current and the resistor R113 controls the thyristor to start working, thereby protecting the subsequent circuit.

6. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 1 is characterized in that: The ARM+FPGA core board adopts the NXP quad-core ARM Cortex-A53 and Xilinx FPGA heterogeneous system design architecture. The ARM+FPGA core board is used for vibration, temperature, and speed physical quantity signal acquisition and algorithm processing, and transmits relevant indicator data and waveform data to the background for diagnosis and analysis.

7. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 1 is characterized in that: In the temperature signal acquisition circuit, the temperature signal is sent to the conditioning circuit composed of R100 and R101 voltage divider and LMV321 operational amplifier to improve the signal input impedance; then sent to the 8-to-1 multiplexer RS2251, which connects the 8-channel temperature signals and switches them; the switched signal is sent to the dual-channel 16-bit ADC MCP3427, and the signal is finally sent to the ARM, and the linear conversion between voltage and temperature is performed; The vibration temperature acquisition module adopts ADI's high-precision 24-bit Σ-Δ type AD7768. The ADC has 8-channel synchronous sampling, a maximum output rate of 256 kSPS, and a bandwidth of 110.8 kHz. Xilinx FPGA is used to perform logic control and data reading on AD7768.

8. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 1 is characterized in that: The vibration signal acquisition circuit includes a vibration temperature sensor, a filter circuit, a gain amplifier and a third-order low-pass filter.

9. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 1, characterized in that: The speed acquisition module is used for speed sensor data acquisition and outputting fixed-angle sampling synchronization signals to the vibration and temperature acquisition module to realize equal-angle sampling. The speed sensor signal converts the 12V speed pulse signal into a 3.3V pulse signal through a high-speed optocoupler, and after waveform shaping and conditioning through a Schmitt trigger, it is transmitted to the FPGA for waveform counting.

10. The mining machinery status monitoring and fault diagnosis and analysis device according to claim 9, characterized in that: The equal-angle sampling adopts hardware equal-angle sampling, and the hardware equal-angle sampling is realized by a hardware circuit composed of a phase-locked loop, a frequency divider, a multiple-choice switch, AD7768, and an FPGA. The voltage-controlled oscillation output of the phase-locked loop CD4046 is output to the clock input end of the frequency divider CD4040, and after frequency division, it enters the multiple-choice switch. After the frequency division coefficient is set by the FPGA, the frequency division signal f1 returns to the phase-discrimination input end of the CD4046 and is compared with the speed signal f0 to be multiplied. When the frequency and phase of f0 and f1 input by the CD4046 are the same, the frequency output by the phase-locked loop CD4046 is the equal-angle synchronous sampling signal f2, and f2 is input to the AD7768 synchronous sampling pin. Under the action of the synchronous signal, the AD7768 starts synchronous sampling, collects the vibration signal of the vibration sensor at this time, and transmits the converted digital signal to the FPGA, wherein f2=f0*f1, F2 is the AD7768 synchronous sampling signal, f2=M*RPM / 60=M*rotation frequency, and M is the speed sampling point.

Images