Semiconductor element

Abstract

A semiconductor device includes a gate electrode, a gate dielectric layer in contact with the gate electrode. A first 2-D material buffer layer is over the gate dielectric layer. A 2-D material channel layer is over the first 2-D material buffer layer. A plurality of source / drain electrodes are over the 2-D material channel layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Advancements in integrated circuit materials and design have produced many generations of integrated circuits. Each generation has smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of integrated circuit manufacturing and fabrication. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected components per unit wafer area) generally increases while the geometric dimensions decrease (i.e., the smallest component (or line) that can be produced using the manufacturing process). This scaling process generally provides several benefits such as increased production efficiency and reduced associated costs. However, as the feature size continues to decrease, the manufacturing process also becomes more difficult to implement. Therefore, it is a challenge to fabricate reliable semiconductor devices at increasingly smaller sizes. Summary of the Utility Model

[0003] According to at least one embodiment of the present disclosure, a semiconductor device includes: a gate electrode; a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; and a plurality of source / drain electrodes on the 2-D material channel layer.

[0004] According to at least one embodiment of the present disclosure, a semiconductor device includes: a gate electrode;

[0005] a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; a second 2-D material buffer layer on the 2-D material channel layer; and a plurality of source / drain electrodes on the 2-D material channel layer.

[0006] According to at least one embodiment of the present disclosure, a semiconductor device includes: a gate electrode; a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; a second 2-D material buffer layer on the 2-D material channel layer; a plurality of source / drain electrodes on the 2-D material channel layer; and a passivation layer on the second 2-D material buffer layer. Description of the Drawings

[0007] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it is noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1A to 1D FIG. is a diagram of a semiconductor device at various manufacturing stages in accordance with some embodiments of the present disclosure;

[0009] Figure 2 FIG. is a schematic diagram of a monolayer of transition metal dichalcogenides (TMDs) in accordance with some embodiments of the present disclosure;

[0010] Figure 3 FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0011] Figures 4A to 4D FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0012] Figures 5A to 5B FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0013] Figure 6 FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0014] Figure 7 FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0015] Figure 8 FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0016] Figure 9 FIG. is a diagram of a semiconductor device in accordance with some embodiments of the present disclosure;

[0017] Figure 10 FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0018] Figure 11 FIG. is a diagram of a semiconductor device in accordance with some embodiments of the present disclosure;

[0019] Figure 12 FIG. is experimental results of a semiconductor device in accordance with some embodiments of the present disclosure;

[0020] Figures 13A to 13F FIG. is a diagram of a semiconductor device at various manufacturing stages in accordance with some embodiments of the present disclosure;

[0021] Figure 14A andFigure 14B According to some embodiments of the present disclosure, a diagram of a semiconductor device;

[0022] Figure 15 According to some embodiments of the present disclosure, experimental results of a semiconductor device.

[0023]

Symbol Description

[0024] 100: Substrate

[0025] 110: Channel layer

[0026] 110CH: Channel region

[0027] 110SD: Source / drain region

[0028] 110SD_1: Portion

[0029] 110SD_2: Portion

[0030] 111: Buffer layer

[0031] 112: Buffer layer

[0032] 120: Dielectric layer

[0033] 130: Metal layer

[0034] 140: Metal layer

[0035] 150: Source / drain electrode

[0036] 150M: Portion

[0037] 150P: Portion

[0038] 160: Passivation layer

[0039] 400: Monolayer of transition metal dichalcogenide

[0040] 402: Transition metal atom

[0041] 404: Chalcogen atom

[0042] A 1g : Signal

[0043] E 1 2g : Signal

[0044] W1: Width

[0045] W2: Width

[0046] W3: Width

[0047] W4: Width

[0048] Δk: Difference Detailed Implementation Manner

[0049] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and configurations to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, in various examples, the present disclosure may repeat reference numerals and / or letters. This repetition is for simplicity and clarity purposes and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0050] In addition, for ease of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, these spatial relative terms are intended to also cover different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and likewise, the spatial relative descriptors used herein may be interpreted accordingly. Terms such as "substantially", "approximately", "about", "nearly", or similar items used herein may represent a range of 20%, 10%, or 5% of the numerical values or ranges provided herein. The numerical magnitudes provided herein are approximate values, and unless otherwise specified, it is inferred that terms such as "substantially", "approximately", "about", "nearly", or similar items used herein are applicable. However, those of ordinary skill in the art will understand that the numerical magnitudes or ranges recited herein are only examples, and these values may vary or decrease as the integrated circuit size is scaled down.

[0051] Figures 1A to 1D are diagrams of semiconductor components at various manufacturing stages according to some embodiments of the present disclosure.

[0052] Reference Figure 1A . Shown herein is a substrate 100. In some embodiments, the substrate 100 may be a conductive substrate, such as polysilicon. For example, the substrate 100 may be made of p-doped polysilicon. A dielectric layer 120 is formed on the substrate 100. In some embodiments, the dielectric layer 120 is silicon dioxide (e.g., SiO 2 ) or aluminum oxide (e.g., Al 2 O 3)。In some other embodiments, the dielectric layer 120 can be a high-k dielectric. In some embodiments, the substrate 100 can serve as the gate electrode of a transistor, and the dielectric layer 120 can serve as the gate dielectric layer of the transistor. Therefore, the substrate 100 can also be regarded as the gate electrode, and the dielectric layer 120 can also be regarded as the gate dielectric layer. In some embodiments, the dielectric layer 120 and the substrate 100 can be jointly regarded as a gate structure.

[0053] Reference Figure 1B 。The 2-D material channel layer 110 is formed on the dielectric layer 120. As used herein, and in accordance with the definitions accepted in the field of solid-state materials, a "2-D material" can be a crystalline material comprising a single layer of atoms. As is more widely accepted in the art, "2-D" can also be a "single-layer" material. In this document, "2-D" materials and "single-layer" materials can be used interchangeably, and there is no difference in meaning between the two unless otherwise specified. The 2-D material layer can be a 2-D material with a suitable thickness. In some embodiments, the 2-D material comprises a single layer of atoms in each of its single-layer structures, so the thickness of the 2-D material is the number of single layers of the 2-D material, which can be one single layer or more than one single layer. The coupling between two adjacent single layers of the 2-D material, including van der Waals forces, is weaker than the chemical bonds between / within single-layer atoms. In some embodiments, the 2-D material layer can be a single single-layer structure or can also be a multi-layer structure.

[0054] In some embodiments, the 2-D material channel layer 110 can be made of transition metal dichalcogenides. That is to say, the 2-D material channel layer 110 can be a metal-containing 2-D material layer. In some embodiments where the 2-D material channel layer 110 comprises a single layer of transition metal dichalcogenides, the single layer of transition metal dichalcogenides comprises molybdenum disulfide (MoS 2 ), molybdenum diselenide (MoSe 2 ), molybdenum ditelluride (MoTe 2 ), tungsten disulfide (WS 2 ), tungsten diselenide (WSe 2 ), tungsten ditelluride (WTe 2 ) or the like.

[0055] Reference Figure 2 。 Figure 2 is a schematic diagram of a single layer 400 of exemplary transition metal dichalcogenides according to some exemplary embodiments. In Figure 2In it, a monolayer-thick transition metal dichalcogenide material layer includes transition metal atoms 402 and chalcogen atoms 404. The transition metal atoms 402 can form a layer in the middle region of the monolayer-thick transition metal dichalcogenide material. The chalcogen atoms 404 can form a first layer on the layer of transition metal atoms 402 and a second layer below the layer of transition metal atoms 402. The transition metal atoms 402 can be tungsten atoms or molybdenum atoms, and the chalcogen atoms 404 can be sulfur atoms, selenium atoms or tellurium atoms. Throughout the discussion, the shown staggered bonding layer includes a layer of transition metal atoms 402 and two layers of chalcogen atoms 404 as a combination, and is regarded as a monolayer 400 of transition metal dichalcogenide.

[0056] Refer back to Figure 1B , the 2-D material channel layer 110 can be made of molybdenum disulfide, and molybdenum disulfide can be formed by the method described below. Although molybdenum disulfide has application potential in optical or electronic components, most components are made of micrometer-sized small molybdenum disulfide flakes, and the size is prepared by mechanical exfoliation or chemical vapor deposition (CVD). These methods cannot be mass-produced and will hinder the practical application of molybdenum disulfide-based components. To solve this problem, obtaining a wafer-level molybdenum disulfide film by sulfidation of a pre-deposited molybdenum or molybdenum trioxide film has been proposed. The number of layers can be well controlled by this method. One possible consideration in the two-step growth process of molybdenum disulfide is that the molybdenum / molybdenum trioxide film usually needs to grow through a monolayer of molybdenum disulfide when it is 1.0 nm. In this case, the coverage of the molybdenum / molybdenum trioxide film on the substrate will be uneven, which will result in an uneven or cracked molybdenum disulfide film after the sulfidation process.

[0057] To achieve uniform molybdenum trioxide growth for subsequent sulfidation, atomic layer deposition technology (ALD) can be adopted to form the 2-D material channel layer 110 of molybdenum disulfide. Two precursors, molybdenum hexacarbonyl (Mo(Co) 6 ) and ozone (O 3 ) are used for the growth of molybdenum trioxide. The carrier gas for the atomic layer deposition system is nitrogen, and the growth temperature is about 180 °C. The deposition cycle for the atomic layer deposition process includes the following steps: (a) a 9-second pulse of molybdenum hexacarbonyl, (b) a 3-second nitrogen purge, (c) a 9-second ozone pulse, (d) a 6-second nitrogen purge. In some embodiments, to form a monolayer of molybdenum disulfide, 6 atomic layer deposition growth cycles are used for the growth of molybdenum trioxide. After the molybdenum trioxide film is formed, the molybdenum trioxide film is sulfided to form a molybdenum disulfide film. As shown in Figure 3 , a smooth surface of the atoms of the sample is observed and has a surface roughness of about 0.23 nm. This result shows that a uniform molybdenum disulfide film can be grown on the substrate by sulfiding the molybdenum trioxide film obtained by atomic layer deposition.

[0058] On the other hand, one of the main advantages of 2-D materials is that the thin film can be transferred onto different substrates and still maintain its unique electrical and optical characteristics after the film transfer process. Compared with the traditional poly(methyl methacrylate) (PMMA)-assisted film transfer process, the film transfer process using polydimethylsiloxane (PDMS) printing can significantly reduce the contamination of methyl methacrylate on the surface of 2-D materials.

[0059] In typical PDMS printing, the PDMS elastomer stamp is used as the carrier substrate for the material to be deposited (e.g., the 2-D material channel layer 110 in this example). In some embodiments, the 2-D material channel layer 110 (e.g., molybdenum disulfide) is coated on the protruding surface of the PDMS stamp. The 2-D material channel layer 110 is transferred to the substrate (e.g., the dielectric layer 120 in this example), and then the PDMS stamp is peeled off from the 2-D material channel layer 110.

[0060] Reference Figure 4A , the atomic force microscopy (AFM) image of the molybdenum disulfide film generated by PDMS printing is shown. Compared with the smoothly grown molybdenum disulfide sample (e.g., Figure 3 shown), wrinkles can be found on the surface of molybdenum disulfide. The surface roughness of the sample is also increased to 0.55 nm. Since the molybdenum disulfide film is only about a few nanometers thick, the surface tension of the transferred molybdenum disulfide film on the substrate may be the main mechanism for this phenomenon.

[0061] To release the surface tension of the molybdenum disulfide film, an annealing process is performed on the sample in an argon (Ar) environment at about 100 °C to about 200 °C (e.g., 150 °C) for about 0.5 hours to 2 hours (e.g., 1.5 hours). After the annealing process, the AFM image of the sample is as shown in Figure 4B shown. Compared with Figure 4A , after the annealing process, the wrinkles are smoothed out, and the surface roughness is reduced to about 0.3 nm. This result indicates that the annealing process can effectively release the surface tension of the molybdenum disulfide thin film and smooth its surface.

[0062] After the film is transferred to the substrate and the annealing process, the Raman spectrum and photoluminescence spectrum of the sample are as shown in Figure 4C and Figure 4D shown, respectively. As shown in the Raman spectrum in Figure 4C , the Raman characteristic signal E 1 2g and the Raman characteristic signal A 1g of the sample after the film transfer process and the additional annealing process are observed. The difference Δk of the similar Raman signals of the sample after the film transfer process and the additional annealing process is 19.4 cm-1 and 19.3 cm -1 , indicating that monolayer molybdenum disulfide is obtained after the growth process. As Figure 4D shown in the photoluminescence spectrum, a stronger photoluminescence signal is observed after the sample undergoes the annealing process. A possible mechanism for this phenomenon is that after the annealing process, water and oxygen molecules attached to the surface of molybdenum disulfide are removed. Since the wrinkles observed in the sample after the transfer process are actually bilayer molybdenum disulfide (see Figure 4A ), a more intense photoluminescence signal is also observed in the annealed monolayer molybdenum disulfide film that has been smoothed. The smoothed molybdenum disulfide film has the potential to reduce carrier scattering and enhance the performance of its transistor applications.

[0063] Figure 5A and Figure 5B are the experimental results of semiconductor devices according to some embodiments of the present disclosure.

[0064] To further explore the smooth molybdenum disulfide surface generated by the polydimethylsiloxane transfer and annealing processes, it is possible to use the strong adhesion force between molybdenum disulfide layers and the advantages of molybdenum disulfide and multi-layer molybdenum disulfide with layer number control established through ordered film adhesion for component applications. By utilizing the same polydimethylsiloxane transfer, one, two, and three molybdenum disulfide films can be transferred onto the substrate one by one. After the transfer of each film, the same annealing process is performed in an argon (Ar) environment at approximately 100 °C to approximately 200 °C (e.g., 150 °C) for approximately 0.5 hours to 2 hours (e.g., 1.5 hours). The Raman spectra of the samples are as Figure 5A shown, where the Raman characteristic signals E 1 2g and Raman characteristic signal A 1g are presented. After the first, second, and third transfers of molybdenum disulfide, the difference Δk between the two signals increases from 19.3 cm -1 to 21.0 cm -1 and 22.7 cm -1 , indicating that three molybdenum disulfide films of monolayer, bilayer, and trilayer are obtained. This result also indicates that the adhesion force between molybdenum disulfide and molybdenum disulfide and the adhesion force between molybdenum disulfide and silicon dioxide are stronger than the adhesion force at the interface between polydimethylsiloxane and molybdenum disulfide. Therefore, after the transfer process, the molybdenum disulfide film tends to adhere to the substrate rather than the polydimethylsiloxane surface. In this case, multi-layer molybdenum disulfide films with good uniformity can be obtained after ordered film adhesion. The photoluminescence spectra of the three samples are as Figure 5BAs shown. The strong photoluminescence signal of a single MoS₂ transfer sample, as well as the redshift of the signal value with the increase in the number of MoS₂ layers, can be observed in the figure. In addition, it is consistent with the results observed from the Raman spectra of monolayer, bilayer, and trilayer obtained after the first to third MoS₂ transfer processes.

[0065] Reference Figure 1C . Source / drain electrodes 150 are formed on the 2-D material channel layer 110. In some embodiments, each source / drain electrode 150 includes a first metal layer 130 and a second metal layer 140 on the first metal layer 130. The source / drain electrodes 150 can be formed as follows. A photoresist layer with openings is formed on the 2-D material channel layer 110, then the first metal layer 130 and the second metal layer 140 are deposited in the openings of the photoresist layer, and then a lift-off process is performed to remove the photoresist layer and the upper part of the first metal layer 130 on the photoresist layer and the upper part of the second metal layer 140 on the photoresist layer. Thus, a part of the first metal layer 130 and a part of the second metal layer 140 in the openings of the photoresist layer remain above the 2-D material channel layer 110 to become the source / drain electrodes 150.

[0066] The first metal layer 130 and the second metal layer 140 can be made of different materials. In some embodiments, the first metal layer 130 is made of a 2-D material of a single element. For example, the first metal layer 130 can be made of antimonene. Specifically, antimonene is a 2-D allotrope of antimony. In other embodiments, the first metal layer 130 can include bismuth, tin, or germanium. In some embodiments, the deposition temperature of the first metal layer 130 can range between 65 °C and about 75 °C, such as 70 °C. If the temperature is too low (e.g., far below 65 °C), the device performance will not be as expected. If the temperature is too high (e.g., far greater than 75 °C), the high temperature will deteriorate the quality of the photoresist layer and have an adverse effect on the formation of the source / drain electrodes 150. By using antimonene as the contact electrode, the observed contact resistance at the interface between antimonene and the 2-D material channel layer 110 (e.g., molybdenum disulfide) will be significantly reduced. On the other hand, if standard lithography and lift-off processes are employed for the deposition of the contact metal of antimony, a relatively low growth temperature (e.g., 70 °C) can be used to form an antimony deposition of about 50 nm on the surface of the 2-D material channel, without the 200 °C required for the formation of single-crystalline antimonene, thereby avoiding the deterioration of the photoresist material. In some embodiments where the first metal layer 130 made of antimonene has a deposition temperature in the range between 70 °C and about 80 °C, the first metal layer 130 includes a polycrystalline structure instead of a single-crystalline structure. Since the first metal layer 130 (e.g., antimony film) can be etched with an alkaline or acidic solution, the second metal layer 140 (such as a 100-nm gold (Au) film) can be deposited at room temperature (RT) after the first metal layer 130 is deposited and serves as a protective layer. In other embodiments, the second metal layer 140 can also include copper or palladium.

[0067] Reference Figure 1D . The partially exposed 2-D material channel layer 110 is patterned by the source / drain electrodes 150 to define the channel region of the transistor. For example, the partially exposed 2-D material channel layer 110 is narrowed by the source / drain electrodes 150 in a direction substantially perpendicular to the current flow direction. Here, the direction of current flow can be the direction from one source / drain electrode 150 to the other source / drain electrode 150. Thus, the channel region 110CH is formed in the 2-D material channel layer 110. On the other hand, a portion of the 2-D material channel layer 110 is longitudinally positioned under the source / drain electrodes 150 and is regarded as the source / drain region 110SD.

[0068] In some embodiments, after the source / drain electrodes 150 are formed, reactive ion etching (RIE) can be employed to define the channel of the transistor. The channel width and channel length of the channel region are about 25 μm and 5 μm, respectively.

[0069] After the channel is defined, the bottom gate transistor is generated. Here, the transistor can be a monolayer molybdenum disulfide transistor. Figure 6 is the transfer curve graph of the device at V DS = 1.0 V. The field effect mobility value calculated from the transfer curve of the device is about 1.0 cm 2 V -1 s -1 . This value is much larger than the field effect mobility (10 -2 cm 2 V -1 s -1 ) of the transistor fabricated using a radio frequency sputtering system. This result shows that the deposition of a uniform molybdenum trioxide film using atomic layer deposition is crucial for the growth of a uniform 2-D material film (such as molybdenum disulfide) through high-temperature sulfidation. A low contact resistance can also be achieved at the antimonene / molybdenum disulfide interface, and thus improved device performance can be observed for the transistor. However, as Figure 6 shows, the device has a large hysteresis under forward and reverse gate biases.

[0070] Figure 7 is a diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 8 is the experimental result of a semiconductor device according to some embodiments of the present disclosure. It is worth noting that Figure 7 some elements of Figures 1A to 1D are similar to those described with respect to

[0071] As described above with respect to Figure 1D and Figure 6 , for a possible mechanism of the large hysteresis loop observed in the monolayer molybdenum disulfide surface crystal, it may be the trapped charges / dangling bonds on the dielectric surface at the interface between the 2-D material channel layer 110 (such as molybdenum disulfide) and the dielectric layer 120 (such as silicon dioxide). Therefore, in order to avoid the influence of the molybdenum disulfide / silicon dioxide interface on the molybdenum disulfide channel, a 2-D material buffer layer can be inserted between the 2-D material channel layer 110 and the dielectric layer 120.

[0072] In Figure 7 , before the generation of the 2-D material channel layer 110 (as described in Figure 1B ), the 2-D material buffer layer 111 is generated on the dielectric layer 120. In some embodiments, in the channel definition process (as described in Figure 1D ), the 2-D material buffer layer 111 and the 2-D material channel layer 110 are patterned together, so that the 2-D material buffer layer 111 can substantially have the same profile as the 2-D material channel layer 110.

[0073] In some embodiments, the 2-D material buffer layer 111 may comprise the same material as the 2-D material channel layer 110, such as molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, tungsten ditelluride, or the like. In other embodiments, the 2-D material buffer layer 111 may comprise a material different from the 2-D material channel layer 110. For example, the 2-D material buffer layer 111 may comprise a transition metal dichalcogenide different from the 2-D material channel layer 110. In some embodiments, the 2-D material channel layer 110 is made of molybdenum disulfide, while the 2-D material buffer layer 111 is made of tungsten disulfide. In other embodiments, the 2-D material buffer layer 111 may comprise hexagonal boron nitride (hBN). In some embodiments, the 2-D material buffer layer 111 may comprise 1 to 10 monolayers.

[0074] In some embodiments, the 2-D material buffer layer 111 may be formed by atomic layer deposition (ALD). In other embodiments, the formation of the 2-D material buffer layer 111 may utilize polydimethylsiloxane transfer followed by an annealing process to reduce the surface roughness of the 2-D material buffer layer 111. That is, when both the 2-D material channel layer 110 and the 2-D material buffer layer 111 are formed by polydimethylsiloxane transfer, a first polydimethylsiloxane transfer is performed to form the 2-D material buffer layer 111 on the dielectric layer 120, and then a first annealing process is performed to smooth the 2-D material buffer layer 111. Then, a second polydimethylsiloxane transfer is performed to form the 2-D material channel layer 110 on the 2-D material buffer layer 111, and then a second annealing process is performed to smooth the 2-D material channel layer 110. This method can ensure better film quality for both the 2-D material channel layer 110 and the 2-D material buffer layer 111.

[0075] In Figure 7 the example of, a molybdenum disulfide buffer layer (such as the 2-D material buffer layer 111) is added between a molybdenum disulfide channel (such as the 2-D material channel layer 110) and a silicon dioxide dielectric layer (such as the dielectric layer 120). That is, a bilayer molybdenum disulfide film can be established on the surface of silicon dioxide by transferring two monolayers of molybdenum disulfide. After the film transfer, the same electrodes (such as the source / drain electrodes 150) are fabricated on the bilayer molybdenum disulfide film. Figure 8 is the transfer curve graph of the device at V DS = 1.0V. Compared with the monolayer molybdenum disulfide transistor as described in Figure 1D the bilayer molybdenum disulfide transistor has a drain current 3 to 4 times larger under the same operating conditions. The field-effect mobility of the device is also increased to 3.41 cm 2 V -1s -1 This result shows that in the case of a 2-D material buffer layer under the 2-D material channel layer, the influence of dangling bonds / defects on the dielectric surface can be suppressed. Lower carrier scattering and thus higher field-effect mobility are observed in the transistor. However, as Figure 8 shown, an obvious hysteresis loop can still be observed in the device.

[0076] Figure 9 is a diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 10 is the experimental result of a semiconductor device according to some embodiments of the present disclosure. It is worth noting that Figure 9 some of the devices and Figures 1A to 1D described are similar. These devices have the same markings, and their related details are not repeated here for the sake of brevity.

[0077] As described above regarding Figure 7 and Figure 8 , although inserting a 2-D material buffer layer 111 between the dielectric layer 120 and the 2-D material channel layer 110 can improve the device performance, an obvious hysteresis loop can still be observed in the device (see Figure 8 ). For the hysteresis of the device under forward and reverse biases, a possible mechanism may be the interface between air and the 2-D material channel. To solve this problem, a passivation layer covering the 2-D material channel layer 110 is formed to isolate the 2-D material channel layer 110 from the ambient atmosphere.

[0078] In Figure 9 , after the source / drain electrodes 150 are formed, a passivation layer 160 is formed on the 2-D material channel layer 110. Thus, the passivation layer 160 can cover and contact the channel region 110CH of the 2-D material channel layer 110. It is worth noting that although the passivation layer 160 shown here only covers the upper surface of the 2-D material channel layer 110, the passivation layer 160 can also extend to the sidewalls of the 2-D material channel layer 110 and the sidewalls of the 2-D material buffer layer 111.

[0079] The passivation layer 160 may comprise a dielectric material such as aluminum oxide (Al 2 O 3 ), silicon dioxide (e.g., SiO 2 ) or other suitable dielectric materials. In other embodiments, the passivation layer 160 may comprise a high-k dielectric material such as hafnium dioxide. In some embodiments, where the passivation layer 160 is aluminum oxide (Al 2 O 3) fabricated, the thickness of the aluminum oxide passivation layer 160 is about 30 nm. In some embodiments, the formation of the 30-nm aluminum oxide passivation layer 160 can be achieved by depositing a 5-nm aluminum oxide layer using a physical deposition process (such as electron beam evaporation), and then depositing 25 nm of aluminum oxide using a chemical deposition process (such as atomic layer deposition). Because the surface of the 2-D material channel layer 110 lacks dangling bonds that provide nucleation points for the dielectric material of the passivation layer 160. If the dielectric material (such as Al 2 O 3 ) is formed by chemical deposition (such as the atomic layer deposition process), the precursors will not be easily and uniformly distributed on the surface of the 2-D material channel layer 110. However, due to the inherent characteristics of physical deposition, the vaporized material or ionized material can be "dropped" onto the surface of the 2-D material channel layer 110, and there can be better coverage on the 2-D material channel layer 110 compared to using chemical deposition. Therefore, the thin layer of the passivation layer 160 formed by physical deposition can serve as a seed layer for the subsequent deposition of the thick layer of the passivation layer 160, so that the entire passivation layer 160 can have better coverage and uniformity on the 2-D material channel layer 110.

[0080] with a passivation layer 160 (such as 30-nm aluminum oxide) Figure 9 of the transistor is shown as Figure 10 . When there is a passivation layer 160, the hysteresis loop of the device under forward and reverse biases is significantly reduced. Higher leakage current and higher field-effect mobility of 7.22 cm 2 V -1 s -1 are also observed. This result shows that water or oxygen molecules adhering to the surface of the 2-D material channel may cause electron scattering and trapped charges on the surface of the 2-D material channel.

[0081] Figure 11 is a diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 12 is the experimental result of a semiconductor device according to an embodiment of the present disclosure. It should be noted that Figure 11 some of the devices are the same as those described in Figures 1A to 1D , Figure 7 and Figure 9 , these devices have the same markings, and the relevant details are not repeated here for the sake of simplicity.

[0082] As described above regarding Figure 9 and Figure 10, the passivation layer 160 covering the 2-D material channel layer 110 can significantly improve the device performance, indicating that the water or oxygen molecules adhering to the 2-D material channel are the main mechanism causing the observed hysteresis in the transistor. However, the increased field-effect mobility value of the transistor also indicates that there will be electron scattering at the interface between the 2-D material channel layer 110 (such as molybdenum disulfide) and the passivation layer 160 (such as a dielectric material). To solve this problem, devices with an additional 2-D material buffer layer above the 2-D material channel are fabricated.

[0083] In Figure 11 , after the source / drain electrodes 150 are formed and before the passivation layer 160 is formed (as Figure 9 described), the 2-D material buffer layer 112 is formed on the 2-D material channel layer 110. More specifically, the 2-D material buffer layer 112 covers the channel region 110CH of the 2-D material channel layer 110. On the other hand, the source / drain regions 110SD of the 2-D material channel layer 110 are covered by the source / drain electrodes 150 and are not completely covered by the 2-D material buffer layer 112. In some embodiments, the 2-D material buffer layer 112 and the 2-D material channel layer 110 can be patterned together in a channel definition process (such as as described in Figure 1D ), and thus the 2-D material buffer layer 112 can substantially have the same profile as the channel region 110CH of the 2-D material channel layer 110.

[0084] In some embodiments, the 2-D material buffer layer 112 can include the same material as the 2-D material channel layer 110, such as molybdenum disulfide (MoS 2 ), molybdenum diselenide (MoSe 2 ), molybdenum ditelluride (MoTe 2 ), tungsten disulfide (WS 2 ), tungsten diselenide (WSe 2 ), tungsten ditelluride (WTe 2 ) or the like. In other embodiments, the 2-D material buffer layer 112 can include a material different from the 2-D material channel layer 110. For example, the 2-D material buffer layer 112 can include a different transition metal dichalcogenide from the 2-D material channel layer 110. In some embodiments, the 2-D material channel layer 110 is made of molybdenum disulfide and the 2-D material buffer layer 112 is made of molybdenum disulfide. In other embodiments, the 2-D material buffer layer 112 can include hexagonal boron nitride. In some embodiments, the 2-D material buffer layer 112 can include 1 to 10 monolayers.

[0085] In some embodiments, the 2-D material buffer layer 112 can be formed by atomic layer deposition (ALD). In other embodiments, the 2-D material buffer layer 112 can be formed by polydimethylsiloxane transfer printing and then annealed to reduce the surface roughness of the 2-D material buffer layer 112. That is, when the 2-D material channel layer 110, the 2-D material buffer layer 111, and the 2-D material buffer layer 112 are all formed by polydimethylsiloxane transfer printing, the first polydimethylsiloxane transfer printing is performed to form the 2-D material buffer layer 111 on top of the dielectric layer 120, and then the first annealing process is performed to smooth the 2-D material buffer layer 111. Next, the second polydimethylsiloxane transfer printing is performed to form the 2-D material channel layer 110 on top of the 2-D material buffer layer 111, and then the second annealing process is performed to smooth the 2-D material channel layer 110. Then, the third polydimethylsiloxane transfer printing is performed to form the 2-D material buffer layer 112 on top of the 2-D material channel layer 110, and then the third annealing process is performed to smooth the 2-D material buffer layer 112. This method can ensure better film quality for the 2-D material channel layer 110, the 2-D material buffer layer 111, and the 2-D material buffer layer 112.

[0086] In Figure 11 embodiments, since the 2-D material buffer layer 112 covers the 2-D material channel layer 110, the passivation layer 160 can cover and be in contact with the upper surface of the 2-D material buffer layer 112. It is worth noting that although the passivation layer 160 shown here only covers the upper surface of the 2-D material buffer layer 112, the passivation layer 160 can also extend to the sidewalls of the 2-D material buffer layer 112, the sidewalls of the 2-D material channel layer 110, and the sidewalls of the 2-D material buffer layer 111.

[0087] Figure 12 is the transfer curve of the device at V DS = 1.0 V. Compared with the devices discussed in Figure 9 and Figure 10 , for the device with a 2-D material buffer layer on the 2-D material channel, even higher leakage current and a transfer curve without hysteresis can be observed. Good device performance with a high field-effect mobility value (22.7 cm 2 V -1 s -1 ) and a high ON / OFF ratio (> 10 5 ) can also be observed.

[0088] Figures 13A to 13F is a diagram of a semiconductor device at various manufacturing stages according to some embodiments of the present disclosure. It is worth noting that Figures 13A to 13FSome of the components are similar to those described above, and these components have the same markings. The relevant details are not repeated here for the sake of brevity.

[0089] Reference Figure 13A , shown here is substrate 100. Dielectric layer 120 is formed on substrate 100. In some embodiments, substrate 100 can serve as the gate electrode of a transistor, and dielectric layer 120 can serve as the gate dielectric layer of the transistor. Thus, conductive substrate 100 can also be regarded as the gate electrode, and dielectric layer 120 can also be regarded as the gate dielectric layer. In some embodiments, dielectric layer 120 and substrate 100 can be jointly regarded as a gate structure.

[0090] Reference Figure 13B . 2D material buffer layer 111 and 2-D material channel layer 110 are sequentially formed on dielectric layer 120. In some embodiments, 2-D material buffer layer 111 and 2-D material channel layer 110 can be made of the same material. In some embodiments, 2-D material buffer layer 111 and 2-D material channel layer 110 can be formed by suitable deposition processes, such as atomic layer deposition as described above. In other embodiments, each of 2-D material buffer layer 111 and 2-D material channel layer 110 can be formed by polydimethylsiloxane transfer and then followed by the annealing process as described above.

[0091] Reference Figure 13C . Source / drain electrodes 150 are formed on 2-D material channel layer 110. In some embodiments, each source / drain electrode 150 includes a first metal layer 130 and a second metal layer 140 above the first metal layer 130.

[0092] Reference Figure 13D . Source / drain electrodes 150 are patterned, so that each source / drain electrode 150 includes a protruding portion 150P that protrudes laterally from the main portion 150M of each source / drain electrode 150. In some embodiments, the protruding portion 150P of source / drain electrode 150 is narrower than the main portion 150M of source / drain electrode 150 along a direction substantially perpendicular to the current flow direction.

[0093] Reference Figure 13E。A 2-D material buffer layer 112 is formed and covers the substrate 100. Subsequently, the 2-D material buffer layer 112, the 2-D material channel layer 110, and the 2-D material buffer layer 111 are patterned. More specifically, the partially exposed 2-D material channel layer 110 and the partially exposed 2-D material buffer layer 111 are patterned by the source / drain electrodes 150. More specifically, a patterning process is performed such that the partially exposed 2-D material channel layer 110 is narrowed by the source / drain electrodes 150 in a direction substantially perpendicular to the current flow direction, thereby defining the channel region 110CH of the 2-D material channel layer 110. The 2-D material buffer layer 111 is patterned together with the 2-D material channel layer 110 such that the 2-D material buffer layer 111 may include substantially the same profile as the 2-D material channel layer 110. On the other hand, the 2-D material buffer layer 112 may include substantially the same profile as the channel region 110CH of the 2-D material channel layer 110. In some embodiments, the patterning process may include electron beam lithography.

[0094] In some embodiments, the 2-D material buffer layer 112 may be formed by a suitable deposition process, such as atomic layer deposition as described above. In other embodiments, the 2-D material buffer layer 112 may be formed by polydimethylsiloxane transfer and then followed by the annealing process as described above.

[0095] Reference Figure 13F 。A passivation layer 160 is formed on the 2-D material buffer layer 112. Thus, the passivation layer 160 may cover and contact the upper surface of the 2-D material buffer layer 112. It is worth noting that although the passivation layer 160 shown herein only covers the upper surface of the 2-D material buffer layer 112, the passivation layer 160 may also extend to the sidewalls of the 2-D material buffer layer 112, the sidewalls of the 2-D material channel layer 110, and the sidewalls of the 2-D material buffer layer 111. In some embodiments, the passivation layer 160 may also cover the upper surface of the source / drain electrodes 150.

[0096] Figure 14A and Figure 14B are diagrams of semiconductor devices according to some embodiments of the present disclosure. More specifically, Figure 14A and Figure 14B are according to some embodiments of the present disclosure, Figure 13F top views of the devices shown. It should be noted that for simplicity, only the source / drain electrodes 150 and the 2-D material channel layer 110 are shown in the Figure 14A and Figure 14B top views.

[0097] Reference Figure 14A。Each source / drain electrode 150 includes a main portion 150M and a protruding portion 150P extending from the main portion 150M along the X direction. In some embodiments, along the Y direction, the width W1 of the protruding portion 150P is smaller than the width W2 of the main portion 150M. In some embodiments, the width W1 is about 500 nm. In some embodiments, the distance between the protruding portion 150P of one source / drain electrode 150 and the protruding portion 150P of another source / drain electrode 150 is about 600 nm.

[0098] On the other hand, the 2-D material channel layer 110 includes a channel region 110CH and source / drain regions 110SD opposing the channel region 110CH. In some embodiments, each source / drain region 110SD may include a first portion 110SD_1 (vertically positioned below the protruding portion 150P of the respective source / drain electrode 150) and a second portion 110SD_2 (vertically positioned below the main portion 150M of the respective source / drain electrode 150). In some embodiments, the first portion 110SD_1 is narrower than the second portion 110SD_2 along the Y direction. In addition, the first portion 110SD_1 of the source / drain region 110SD has a width W3 along the Y direction, and the channel region 110CH also includes a width W3 along the Y direction. That is to say, the first portion 110SD_1 of the source / drain region 110SD and the channel region 110CH substantially have the same width. In some embodiments, the width W3 is larger than the width W1 and smaller than the width W2.

[0099] Reference Figure 14B 。 Figure 14B and Figure 14A The difference is that the channel region 110CH includes a width W4 along the Y direction, which is larger than the width W3 of the first portion 110SD_1 of the source / drain region 110SD. This is because in the channel definition process (as described in Section 13E), the channel region 110CH may not be protected by the source / drain electrode 150, so a wider channel region 110CH can provide sufficient buffering for the etching process.

[0100] In some embodiments where the 2-D material channel layer 110 is made of molybdenum disulfide, a polycrystalline molybdenum disulfide film (instead of a single-crystalline molybdenum disulfide film) is obtained as a sample of wafer-level molybdenum disulfide. Other possible mechanisms (which affect device performance) may come from carrier scattering at the molybdenum disulfide grain boundaries. To explore this phenomenon, devices with reduced linewidths are fabricated. After the source / drain electrodes 150 are formed, electrodes extending from the source / drain electrodes 150 (such as the protruding portion 150P) are fabricated. To avoid excessive current flow from the large source / drain electrodes 150 to the channel region 110CH, a channel region 110CH and source / drain electrodes 150 with reduced linewidths are formed. Figure 15 is the transfer curve graph of the device when VDS = 1.0V. Compared with devices with larger linewidths (see Figure 11 and Figure 12 ), the device can be observed to have a larger field-effect mobility value (63.80 cm 2 V -1 S -1 ) and ON / OFF ratio (>10 6 ), which may be due to reduced carrier scattering in the polycrystalline molybdenum disulfide channel. In addition, a higher leakage current density (about 90 μA / μm) is also observed in the device. This result also demonstrates that the crystallinity of the molybdenum disulfide film is a major issue for device performance.

[0101] According to the embodiments described above, it can be understood that the present disclosure provides advantages for manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and no particular advantage is necessarily required for all embodiments. The embodiments of the present disclosure provide a method for generating semiconductor devices with a 2-D material channel layer. In some embodiments, the 2-D material channel layer can be generated by atomic layer deposition or by polydimethylsiloxane transfer and annealing processes, thereby reducing the surface roughness of the 2-D material channel, but reducing device performance. In other embodiments, a 2-D material buffer layer can be generated above or below the 2-D material channel layer, thereby preventing the influence of dangling bonds / defects / pad scattering at the interface between the 2-D material channel layer and the dielectric layer. In other embodiments, a passivation layer can be generated above the 2-D material channel layer to prevent the 2-D material channel layer from being exposed to air. In other embodiments, the linewidths of the 2-D material channel layer and the source / drain electrodes are reduced to further improve device performance.

[0102] According to at least one embodiment of the present disclosure, a method includes: generating a gate electrode in contact with a gate dielectric layer; generating a first 2-D material buffer layer on the gate dielectric layer; generating a 2-D material channel layer on the first 2-D material buffer layer; and generating a plurality of source / drain electrodes on a plurality of source / drain regions of the 2-D material channel layer.

[0103] In some embodiments, it further includes generating a second 2-D material buffer layer on the 2-D material channel layer.

[0104] In some embodiments, the first 2-D material buffer layer and the second 2-D material buffer layer are made of a different 2-D material from the 2-D material channel layer.

[0105] In some embodiments, the 2-D material channel layer is in contact with the plurality of source / drain electrodes.

[0106] In some embodiments, the generation of the 2-D material channel layer is by: performing a first polydimethylsiloxane (PDMS) transfer process to transfer the 2-D material channel layer to the first 2-D material buffer layer; and performing a first annealing process to reduce a surface roughness of the 2-D material channel layer.

[0107] In some embodiments, the generation of the first 2-D material buffer layer is by: performing a second polydimethylsiloxane (PDMS) transfer process to transfer the first 2-D material buffer layer to the gate dielectric layer; and performing a second annealing process to reduce a surface roughness of the first 2-D material buffer layer.

[0108] In some embodiments, it further includes, after generating the plurality of source / drain electrodes, generating a passivation layer to cover an upper surface of the 2-D material channel layer.

[0109] According to at least one embodiment of the present disclosure, a method includes: generating a gate electrode in contact with a gate dielectric layer; generating a 2-D material channel layer on the gate dielectric layer, wherein the generation of the 2-D material channel layer is by: generating the 2-D material channel layer on a first carrier; transferring the 2-D material channel layer from the first carrier to the gate dielectric layer; and performing a first annealing process to reduce a surface roughness of the 2-D material channel layer; and generating a plurality of source / drain electrodes on a plurality of source / drain regions of the 2-D material channel layer.

[0110] In some embodiments, it further includes, before generating the 2-D material channel layer, generating a 2-D material buffer layer on the gate dielectric layer, wherein the 2-D material channel layer is in contact with the 2-D material buffer layer.

[0111] In some embodiments, after generating the plurality of source / drain electrodes, a 2-D material buffer layer is further formed on the 2-D material channel layer.

[0112] In some embodiments, after generating the plurality of source / drain electrodes, a dielectric passivation layer is further formed to cover an upper surface of the 2-D material channel layer.

[0113] In some embodiments, after generating the plurality of source / drain electrodes, a first patterning process is performed on an exposed portion of the 2-D material channel, thereby narrowing the 2-D material channel layer along a first direction.

[0114] In some embodiments, before performing the first patterning process, a second patterning process is performed on the plurality of source / drain electrodes, such that each of the plurality of source / drain electrodes includes a main portion and a protruding portion, and the protruding portion extends from the main portion along a second direction perpendicular to the first direction.

[0115] In some embodiments, after the first patterning process is completed, a channel region of the 2-D material channel layer is located between the plurality of source / drain electrodes, and a source / drain region is located below the protruding portion of one of the plurality of source / drain electrodes, wherein the channel region is wider than the source / drain region along the first direction.

[0116] In some embodiments, the protruding portion is narrower than the main portion along the first direction.

[0117] According to at least one embodiment of the present disclosure, a semiconductor device includes: a gate electrode; a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; and a plurality of source / drain electrodes on the 2-D material channel layer.

[0118] In some embodiments, the first 2-D material buffer layer and the 2-D material channel layer are made of different 2-D materials.

[0119] In some embodiments, a second 2-D material buffer layer is further included on the 2-D material channel layer.

[0120] In some embodiments, each of the plurality of source / drain electrodes includes a main portion and a protruding portion, the protruding portion extends from the main portion along a first direction, and the protruding portion is narrower than the main portion in a second direction perpendicular to the first direction.

[0121] In some embodiments, the 2-D material channel layer has a channel region between the plurality of source / drain electrodes, and a source / drain region is under a protruding portion of one of the plurality of source / drain electrodes, wherein the channel region is wider than the source / drain region along the second direction.

[0122] According to at least one embodiment of the present disclosure, a semiconductor device includes: a gate electrode;

[0123] a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; a second 2-D material buffer layer on the 2-D material channel layer; and a plurality of source / drain electrodes on the 2-D material channel layer.

[0124] In some embodiments, a passivation layer is further included on the second 2-D material buffer layer.

[0125] In some embodiments, the second 2-D material buffer layer is located between the source / drain electrodes.

[0126] According to at least one embodiment of the present disclosure, a semiconductor device includes: a gate electrode; a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; a second 2-D material buffer layer on the 2-D material channel layer; a plurality of source / drain electrodes on the 2-D material channel layer; and a passivation layer on the second 2-D material buffer layer. In some embodiments, the second 2-D material buffer layer is located between the source / drain electrodes.

[0127] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor element, characterized in that: Include: a gate electrode; a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; and A plurality of source / drain electrodes are formed on top of the 2-D material channel layer.

2. The semiconductor device according to claim 1, wherein: The first 2-D material buffer layer and the 2-D material channel layer are made of different 2-D materials.

3. The semiconductor device according to claim 2, wherein: A second 2-D material buffer layer is also included on the 2-D material channel layer.

4. The semiconductor device according to claim 1, wherein: Each of the plurality of source / drain electrodes includes a main portion and a protruding portion, the protruding portion extends from the main portion along a first direction, and the protruding portion is narrower than the main portion along a second direction perpendicular to the first direction.

5. The semiconductor device according to claim 4, wherein: The 2-D material channel layer has a channel region between the multiple source / drain electrodes, and a source / drain region is below the protruding portion of one of the multiple source / drain electrodes, wherein the channel region is wider than the source / drain region along the second direction.

6. A semiconductor element, characterized in that: Include: a gate electrode; a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; a second 2-D material buffer layer on the 2-D material channel layer; as well as A plurality of source / drain electrodes are formed on top of the 2-D material channel layer.

7. The semiconductor device according to claim 6, wherein: A passivation layer is also included and is located on the second 2-D material buffer layer.

8. The semiconductor device according to claim 6, wherein: The second 2-D material buffer layer is located between the multiple source / drain electrodes.

9. A semiconductor element, characterized in that: Include: a gate electrode; a gate dielectric layer in contact with the gate electrode; a first 2-D material buffer layer on the gate dielectric layer; a 2-D material channel layer on the first 2-D material buffer layer; a second 2-D material buffer layer on the 2-D material channel layer; a plurality of source / drain electrodes on the 2-D material channel layer; and A passivation layer is located on the second 2-D material buffer layer.

10. The semiconductor device according to claim 9, wherein: The second 2-D material buffer layer is located between the multiple source / drain electrodes.

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