Package structure

Abstract

A package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through-substrate via structure formed in the first substrate. A buffer layer surrounds the first substrate, and a first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate, and a second bonding layer formed over the second device. A hybrid bonding structure is located between the first package structure and the second package structure, and is formed by bonding the first bonding layer to the second bonding layer.

Description

Technical Field

[0001] The content of the present creative embodiment relates to a packaging structure, and particularly to a packaging structure with high yield, high quality and high reliability. Background Art

[0002] Semiconductor devices are used in various electronic product applications, such as personal computers, mobile phones, digital cameras and other electronic devices. The manufacturing of semiconductor devices is usually carried out by sequentially depositing an insulating layer or a dielectric layer, a conductive layer and a semiconductor material layer on a semiconductor substrate, and using lithography to pattern each material layer, and forming circuit components and elements thereon. Many integrated circuits are usually manufactured on a single semiconductor wafer, and the individual die on the wafer are separated by cutting along scribe lines between the integrated circuits. For example, in a multi-chip module, or in other types of packages, the individual die are usually packaged separately.

[0003] New packaging technologies, such as package on package (PoP), have been developed, in which a top package having a device die is bonded to a bottom package having another device die. By adopting these new packaging technologies, various packages with different functions or similar functions can be integrated together.

[0004] Although existing packaging structures and methods for manufacturing packaging structures are generally sufficient to meet their intended purposes, they are not entirely satisfactory in all aspects. Summary of the Utility Model

[0005] The purpose of the present utility model is to provide a packaging structure to solve at least one of the above problems.

[0006] Some embodiments of the present utility model provide a packaging structure, including a first packaging structure and a second packaging structure. The first packaging structure includes a first device formed above a first substrate. This first device includes a first conductive plug connected to a substrate via-hole structure formed in the first substrate. A buffer layer surrounds the first substrate, and a first bonding layer is formed above the first substrate and the buffer layer. The second packaging structure includes a second device formed above a second substrate, and a second bonding layer formed above the second device. A hybrid bonding structure is located between the first packaging structure and the second packaging structure and is formed by bonding the first bonding layer to the second bonding layer.

[0007] According to one embodiment of the present utility model, the hybrid bonding structure includes a first conductive material embedded in a first insulating layer and a second conductive material embedded in a second insulating layer.

[0008] According to one embodiment of the present utility model, a width of the first substrate is smaller than a width of the second substrate.

[0009] According to one embodiment of the present utility model, the first substrate is in direct contact with the buffer layer.

[0010] According to one embodiment of the present utility model, a top surface of the buffer layer is coplanar with a top surface of the first substrate.

[0011] According to one embodiment of the present utility model, a top surface of the buffer layer is higher than an interface between the first conductive plug and the substrate via structure in the first substrate.

[0012] According to one embodiment of the present utility model, the second encapsulation structure further includes a second substrate via structure.

[0013] According to one embodiment of the present utility model, the first device further includes: nanostructures formed above the first substrate; a source / drain structure formed adjacent to the plurality of nanostructures; a source / drain contact structure formed above the source / drain structure; and a second conductive plug connected to the first conductive plug and the source / drain contact structure.

[0014] According to one embodiment of the present utility model, the first device further includes: an interconnect structure formed on the plurality of nanostructures, wherein the first bonding layer is formed above the interconnect structure.

[0015] According to one embodiment of the present utility model, the interconnect structure is located on a top surface of the buffer layer and a top surface of the substrate via structure, and the top surface of the buffer layer is coplanar with the top surface of the substrate via structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The content of the embodiments of the present utility model can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to the industrial standard practice, many components (features) are not drawn to scale. In fact, for the purpose of clear discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0017] Figures 1A - 1H A perspective view showing multiple stages of forming a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figures 2A to 2CShows, according to some embodiments, after Figure 1H along Figure 1H a cross-sectional schematic view of multiple stages of manufacturing a semiconductor structure as shown by line A-A' in

[0019] Figures 3A to 3B Shows, according to some embodiments, after Figure 2B along Figure 1H a cross-sectional schematic view of multiple stages of manufacturing a semiconductor structure as shown by line B-B' in

[0020] Figure 4 Shows, according to some embodiments, a cross-sectional schematic view of a semiconductor structure as shown by line C-C' in Figure 1H

[0021] Figures 5A to 5F Shows a cross-sectional schematic view of multiple stages of manufacturing a package structure according to some embodiments.

[0022] Figure 5C ' is Figure 5C a top view of a package structure according to some embodiments of

[0023] Figure 6A Shows, according to some embodiments, Figure 5A an enlarged cross-sectional schematic view of a semiconductor structure of

[0024] Figure 6B Shows, according to some embodiments, Figure 5E an enlarged cross-sectional schematic view of a semiconductor structure of

[0025] Figure 6C Shows, according to some embodiments, Figure 5F an enlarged cross-sectional schematic view of a semiconductor structure of

[0026] Figures 7A to 7B Shows a cross-sectional schematic view of multiple stages of manufacturing a package structure according to some embodiments.

[0027] Figures 8A to 8C Shows a cross-sectional schematic view of multiple stages of manufacturing a package structure according to some embodiments.

[0028] Figures 9A to 9F Shows a cross-sectional schematic view of multiple stages of manufacturing a package structure according to some embodiments.

[0029] Figures 10A to 10F Shows a cross-sectional schematic view of multiple stages of manufacturing a package structure according to some embodiments.

[0030] The reference numerals are as follows:

[0031] ​10: Semiconductor structure

[0032] 100a, 100b, 100c, 200a, 300a, 300b: Encapsulation structure

[0033] 102, 202: Substrate

[0034] 102a, 202a: Front surface

[0035] 102b, 202b: Back surface

[0036] 104a: First fin structure

[0037] 104b: Second fin structure

[0038] 106: First semiconductor material layer

[0039] 108: Second semiconductor material layer

[0040] 108’: Nanostructure

[0041] 110: Mask structure

[0042] 111: Isolation material

[0043] 113, 143, 145: Trench

[0044] 114, 150: Conductive plug

[0045] 114a, 172a, 272a: Barrier layer

[0046] 114b, 162, 172b, 184, 272b, 284: Conductive layer

[0047] 115: Dielectric plug

[0048] 116: Isolation structure

[0049] 118:Dummy gate structure

[0050] 120: Dummy gate dielectric layer

[0051] 122: Dummy gate electrode layer

[0052] 126: Gate spacer

[0053] 134: Inner spacer

[0054] 136: Source / drain structure

[0055] 138: Contact etch stop layer

[0056] 140: Interlayer dielectric layer

[0057] 142: Gate structure

[0058] 144: Interface layer

[0059] 146: Gate dielectric layer

[0060] 148: Gate electrode layer

[0061] 152, 160, 240: Dielectric layer

[0062] 154: Silicide layer

[0063] 156: Source / drain contact structure

[0064] 164, 182, 264: Interconnection structure

[0065] 167: Adhesion layer

[0066] 168: Carrier substrate

[0067] 172, 272: Substrate via structure

[0068] 176: Buffer layer

[0069] 178: Stop layer

[0070] 179: Opening

[0071] 186, 286: Insulating layer

[0072] 188: First bonding layer

[0073] 190: Device area

[0074] 204: Device element

[0075] 288: Second bonding layer

[0076] 290: Protective layer

[0077] 292: UBM layer

[0078] 294: Connector

[0079] 350: Hybrid bonding structure

[0080] A - A’, B - B’, C - C’, D - D’: Lines

[0081] T 1 : First thickness

[0082] T 2 : Second thickness Detailed implementation manners

[0083] The following provides many different embodiments or examples for implementing different components of the embodiments of the present utility model. Specific examples of components and configurations are described below to simplify the embodiments of the present utility model. Of course, these are merely examples and are not intended to limit the embodiments of the present utility model. For example, when it is described that a first component is formed above or on a second component, it may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and the second components such that the first and second characteristic components are not in direct contact. Additionally, the embodiments of the present utility model may repeat element symbols and / or letters in many examples. These repetitions are for the purposes of simplicity and clarity and do not themselves represent a particular relationship between the various embodiments and / or configurations being discussed.

[0084] Some variations of the embodiments are described below. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that some additional steps may be performed before, during, and after these methods, and for other embodiments of these methods, some of the described steps may be replaced or eliminated.

[0085] The embodiments may also include other components and processes. For example, testing structures may be included to assist in validating 3D packages or 3D integrated circuit (3DIC) devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow the use of 3D packages or 3D integrated circuits, probes, and / or probe cards for testing, etc. The above-mentioned validation tests may be performed on intermediate structures and final structures. Additionally, the structures and methods disclosed herein may be used in combination with test methods incorporating intermediate verification of known good dies to improve yield and reduce costs.

[0086] Embodiments provide a packaging structure and a method of forming the same. The aforementioned packaging structure includes encapsulating a first die having a semiconductor structure into a second die. The aforementioned semiconductor structure includes a device above a substrate at a wafer level, and a conductive plug formed in the aforementioned substrate. Each semiconductor structure (or integrated circuit (IC)) on the wafer can be tested by a wafer test system before being separated or "diced" from the wafer for packaging. After passing the test, a known good chip without defects in the integrated circuit (IC) chip can be diced from the wafer.

[0087] The substrate of the known good die is flipped and placed on a carrier substrate. The back surface of the substrate of the die is exposed, and a buffer layer is formed above the surface of the back surface of the substrate. The buffer layer is used to improve the polishing uniformity of the substrate during a planarization process (such as a chemical mechanical polishing (CMP) process). A planarization process is performed on a part of the buffer layer and a part of the substrate to form a thinned substrate. Through-Substrate Via (TSV) structures are formed in the thinned substrate to connect to the conductive plugs formed before the planarization process. Since the die is a known good die and the polishing uniformity of the substrate can be well controlled with the assistance of the buffer layer. In this way, the yield, quality, and reliability of the packaging structure can be improved.

[0088] Figures 1A - 1H A perspective view showing multiple stages of forming a semiconductor structure 10 according to some embodiments of the present disclosure is shown.

[0089] As Figure 1A shown, first semiconductor material layers 106 and second semiconductor material layers 108 are formed above a substrate 102. The substrate 102 includes a front surface 102a and a back surface 102b. The first semiconductor material layers 106 and the second semiconductor material layers 108 are formed above the front surface 102a of the substrate 102.

[0090] The substrate 102 can be a semiconductor chip, such as a silicon chip. Alternatively or additionally, the substrate 102 can include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. The aforementioned elemental semiconductor materials can include, but are not limited to, crystalline silicon, polysilicon, amorphous silicon, germanium, and / or diamond. The aforementioned compound semiconductor materials can include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The aforementioned alloy semiconductor materials can include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0091] In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are alternately stacked above the substrate 102. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the material of the first semiconductor material layer 106 is silicon germanium (SiGe), and the material of the second semiconductor material layer 108 is silicon. It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are formed, the semiconductor structure can include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure can include two to five first semiconductor material layers 106 and two to five second semiconductor material layers.

[0092] The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed by low-pressure chemical vapor deposition (LPCVD), an epitaxial growth process, other suitable methods, or a combination of the foregoing. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0093] Subsequently, according to some embodiments, after forming the first semiconductor material layer 106 and the second semiconductor material layer 108 into a semiconductor material stack above the substrate 102, the semiconductor material stack is patterned to form a first fin structure 104a and a second fin structure 104b. In some embodiments, each of the first fin structure 104a and the second fin structure 104b includes a base fin structure and a semiconductor material stack including the first semiconductor material layer 106 and the second semiconductor material layer 108.

[0094] In some embodiments, the aforementioned patterning process includes forming a mask structure 110 above the semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multi-layer structure including a pad oxide layer and a nitride layer formed above the pad oxide layer. The pad oxide layer can be made of silicon oxide, which is formed by thermal oxidation or chemical vapor deposition (CVD), and the nitride layer can be made of silicon nitride, which is formed by chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD).

[0095] Next, as Figure 1B shown, according to some embodiments, after forming the first fin structure 104a and the second fin structure 104b, an isolation material 111 is formed around the first fin structure 104a and the second fin structure 104b. Next, a portion of the isolation material 111 and the mask structure 110 are removed by a planarization process such as a chemical mechanical polishing (CMP) process.

[0096] The isolation material 111 is made of a low dielectric constant dielectric material with a dielectric constant (K value) in the range of about 1 to about 5. In some embodiments, the isolation material 111 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or a combination of the foregoing materials. In some embodiments, the isolation material 111 is formed by a low-pressure chemical vapor deposition (LPCVD) process, a plasma-assisted chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDP-CVD) process, a high aspect ratio process (HARP), a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, other suitable methods, or a combination of the foregoing methods.

[0097] Next, as Figure 1C shown, according to some embodiments, a trench 113 is formed to pass through a portion of the isolation material 11 and the substrate 102. The trench 113 is formed by an etching process, such as a dry etching process or a wet etching process.

[0098] After that, as Figure 1D shown, according to some embodiments, a barrier layer 114a and a conductive layer 114b are formed in the trench 113. A conductive plug 114 is composed of the barrier layer 114a and the conductive layer 114b. In some embodiments, the conductive plug 114 is formed to be connected to a power rail.

[0099] The barrier layer 114a is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials. In some embodiments, the barrier layer 114a is formed by using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0100] The conductive layer 114b can be made of a conductive material. In some embodiments, the conductive layer 114b is made of tungsten (W), ruthenium (Ru), molybdenum (Mo), etc. In some embodiments, a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, is performed to form the conductive layer 114b.

[0101] Next, as Figure 1E shown, according to some embodiments, the top portion of the conductive plug 114 is removed. After removal, the trench 113 can be exposed. The isolation material 111 is exposed by the trench 113. In some embodiments, the top portion of the conductive plug 114 can be removed by an etching process, such as a dry etching process or a wet etching process.

[0102] After that, as Figure 1F shown, according to some embodiments, a dielectric plug 115 is filled into the trench 113. The dielectric plug 115 can include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination of the foregoing materials. In some embodiments, a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, is performed to form this dielectric plug 115.

[0103] After that, as Figure 1G shown, according to some embodiments, a portion of the isolation material 111 and a portion of the dielectric plug 115 are removed to form an isolation structure 116. The top surface of the isolation structure 116 is substantially coplanar with the top surface of the dielectric plug 115.

[0104] According to some embodiments, the isolation structure 116 is configured to electrically isolate the active regions (e.g., fin structures, such as the first fin structure 104a and the second fin structure 104b) of the semiconductor structure 10, and the isolation structure 116 can also be referred to as a shallow trench isolation (STI) component.

[0105] After that, as Figure 1H shown, according to some embodiments, a dummy gate structure 118 is formed above the first fin structure 104a and the second fin structure 104b and above the isolation structure 116.

[0106] In some embodiments, the dummy gate structure 118 includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122. In some embodiments, the dummy gate dielectric layer 120 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO 2 , HfZrO, HfSiO, HfTiO, HfAlO, or a combination of the foregoing materials. In some embodiments, thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or a combination of the foregoing methods are used to form the dummy gate dielectric layer 120. In some embodiments, the dummy gate dielectric layer 120 is made of a conductive material. The foregoing conductive materials include polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metals, or a combination of the foregoing materials. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of the foregoing methods can be used to form the foregoing dummy gate electrode layer 122.

[0107] Figures 2A to 2C Shows, according to some embodiments, in Figure 1H After, along Figure 1H A cross-sectional schematic diagram of multiple stages of manufacturing the semiconductor structure 10 as shown by line A-A' in

[0108] As Figure 2A Shown, according to some embodiments, the first fin structure 104a and the second fin structure 104b are formed above the substrate 102 and extend above the isolation structure 116.

[0109] After, as Figure 2B Shown, according to some embodiments, the top portions of the first fin structure 104a and the top portions of the second fin structure 104b are removed to form source / drain recesses (not shown) in the source / drain region. The source / drain (S / D) region can refer to a source or a drain individually, or to the source and the drain collectively, depending on the context.

[0110] According to some embodiments, after forming the source / drain (S / D) recesses, the first semiconductor material layer 106 exposed by the source / drain (S / D) recesses is laterally recessed to form notches (not shown). Next, according to some embodiments, inner spacers 134 (as Figure 4 shown) are formed in the notches between the second semiconductor material layers 108. According to some embodiments, the inner spacers 134 are configured to separate the source / drain (S / D) structures and the gate structures formed in subsequent manufacturing processes. In some embodiments, the inner spacers 134 are made of a dielectric material, such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxide, silicon oxynitride carbon (SiOCN), or a combination of the foregoing materials. In some embodiments, the inner spacers 134 are formed by a deposition process, such as by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable processes, or a combination of the foregoing processes to form the inner spacers 134.

[0111] After that, according to some embodiments, after forming the inner spacers 134, source / drain (S / D) structures 136 are formed in the source / drain (S / D) recesses. In some embodiments, an epitaxial growth process, such as molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), other suitable epitaxial growth processes, or a combination of the foregoing methods, can be used to form the source / drain structures 136. In some embodiments, the source / drain structures 136 can be made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination of the foregoing materials.

[0112] In some embodiments, the source / drain structure 136 is doped in-situ during the epitaxial growth process. For example, the source / drain structure 136 can be epitaxially grown SiGe doped with boron (B). For example, the source / drain structure 136 can be epitaxially grown silicon doped with carbon to form Si:C source / drain features, or doped with phosphorus to form Si:P source / drain features, or doped with carbon and phosphorus to form SiCP source / drain features. In some embodiments, the source / drain structure 136 is doped in one or more implantation processes after the epitaxial growth process.

[0113] Next, according to some embodiments, after forming the source / drain structure 136, a contact etch stop layer (CESL) 138 is conformally formed on the source / drain structure 136 to cover the source / drain structure 136, and an interlayer dielectric (ILD) layer 140 is formed above the contact etch stop layer 138.

[0114] In some embodiments, the contact etch stop layer (CESL) 138 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, other suitable dielectric materials, or a combination of the foregoing materials. The dielectric material for the contact etch stop layer (CESL) 138 can be conformally deposited on the semiconductor structure by performing chemical vapor deposition (CVD), atomic layer deposition (ALD), other applicable methods, or a combination of the foregoing methods.

[0115] The interlayer dielectric layer 140 can include multiple layers made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other suitable low-k dielectric materials. The interlayer dielectric layer 140 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0116] According to some embodiments, after depositing the contact etch stop layer (CESL) 138 and the interlayer dielectric layer 140, a planarization process, such as chemical mechanical polishing (CMP) or an etch-back process, may be performed until the gate electrode layer 122 of the dummy gate structure 118 is exposed, as Figure 2B shown.

[0117] Figures 3A to 3B FIG. shows a cross-sectional schematic diagram of multiple stages of manufacturing the semiconductor structure 10 along the line B-B' in Figure 2B after Figure 1H according to some embodiments.

[0118] As Figure 3A shown, according to some embodiments, after forming the interlayer dielectric layer 140, the dummy gate structure 118 is replaced with a gate structure 142. The gate structure 142 is formed along a second direction (e.g., the Y-axis).

[0119] More specifically, according to some embodiments, the dummy gate structure 118 is removed to form a trench 143, and the first semiconductor material layer 106 is removed to form a trench 145. Accordingly, nanostructures 108' having the second semiconductor material layer 108 can be formed. The source / drain structure 136 is also attached to the nanostructures 108'.

[0120] The above removal process may include one or more etching processes. For example, when the dummy gate electrode layer 122 is polysilicon, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the dummy gate electrode layer 122. Thereafter, methods such as plasma dry etching, dry chemical etching, and / or wet etching may be used to remove the dummy gate dielectric layer 120. The first semiconductor material layer 106 can be removed by performing a selective wet etching process, such as an APM (e.g., a mixture of ammonium hydroxide - hydrogen peroxide - water) etching process. For example, the aforementioned wet etching process uses etchants such as ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solutions. In some embodiments, the upper portion of the gate spacers 126 is also removed.

[0121] After forming the nanostructure 108’, a gate structure 142 is formed to surround the nanostructure 108’. According to some embodiments, the gate structure 142 surrounds the nanostructure 108’ to form a gate-all-around transistor structure. In some embodiments, the gate structure 142 includes an interfacial layer 144, a gate dielectric layer 146, and a gate electrode layer 148.

[0122] In some embodiments, the interfacial layer 144 is an oxide layer formed on the top of the nanostructure 108’ and the bottom fin structure. In some embodiments, the interfacial layer 144 is formed by performing a heat treatment.

[0123] In some embodiments, the gate dielectric layer 146 is formed above the interfacial layer 144 such that the nanostructure 108’ is surrounded (e.g., wrapped) by the gate dielectric layer 146. Furthermore, according to some embodiments, the gate dielectric layer 146 also covers the sidewalls of the gate spacer 126 and the sidewalls of the inner spacer 134. In some embodiments, the gate dielectric layer 146 is made of one or more dielectric materials, such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloy, other suitable high-k dielectric materials, or a combination of the foregoing materials. In some embodiments, chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination of the foregoing methods are used to form the gate dielectric layer 146.

[0124] In some embodiments, a gate electrode layer 148 is formed on the gate dielectric layer 146. In some embodiments, the gate electrode layer 148 is made of one or more layers of conductive materials such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations of the foregoing materials. In some embodiments, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable methods, or combinations of the foregoing methods are used to form the gate electrode layer 148. Other conductive layers, such as work function metal layers or the like, may also be formed in the gate structure 142, although they are not shown in the figures. In some embodiments, the n-type work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations of the foregoing materials. In some embodiments, the p-type work function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride, tungsten nitride (WN), ruthenium (Ru), or combinations of the foregoing materials.

[0125] After forming the foregoing interface layer 144, the foregoing gate dielectric layer 146, and the foregoing gate electrode layer 148, a planarization process, such as chemical mechanical polishing (CMP) or an etch-back process, may be performed until the interlayer dielectric layer 140 is exposed.

[0126] Figure 4 Shown is a cross-sectional schematic view of a semiconductor structure 10 taken along line C-C' in accordance with some embodiments. Figure 1H as shown in

[0127] Figure 4 Shown is the semiconductor structure 10 after the gate structure 142 is formed. Inner spacers 134 are formed between the source / drain (S / D) structures 136 and the gate structure 142. Gate spacers 126 are formed on opposite sidewall surfaces of the gate structure 142. The inner spacers 134 are formed directly below the gate spacers 126. The nanostructure 108' is surrounded by the gate structure 142.

[0128] Next, referring to Figure 2C, According to some embodiments, after forming the gate structure 142, a conductive plug 150 is formed to penetrate the interlayer dielectric layer 140, and a dielectric layer 152 is formed above the interlayer dielectric layer 140. Then, a silicide layer 154 and a source / drain contact structure 156 are formed above the source / drain structure 136. The conductive plug 150 is formed on the interface layer 144 and is electrically connected to the interface layer 144. Also, the conductive plug 150 is electrically connected to the source / drain contact structure 156 and the interface layer 144.

[0129] The aforementioned conductive plug 150 can be formed in the following manner. For example, an opening is formed, and this opening penetrates the interlayer dielectric layer 140, the contact etch stop layer 138, the dielectric plug 115, and the isolation structure 116 to expose the conductive plug 114. Then, a barrier layer and a conductive material are formed in the opening to form the aforementioned conductive plug 150.

[0130] The dielectric layer 152 can include multiple layers made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other suitable low-k dielectric materials. The dielectric layer 152 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0131] In some embodiments, a contact opening can be formed to penetrate the contact etch stop layer 138, the interlayer dielectric layer 140, and the dielectric layer 152 to expose the top surface of the source / drain structure. Then, the silicide layer 154 and the source / drain contact structure 156 can be formed in the contact opening. A lithography process and an etching process can be used to form the contact opening. Furthermore, in the aforementioned etching process, some portions of the source / drain structure exposed by the contact opening may also be etched.

[0132] The aforementioned silicide layer 154 can be formed by forming a metal layer above the top surface of the source / drain structure 136 and annealing this metal layer so that the metal layer reacts with the source / drain structure 136 to form the silicide layer 154. After forming the silicide layer 154, the unreacted metal layer can be removed.

[0133] The source / drain (S / D) contact structure 156 may include a barrier layer and a conductive layer. In some other embodiments, the source / drain (S / D) contact structure 156 does not include a barrier layer. In some embodiments, the barrier layer is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials. In some embodiments, the above-mentioned barrier layer can be formed by using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process. In some embodiments, the above-mentioned conductive layer is made of tungsten (W), ruthenium (Ru), molybdenum (Mo), or similar materials. In some embodiments, the above-mentioned conductive layer is formed by performing a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0134] Next, an interconnect structure 164 is formed over the dielectric layer 152. The interconnect structure 164 can be used as a redistribution layer (RDL) structure for wiring. The interconnect structure 164 includes a plurality of conductive layers 162 formed in a plurality of dielectric layers 160. The conductive plug 114 can be electrically connected to the conductive layer 162 of the interconnect structure 160 through the conductive plug 150 and the source / drain (S / D) contact structure 156.

[0135] The above-mentioned conductive layer 162 is made of a metal material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy. In some embodiments, the above-mentioned conductive layer 162 can be formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process, or physical vapor deposition (PVD) process.

[0136] Figures 5A to 5F A cross-sectional schematic diagram showing multiple stages of manufacturing a package structure 100a according to some embodiments is shown. Figure 5C ’ is Figure 5C A top view of the package structure 100a according to some embodiments. Figure 5C is according to some embodiments, along Figure 5C A cross-sectional schematic diagram of the package structure 100a shown along the DD' line of ’.

[0137] Figure 6A A cross-sectional schematic diagram showing an enlarged semiconductor structure 10 according to some embodiments is shown. And Figure 5A ofFigure 6B Shows a cross-sectional schematic diagram of an enlarged semiconductor structure 10 according to some embodiments. Furthermore, Figure 5E Shows a cross-sectional schematic diagram of an enlarged semiconductor structure 10 according to some embodiments. Figure 6C Shows a cross-sectional schematic diagram of an enlarged semiconductor structure 10 according to some embodiments. Figure 5F Shows a cross-sectional schematic diagram of an enlarged semiconductor structure 10 according to some embodiments.

[0138] As Figure 5A And Figure 6A Shown, according to some embodiments, the semiconductor structure 10 in the form of a die or chip is obtained from Figure 2C And the semiconductor structure 10 is inverted top to bottom and placed above a carrier substrate 168 through an adhesive layer 167 ( Figure 6A Shown). The back surface 102b of the substrate 102 is away from the carrier substrate 168. The front surface 102a of the substrate 102 is closer to the carrier substrate 168 than the back surface 102b of the substrate 102.

[0139] A device region 190 is formed above the substrate 102. The remaining structure of the device region 190 is as Figure 6A Shown, and for clarity, is not shown in detail in Figure 5A . The device region 190 includes all the layers and all the structures formed above the substrate 102. In some embodiments, the device region 190 includes conductive plugs 114, isolation structures 116, source / drain structures 136, contact etch stop layers (CESL) 138, interlayer dielectric layers 140, conductive plugs 150, dielectric layers 152, silicide layers 154, source / drain contact structures 156, dielectric layers 160, conductive layers 162, and interconnect structures 164.

[0140] After a series of manufacturing processes are performed on the semiconductor structure 10 at the wafer level, each semiconductor structure (or integrated circuit (IC)) on the wafer can be tested via a wafer test system before they are separated or "singulated" for packaging. After passing the wafer test, a known good chip without defects can be cut from the integrated circuit (IC) chips on the wafer. In some embodiments, the semiconductor structure 10 is an integrated circuit (IC) die cut from the wafer and is a "known good die". Therefore, the semiconductor structure 10 is in the form of a die or chip, rather than a wafer form. In some embodiments, the integrated circuit (IC) die is a logic die, a memory die, or other suitable types of dies.

[0141] The above-mentioned adhesive layer 167 serves as a temporary adhesive layer. This adhesive layer 167 can be glue or a tape. In some embodiments, the adhesive layer 167 is photosensitive and can be easily separated from the carrier substrate 118 by light irradiation. For example, ultraviolet (UV) light or laser irradiation is used on the carrier substrate 168 to separate the adhesive layer. In some embodiments, the adhesive layer 167 is a light-to-heat-conversion (LTHC) coating. In some other embodiments, the adhesive layer 167 is heat-sensitive and can be easily separated from the carrier substrate 168 when exposed to heat.

[0142] The original substrate 102 has a first thickness T in the vertical direction. 1 . In some embodiments, the first thickness T of the substrate 102 1 is in the range of approximately 10 μm to approximately 30 μm.

[0143] After that, as Figure 5B shown, according to some embodiments, a buffer layer 176 is formed on the back surface 102b of the substrate 102, on one sidewall surface of the substrate 102, and on the carrier substrate 168. The substrate 102 and the buffer layer 176 are in direct contact. The aforementioned buffer layer 176 is used to improve the polishing uniformity of the substrate 102 during a planarization process (such as a chemical mechanical polishing (CMP) process).

[0144] In some embodiments, the buffer layer 176 is made of an oxide, such as silicon oxide. In some embodiments, the buffer layer 176 is formed by a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDP-CVD) process, a high aspect ratio process (HARP) process, a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, other suitable methods, or a combination of the foregoing methods.

[0145] After that, as Figure 5C and Figure 5C ' shown, according to some embodiments, the buffer layer 176 is patterned to form openings 179. The back surface 102b of the substrate 102 is exposed by the openings 179. The semiconductor structure 10 is surrounded by the buffer layer 176.

[0146] In some embodiments, the buffer layer 176 is patterned by a patterning process. The aforementioned patterning process includes a lithography process and an etching process. The lithography process includes photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The aforementioned etching process may include a dry etching process or a wet etching process.

[0147] Next, as Figure 5D shown, according to some embodiments, a planarization process is performed on the buffer layer 176 and the substrate 102. By the aforementioned planarization process, the top of the buffer layer 176 and the top of the substrate 102 of the semiconductor structure 10 can be removed simultaneously.

[0148] The aforementioned planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other suitable processes, or a combination of the aforementioned methods. In some embodiments, the aforementioned planarization process includes multiple chemical mechanical polishing (CMP) processes.

[0149] By forming the buffer layer 176 around the substrate 102 of the semiconductor structure 102, the downward pressure between the back surface 102b of the target back side of the substrate 102 and the polishing surface of the polishing pad can be more uniform, so that the topography variation of the substrate 102 can be well controlled.

[0150] During the planarization process, as the thickness of the substrate 102 gradually decreases, the topography variation of the substrate 102 gradually decreases. Accordingly, the substrate 102 can have a more uniform and smooth topography.

[0151] The chemical mechanical polishing (CMP) process includes applying an abrasive in a solution (referred to as a slurry) to the surface of the substrate 102 and then polishing this surface. Additives in the solution react chemically with the surface material being polished to soften it, and the highest components of the substrate 102 and the buffer layer 176 are removed by the abrasive particles of the chemical mechanical polishing (CMP) process.

[0152] In a comparative example, a SiGe layer is formed on a substrate (e.g., Si) as a stop layer, and the removal amount of the substrate is controlled. In these embodiments, the buffer layer 176 is formed on the substrate 102 (e.g., Si) and is in direct contact with the substrate 102, and there is no other layer (e.g., SiGe layer) on the substrate 102. Therefore, the manufacturing cost can be reduced.

[0153] After that, as Figure 5E and Figure 6BAs shown, according to some embodiments, after the planarization process, a portion of the substrate 102 is removed. In some embodiments, a portion of the substrate 102 is removed from the backside surface 102b of the substrate 102 until a predetermined thickness of the substrate 102 is reached. The thinned substrate 102 has a second thickness T 2 , the second thickness T 2 is less than Figure 5A the first thickness T of the original substrate 102 in 1 . In some embodiments, the second thickness T of the thinned substrate 102 2 is in the range of about 0.05 μm to about 0.8 μm.

[0154] After the planarization process, the buffer layer 176 still surrounds the semiconductor structure 10, and the top surface of the backside surface 102b of the substrate 102 is substantially coplanar with the top surface of the remaining buffer layer 176.

[0155] Next, as Figure 5F and Figure 6C shown, according to some embodiments, after obtaining the thinned substrate 102, a through substrate via (TSV) structure 172 is formed in the substrate 102 to connect the conductive plug 114. One of the through substrate via (TSV) structures 172 is electrically connected to one of the conductive plugs 114. In some embodiments, the conductive plug 114 is formed to connect to a power rail. In some other embodiments, the through substrate via (TSV) structure 172 may be referred to as a through-silicon via. It should be noted that the top surface of the buffer layer 176 is higher than the interface between the conductive plug 114 and the through substrate via (TSV) structure 172.

[0156] In some embodiments, each through substrate via (TSV) structure 172 includes a barrier layer 172a and a conductive layer 172b formed on the barrier layer 172a. The barrier layer 172a is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials. In some embodiments, the barrier layer 172a is formed by using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0157] The conductive layer 172b can be made of a conductive material. In some embodiments, the conductive layer 172b is made of tungsten (W), ruthenium (Ru), molybdenum (Mo), or the like. In some embodiments, a deposition process is performed to form the conductive layer 172b, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0158] It is noted that the substrate 102 in the encapsulation structure 100a is a single die cut from a wafer, and the substrate 102 is a known good die, so the yield of the encapsulation structure 100a is improved.

[0159] Furthermore, the buffer layer 176 is used to improve the polishing uniformity of the substrate 102 during a planarization process (such as a chemical mechanical polishing (CMP) process) without using a SiGe layer. Therefore, the manufacturing cost of the encapsulation structure 100a can be reduced.

[0160] Figures 7A to 7B A cross-sectional schematic diagram showing multiple stages of manufacturing the encapsulation structure 100b according to some embodiments is shown. Figure 7A The shown encapsulation structure 100b is Figure 5B similar or identical to the shown encapsulation structure 100a, except that a stop layer 178 is formed on the buffer layer 176. The processes and materials used to form the encapsulation structure 100b can be similar or identical to the processes and materials used to form the encapsulation structure 100a, and will not be repeated here.

[0161] As Figure 7A shown, the stop layer 178 is conformally formed above the buffer layer 176. The material of the stop layer 178 is different from the material of the buffer layer 176. The removal rate of the stop layer 178 is different from the removal rate of the buffer layer 176. Therefore, the stop layer 178 serves as a removal stop layer while the buffer layer 176 is being removed.

[0162] It is noted that after the stop layer 178 is completely removed, the chemical mechanical polishing (CMP) process is immediately stopped to minimize the removal of the underlying layer. The stop layer 178 can serve as a detection layer to assist the chemical mechanical polishing (CMP) process. After the chemical mechanical polishing (CMP) process, the stop layer 178 is completely removed, and the remaining buffer layer 176 still surrounds the semiconductor structure 10.

[0163] In some embodiments, the foregoing stop layer 178 is made of silicon nitride, and the foregoing buffer layer 176 is made of a silicon oxide layer. In some embodiments, the foregoing stop layer 178 can be formed by a low-pressure chemical vapor deposition (LPCVD) process, a plasma-assisted chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDP-CVD) process, a high aspect ratio process (HARP) process, a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, other suitable methods, or a combination of the foregoing methods.

[0164] After that, as Figure 7B shown, according to some embodiments, after performing a planarization process, a portion of the substrate 102 is removed. In some embodiments, a portion of the substrate 102 is removed from the backside surface 102b of the substrate 102 until a predetermined thickness of the substrate 102 is reached.

[0165] Figures 8A to 8C A cross-sectional schematic diagram showing multiple stages of manufacturing a packaging structure 100c according to some embodiments is shown. Figure 8A The shown packaging structure 100c is similar or identical to Figure 5A the shown packaging structure 100a, except that the through-substrate via (TSV) structure is formed before performing the planarization process. The processes and materials used to form the packaging structure 100c can be similar or identical to the processes and materials used to form the packaging structure 100a, and will not be described in detail herein.

[0166] As Figure 8A shown, according to some embodiments, the through-substrate via (TSV) structure 172 is pre-formed in the substrate 102, and the semiconductor structure 10 is flipped and placed above the carrier substrate 168. One of the through-substrate via (TSV) structures 172 is electrically connected to one of the conductive plugs 114 before the planarization process. More specifically, the through-substrate via (TSV) structure 172 is pre-formed in the substrate 102 before dicing individual dies of the semiconductor structure 10 from the wafer.

[0167] Next, as Figure 8B shown, according to some embodiments, the buffer layer 176 is formed on the semiconductor structure 10. More specifically, the buffer layer 176 covers the top surface of the backside surface 102b of the substrate 102 and the sidewall surface of the substrate 102. The buffer layer 176 is used to improve the polishing uniformity of the substrate 102 during a planarization process (e.g., a chemical mechanical polishing (CMP) process).

[0168] After that, as Figure 8CAs shown, according to some embodiments, after the planarization process, the through-substrate via (TSV) structure 172 is exposed. The exposed top surface of the through-substrate via (TSV) structure 172 is substantially coplanar with the top surface of the buffer layer 176.

[0169] Figures 9A to 9F A cross-sectional schematic diagram showing multiple stages of manufacturing a package structure 300a according to some embodiments is shown. The package structure 300a can be a chip-on-wafer-on-substrate (CoWoS) package or other suitable package. The package structure 300a can be a system on integrated circuit (SoIC) device that includes two or more chips with integrated functions.

[0170] As Figure 9A shown, the package structures 100a, 100b, or 100c are obtained from Figure 5F , Figure 7B or Figure 8C and an interconnect structure 182 is formed on the substrate 102 and the buffer layer 176 of the package structures 100a, 100b, or 100c. Then, a bonding layer 188 is formed on the interconnect structure 182, and the package structure 100a is turned upside down.

[0171] The interconnect structure 182 includes conductive layers and vias embedded in a dielectric layer. The illustrated interconnect structure 182 is for illustrative purposes only. The interconnect structure 182 can include other configurations, and the interconnect structure 182 can include one or more wire and via layers.

[0172] The first bonding layer 188 includes a plurality of conductive layers 184 embedded in an insulating layer 186. These conductive layers 184 are contact pads (or bond pads) formed on the top surface of the interconnect structure 182. The conductive layers 184 can be made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination of the foregoing materials. Other suitable materials can also be used to fabricate the conductive layers 184. In some embodiments, the insulating layer 186 is made of silicon oxide. In some embodiments, the insulating layer 186 includes a plurality of dielectric layers of a dielectric material. In some other embodiments, the insulating layer 186 can be made of a polymer, such as benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or other suitable materials to form the insulating layer 186.

[0173] Next, as Figure 9B shown, according to some embodiments, through-silicon via (TSV) structures 272 are formed in the substrate 202. The substrate 202 includes a front side surface 202a and a back side surface 202b.

[0174] Each through-silicon via (TSV) structure 272 can include a barrier layer 272a and a conductive layer 272b on the barrier layer 272a. The barrier layer 272a is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials. In some embodiments, the barrier layer 272a is formed by using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0175] The conductive layer 272b can be made of a conductive material. In some embodiments, the conductive layer is made of tungsten (W), ruthenium (Ru), molybdenum (Mo), or the like. In some embodiments, the conductive layer 272b is formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0176] After that, as Figure 9CAs shown, device elements 204 are formed in a dielectric layer 240 above a substrate 202. The device elements 204 include active elements (e.g., transistors, diodes, or the like) and / or passive elements (e.g., resistors, capacitors, inductors, or the like). In some embodiments, the device elements 204 include a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, a high bandwidth memory (HBM) device, or other memory devices. In some embodiments, the device elements 204 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.), diodes, and / or other suitable elements. Various processes are performed to form these device elements 204, such as deposition, etching, implantation, lithography, annealing, and / or other suitable processes. In some embodiments, the device elements 204 are fabricated in the front-end-of-line (FEOL) and formed in the substrate 202.

[0177] Then, an interconnect structure 264 is formed above the dielectric layer 240 to form a second package structure 200a. The interconnect structure 264 includes a plurality of conductive layers and a plurality of vias embedded in the dielectric layer. The interconnect structure 264 can serve as a redistribution (RDL) structure for routing.

[0178] Next, a second bonding layer 288 is formed above the interconnect structure 264. The second bonding layer 288 is similar to the first bonding layer 188. The second bonding layer 288 includes a conductive layer 284 embedded in an insulating layer 286. The conductive layer 284 is contact pads (or bond pads) formed on the top surface of the interconnect structure 264. The conductive layer 284 can be made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination of the foregoing materials. Other suitable materials can be used to form the conductive layer 284. In some embodiments, the insulating layer 286 is made of silicon oxide. In some embodiments, the insulating layer 286 includes a plurality of dielectric layers made of a dielectric material. In some other embodiments, the insulating layer 286 is made of a polymer, such as benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or other suitable materials.

[0179] After that, as Figure 9D shown, according to some embodiments, Figure 9A the first package structure 100a of Figure 9C is aligned with the second package structure 200a of

[0180] The width of the substrate 102 of the first package structure 100a is less than the width of the substrate 202 of the second package structure 200a.

[0181] Next, as Figure 9E shown, according to some embodiments, after alignment, Figure 9A the first package structure 100a of Figure 9C and the second package structure 200a of 2 can be bonded together, and this hybrid bonding can form the package structure 300a. The first package structure 100a and the second package structure 200a can be hybrid bonded together by applying pressure and heat. The foregoing hybrid bonding process can be carried out in an inert environment, such as an environment filled with an inert gas including N

[0182] As Figure 9EAs shown, a hybrid bonding structure 350 is formed between a first packaging structure 100a and a second packaging structure 200a. This hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding. The aforementioned hybrid bonding structure 350 includes a conductive layer 184 and a conductive layer 284 bonded by metal-to-metal bonding, and an insulating layer 186 and an insulating layer 286 bonded by non-metal-to-non-metal bonding. The aforementioned hybrid bonding structure 350 has a metallic bonding interface between the conductive layer 184 and the conductive layer 284, but may not have a clear non-metallic interface between the insulating layer 186 and the insulating layer 286.

[0183] Next, according to some embodiments, a portion of the substrate 202 is removed. In some embodiments, the substrate 202 is thinned from the front surface 202a until the through-substrate via (TSV) structure 272 is exposed. In some embodiments, the substrate 202 is thinned by a planarization process. The aforementioned planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other suitable methods, or a combination of the aforementioned methods.

[0184] After that, as Figure 9F shown, a passivation layer 290 is formed under the substrate 202, and the passivation layer 290 is patterned to form a plurality of openings. These openings expose portions of the through-substrate via (TSV) structure 272.

[0185] The passivation layer 290 is made of a dielectric material and can provide stress relief for the bonding stress generated during subsequent bonding processes. In some embodiments, the passivation layer 290 is made of PBO, BCB, silicone, acrylate, siloxane, other suitable materials, or a combination of the aforementioned materials. In some other embodiments, the passivation layer 290 is made of a non-organic material. The aforementioned non-organic materials include silicon oxide, un-doped silicate glass, silicon oxynitride, silicon resin (SR), silicon nitride, silicon carbide, hexamethyldisilazane (HMDS), other suitable materials, or a combination of the aforementioned materials.

[0186] Next, an under bump metal layer (hereinafter referred to as the UBM layer) 292 is formed in the opening, and connectors 294 are formed above the UBM layer 292. The UBM layer 292 may include an adhesion layer and / or a wetting layer. In some embodiments, the UBM layer 292 is made of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), or the like. In some embodiments, the UBM layer 292 further includes a copper seed layer. In some embodiments, the UBM layer 292 and the connectors 294 are formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process, physical vapor process, or other suitable processes.

[0187] The connectors 294 are formed above the protective layer 290. The connectors 294 are electrically connected to the through-silicon via (TSV) structure 272. In some embodiments, the connectors 294 may be referred to as controlled collapse chip connection (C4) bumps or micro-bumps. The conductive connectors 294 are made of solder, such as tin (Sn), tin-silver (SnAg), tin-lead (SnPb), tin-copper (SnCu), tin-silver-copper (SnAgCu), tin-silver-zinc (SnAgZn), tin-zinc (SnZn), tin-bismuth-indium (SnBiIn), tin-indium (SnIn), tin-gold (SnAu), tin-zinc-indium (SnZnIn), tin-silver-antimony (SnAgSb), or other suitable materials. In some embodiments, the conductive connectors 294 are formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process, physical vapor process, or other suitable processes.

[0188] Figures 10A to 10F A cross-sectional schematic diagram showing multiple stages of manufacturing a package structure 300b according to some embodiments is shown. The processes and materials used to form the package structure 300b may be similar or the same as those used to form the package structure 300a, and will not be described in detail herein.

[0189] As Figure 10A shown, according to some embodiments, a through-silicon via (TSV) structure 272 is formed in the substrate 202. The substrate 202 includes a front side surface 202a and a back side surface 202b. The through-silicon via (TSV) structure 272 is formed from the front side surface 202a of the substrate 202.

[0190] Each substrate through - silicon via (TSV) structure 272 may include a barrier layer 272a and a conductive layer 272b on the barrier layer 272a. The barrier layer 272a is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials. In some embodiments, the barrier layer 272a is formed by using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma - enhanced chemical vapor deposition (PECVD), plasma - enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0191] The conductive layer 272b may be made of a conductive material. In some embodiments, the conductive layer is made of tungsten (W), ruthenium (Ru), molybdenum (Mo), or the like. In some embodiments, the conductive layer 272b is formed by performing a deposition process, such as forming the conductive layer 272b by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0192] Next, as Figure 10B shown, according to some embodiments, a dielectric layer 240 is formed above the substrate through - silicon via (TSV) structure 272 above the substrate 202, and device elements 204 are formed in the dielectric layer 240. In some embodiments, the device elements 204 include a static random - access memory (SRAM) device, a dynamic random - access memory (DRAM) device, a high - bandwidth memory (HBM) device, or other memory devices. In some embodiments, the device elements 204 include active elements (e.g., transistors, diodes, or the like) and / or passive elements (e.g., resistors, capacitors, inductors, or the like). In some embodiments, the device elements 204 include transistors (e.g., metal - oxide - semiconductor field - effect transistors (MOSFETs), complementary metal - oxide - semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high - voltage transistors, high - frequency transistors, p - channel and / or n - channel field - effect transistors (PFET / NFET), etc.), diodes, and / or other applicable elements. Various processes are performed to form the device elements 204, such as deposition, etching, implantation, lithography, annealing, and / or other suitable processes. In some embodiments, the device elements 204 are formed in the substrate 202 in the front - end - of - line (FEOL) process.

[0193] Then, an interconnect structure 264 is formed above the dielectric layer 240. The interconnect structure 264 includes conductive layers and vias embedded in the dielectric layer.

[0194] After that, as Figure 10CAs shown, according to some embodiments, the substrate 202 is flipped and a portion of the substrate 202 is removed to form a second encapsulation structure 200b. A portion of the substrate 202 is removed from the backside surface 202b by a planarization process to expose the substrate through - via (TSV) structure 272. The aforementioned planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other suitable processes, or a combination of the foregoing processes.

[0195] Next, as Figure 10D shown, a second bonding layer 288 is formed over the exposed substrate through - via (TSV) structure 272 and the backside surface 202b of the substrate 202, and according to some embodiments, Figure 9A the first encapsulation structure 100a and Figure 10C the second encapsulation structure 200b are aligned with each other.

[0196] The second bonding layer 288 is similar to the first bonding layer 188. The second bonding layer 288 includes a conductive layer 284 embedded in an insulating layer 286. More specifically, the conductive layer 184 of the first bonding layer 188 is aligned with the conductive layer 284 of the second bonding layer 288. The insulating layer 186 of the first bonding layer 188 is aligned with the insulating layer 286 of the second bonding layer 288. In some embodiments, the alignment of the first encapsulation structure 100a and the second encapsulation structure 200b can be achieved by an optical sensing method.

[0197] After that, as Figure 10E shown, according to some embodiments, after alignment, Figure 9A the first encapsulation structure 100a and Figure 10C the second encapsulation structure 200b are bonded together by hybrid bonding to form an encapsulation structure 300b. The first encapsulation structure 100a and the second encapsulation structure 200b are bonded together by applying pressure and heat. The hybrid bonding process can be performed in an inert environment, such as an environment filled with an inert gas including N 2 , Ar, He, or a combination of the foregoing gases.

[0198] As Figure 10E shown, a hybrid bonding structure 350 is formed between the first encapsulation structure 100a and the second encapsulation structure 200b. Hybrid bonding involves at least two types of bonding, including metal - to - metal bonding and non - metal - to - non - metal bonding. The hybrid bonding structure 350 includes the conductive layer 184 and the conductive layer 284 bonded by metal - to - metal bonding, and the insulating layer 186 and the insulating layer 286 bonded by non - metal - to - non - metal bonding.

[0199] Next, asFigure 10F As shown, according to some embodiments, a protective layer 290 is formed under the interconnect structure 264, and the protective layer 290 is patterned to form a plurality of openings. Then, the UBM layer 292 is formed in the openings, and the connecting member 294 is formed above the UBM layer 292.

[0200] The protective layer 290 is made of a dielectric material and provides stress relief for the bonding stress generated during subsequent bonding processes. In some embodiments, the protective layer 290 is made of PBO, BCB, silicone, acrylate, siloxane, other suitable materials, or a combination of the foregoing materials. In some other embodiments, the protective layer 290 is made of a non-organic material. Non-organic materials include silicon oxide, undoped silicate glass, silicon oxynitride, silicone rubber (SR), silicon nitride, silicon carbide, hexamethyldisilazane (HMDS), other suitable materials, or a combination of the foregoing materials.

[0201] The connecting member 294 is formed above the protective layer 290. The connecting member 294 is electrically connected to the through-silicon via (TSV) structure 272 through the conductive layer of the interconnect structure 264. In some embodiments, the connecting member 294 is referred to as a controlled collapse chip connection (C4) bump or a micro-bump.

[0202] The first package structure 100a, 100b, or 100c is bonded to the second package structure 200a or 200b to form a hybrid bonded package structure 300a or 300b. The first die of the package structures 100a, 100b, or 100c is cut from a wafer and is a known good die that has passed testing. Since the first die is a known good die, the yield and reliability are improved. Furthermore, the substrate 102 of the first die is thinned to form a through-silicon via (TSV) structure 172 by using a buffer layer instead of a SiGe layer. This also reduces the manufacturing cost.

[0203] Embodiments provide a method for forming a packaging structure. First, a semiconductor structure is formed, and the semiconductor structure includes devices formed above a substrate and a conductive plug formed in the substrate. Known good die containing the semiconductor structure are obtained from a wafer. Next, the known good die in the form of a die or chip is flipped and placed on a carrier substrate. The back surface of the substrate is exposed, and a buffer layer is formed above the surface of the back surface of the substrate. This buffer layer is used to improve the polishing uniformity of the substrate during a planarization process (such as a chemical mechanical polishing (CMP) process). A planarization process is performed on a part of the buffer layer and a part of the substrate to form a thinned substrate. Through-silicon via (TSV) structures are formed in the thinned substrate to connect to the conductive plugs formed before the planarization process. Since the die are known good die and the polishing uniformity of the substrate can be well controlled by means of the buffer layer. In this way, the yield, quality, and reliability of the packaging structure can be improved.

[0204] In some embodiments, a method for forming a packaging structure is provided. The method includes forming a first die above a carrier substrate, and the first die includes a first substrate having a first thickness and a first conductive plug formed in the first substrate. The method further includes forming a buffer layer above the first die and the first substrate, and the buffer layer covers a top surface and a sidewall surface of the first die. The method includes removing a part of the buffer layer to form a trench in the buffer layer and exposing the first substrate through the trench. The method includes performing a planarization process on the buffer layer and the first substrate of the first chip to form a thinned first substrate, and the thinned first substrate has a second thickness less than the first thickness. After the planarization process, the method includes forming through-silicon via structures in the thinned first substrate. One of the through-silicon via structures is electrically connected to the first conductive plug.

[0205] In some embodiments, the method for forming the encapsulation structure further includes: forming a stop layer above the buffer layer before performing the aforementioned planarization process. In some embodiments, the method for forming the encapsulation structure further includes: forming a dielectric layer above the first substrate of the first die; and forming a second conductive plug in the dielectric layer, wherein the second conductive plug is connected to the first conductive plug. In some embodiments, the method for forming the encapsulation structure further includes: forming a first bonding layer above the buffer layer and the substrate via structure, wherein the first bonding layer includes a first conductive layer embedded in a first insulating layer. In some embodiments, the method for forming the encapsulation structure further includes: forming a second die having a second bonding layer above a second substrate, wherein a width of the second substrate is greater than a width of the first substrate; and bonding the first bonding layer to the second bonding layer to form a bonding structure between the first die and the second die. In some embodiments, in the method for forming the encapsulation structure, the first conductive plug is formed on a front side surface of the first substrate, and the buffer layer is formed on a rear side surface of the first substrate. In some embodiments, in the method for forming the encapsulation structure, the first die is cut from a wafer. In some embodiments, in the method for forming the encapsulation structure, a top surface of the buffer layer is higher than an interface between the first conductive plug and one of the substrate via structures. In some embodiments, in the method for forming the encapsulation structure, the first die further includes: nanostructures formed on the first substrate; a source / drain structure formed adjacent to the nanostructures; a source / drain contact structure formed above the source / drain structure; and a second conductive plug connected to the first conductive plug and the source / drain contact structure.

[0206] In some embodiments, a method for forming an encapsulation structure is provided. The method includes forming a first die above a carrier substrate, and the first die includes a first substrate and a first conductive plug formed in the first substrate. The method includes forming a buffer layer on the first die, and the first die is surrounded by the buffer layer. The method further includes removing a portion of the buffer layer and a portion of the first substrate to form a thinned first substrate surrounded by the remaining buffer layer. The method includes forming a first bonding layer on the thinned first substrate and the remaining buffer layer to form a first encapsulation structure. The method includes bonding the first encapsulation structure to a second encapsulation structure by bonding the first bonding layer to a second bonding layer.

[0207] In some embodiments, the method for forming the provided packaging structure further includes: forming a plurality of substrate via structures in the foregoing first substrate; and exposing the foregoing substrate via structures after removing the foregoing portion of the foregoing first substrate. In some embodiments of the method for forming the provided packaging structure, one of the foregoing substrate via structures is connected to the foregoing first conductive plug. In some embodiments, the method for forming the provided packaging structure further includes: forming a nanostructure above the foregoing first substrate; forming an interconnect structure on the foregoing nanostructure; and forming the foregoing first bonding layer above the foregoing interconnect structure. In some embodiments of the method for forming the provided packaging structure, the foregoing first substrate is in direct contact with the foregoing buffer layer before removing the foregoing portion of the foregoing buffer layer and the foregoing portion of the foregoing first substrate. In some embodiments of the method for forming the provided packaging structure, the foregoing first die is cut from a wafer.

[0208] In some embodiments, a packaging structure is provided. The packaging structure includes a first packaging structure and a second packaging structure. The first packaging structure includes a first device formed above a first substrate. The first device includes a first conductive plug connected to a substrate via structure formed in the first substrate. A buffer layer surrounds the first substrate, and a first bonding layer is formed above the first substrate and the buffer layer. The second packaging structure includes a second device formed above a second substrate and a second bonding layer formed above the second device. The packaging structure further includes a hybrid bonding structure formed by bonding the first bonding layer to the second bonding layer, and the hybrid bonding structure is located between the first packaging structure and the second packaging structure.

[0209] In some embodiments of the provided packaging structure, the hybrid bonding structure includes a first conductive material embedded in a first insulating layer and a second conductive material embedded in a second insulating layer. In some embodiments of the provided packaging structure, a width of the foregoing first substrate is less than a width of the foregoing second substrate. In some embodiments of the provided packaging structure, the foregoing second packaging structure further includes a second substrate via structure. In some embodiments of the provided packaging structure, the foregoing first device further includes: a nanostructure formed above the foregoing first substrate; a source / drain structure formed adjacent to the foregoing nanostructure; a source / drain contact structure formed above the foregoing source / drain structure; and a second conductive plug connected to the foregoing first conductive plug and the foregoing source / drain contact structure.

[0210] The above outlines the components of several embodiments so that those skilled in the art to which the present utility model pertains can better understand the viewpoints of the embodiments of the present utility model. Those skilled in the art to which the present utility model pertains should understand that they can easily design or modify other processes and structures based on the embodiments of the present utility model to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present utility model pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present utility model, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present utility model. Therefore, the protection scope of the present utility model shall be defined by the appended claims.

Claims

1. A packaging structure, characterized in that: include: A first packaging structure, wherein the first packaging structure comprises: a first device formed on a first substrate, wherein the first device includes a first conductive plug connected to a substrate through-hole structure formed in the first substrate; a buffer layer surrounding the first substrate; and a first bonding layer formed on the first substrate and the buffer layer; and a second packaging structure, wherein the second packaging structure comprises: a second device formed on a second substrate; and a second bonding layer formed over the second device; and A hybrid bonding structure is formed by bonding the first bonding layer to the second bonding layer and is located between the first packaging structure and the second packaging structure.

2. The packaging structure according to claim 1, characterized in that: The hybrid junction structure includes a first conductive material embedded in a first insulating layer and a second conductive material embedded in a second insulating layer.

3. The packaging structure according to claim 1, characterized in that: A width of the first substrate is smaller than a width of the second substrate.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: The first substrate is in direct contact with the buffer layer.

5. The packaging structure according to any one of claims 1 to 3, characterized in that: A top surface of the buffer layer is coplanar with a top surface of the first substrate.

6. The packaging structure according to any one of claims 1 to 3, characterized in that: A top surface of the buffer layer is higher than an interface between the first conductive plug and the substrate through hole structure in the first substrate.

7. The packaging structure according to any one of claims 1 to 3, characterized in that: The second packaging structure also includes a second through substrate via structure.

8. The packaging structure according to any one of claims 1 to 3, characterized in that: The first device also includes: A nanostructure is formed on the first substrate; a source / drain structure formed adjacent to the plurality of nanostructures; a source / drain contact structure formed above the source / drain structure; and A second conductive plug is connected to the first conductive plug and the source / drain contact structure.

9. The packaging structure according to claim 8, characterized in that: The first device also includes: an interconnection structure formed on the plurality of nanostructures, The first bonding layer is formed above the interconnect structure.

10. The packaging structure according to claim 9, characterized in that: The interconnection structure is located on a top surface of the buffer layer and a top surface of the substrate through-hole structure, and the top surface of the buffer layer and the top surface of the substrate through-hole structure are coplanar.

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