Battery cell voltage sampling control circuit, battery management system and energy storage device

Abstract

The utility model provides a cell voltage sampling control circuit, a battery management system and an energy storage device. The circuit comprises a sampling control sub-circuit, a reference voltage sampling sub-circuit and at least one group of main sampling sub-circuit and branch sampling sub-circuit, the main sampling sub-circuit and the branch sampling sub-circuit in the same group are connected with the voltage sampling pin of the same battery cell of the front-end analog chip, and the main sampling sub-circuit and the branch sampling sub-circuit are respectively connected with the positive electrode ends of different battery cells; and the reference voltage sampling sub-circuit is respectively connected with the negative electrode end of the battery module consisting of the plurality of battery cells and the negative electrode voltage sampling pin of the front-end analog chip. As the same cell voltage sampling pin of the front-end analog chip can be connected with two different cells through the same group of main sampling sub-circuit and branch sampling sub-circuit, the function of sampling the voltage of the two cells by the same cell voltage sampling pin can be realized, and the device power consumption and the sampling cost in the cell voltage sampling link are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of battery management, in particular to a cell voltage sampling control circuit, a battery management system and an energy storage device. Background Art

[0002] At present, in order to monitor the working state of cells in a battery pack, an analog front-end chip is usually used to collect the cell voltage, so as to provide effective data basis for battery management.

[0003] In the related art, usually only one cell voltage sampling pin of the analog front-end chip can collect the voltage of one cell, that is, the relationship between the cell and the cell voltage sampling pin of the sampling chip is one-to-one. When the number of cells increases exponentially, more analog front-end chips are required to meet the voltage sampling requirements of each cell, resulting in higher device power consumption and sampling cost in the cell voltage sampling link. Summary of the Utility Model

[0004] The utility model provides a cell voltage sampling control circuit, a battery management system and an energy storage device, so as to solve the defect that only one cell voltage sampling pin of the current analog front-end chip can collect the voltage of one cell, resulting in higher device power consumption and sampling cost in the cell voltage sampling link.

[0005] On the one hand, the utility model provides a cell voltage sampling control circuit, which is arranged between an analog front-end chip and multiple cells. The circuit includes: a sampling control sub-circuit, a reference voltage sampling sub-circuit, and at least one group of main sampling sub-circuits and branch sampling sub-circuits;

[0006] The input ends of the sampling control sub-circuit are respectively connected to the first control pin and the second control pin of the analog front-end chip, and the output ends of the sampling control sub-circuit are respectively connected to the main sampling sub-circuit and the branch sampling sub-circuit of each group;

[0007] The main sampling sub-circuit and the branch sampling sub-circuit of the same group are both connected to the same cell voltage sampling pin of the front-end analog chip, and the main sampling sub-circuit and the branch sampling sub-circuit are respectively connected to the positive electrodes of different cells;

[0008] The reference voltage sampling sub-circuit is respectively connected to the negative electrode of the battery module composed of the multiple cells and the negative voltage sampling pin of the front-end analog chip.

[0009] According to the cell voltage sampling control circuit provided by the utility model, the sampling control sub-circuit includes: a logic gate module, and at least one group of first switch modules and second switch modules;

[0010] The first input terminal of the logic gate module is connected to the first control pin of the analog front-end chip, the second input terminal of the logic gate module is connected to the second control pin of the analog front-end chip, the first output terminal of the logic gate module is respectively connected to at least one of the first switch modules, and the second output terminal of the logic gate module is respectively connected to at least one of the second switch modules;

[0011] The first switch module is arranged in the main sampling sub-circuit, and the second switch module is arranged in the branch sampling sub-circuit.

[0012] According to the cell voltage sampling control circuit provided by the present invention, the logic gate module includes: a first AND gate, a second AND gate, and a NOT gate;

[0013] The first input terminal of the first AND gate is connected to the NOT gate, the first input terminals of the NOT gate and the second AND gate are both connected to the second control pin of the analog front-end chip, the second input terminals of the first AND gate and the second AND gate are both connected to the first control pin of the analog front-end chip, the output terminal of the first AND gate is respectively connected to at least one of the first switch modules, and the output terminal of the second AND gate is respectively connected to at least one of the second switch modules.

[0014] According to the cell voltage sampling control circuit provided by the present invention, the first switch module includes: a first MOS transistor and a first auxiliary sub-module;

[0015] The first MOS transistor is arranged in the main sampling sub-circuit, the first MOS transistor is connected to the first auxiliary sub-module, and the first auxiliary sub-module is connected to the first output terminal of the logic gate module.

[0016] According to the cell voltage sampling control circuit provided by the present invention, the second switch module includes: a second MOS transistor and a second auxiliary sub-module;

[0017] The second MOS transistor is arranged in the branch sampling sub-circuit, the second MOS transistor is connected to the second auxiliary sub-module, and the second auxiliary sub-module is connected to the second output terminal of the logic gate module.

[0018] According to the cell voltage sampling control circuit provided by the present invention, the main sampling sub-circuit includes: a first bead, a first resistor, a second resistor, a first capacitor, and a second capacitor;

[0019] The first magnetic bead is respectively connected to the positive electrode of the corresponding battery cell and the first switching module. The first resistor is respectively connected to the first switching module and the second resistor. The second resistor is connected to the battery cell voltage sampling pin of the front-end analog chip. The first capacitor is connected to the line between the first resistor and the first switching module. The second capacitor is connected to the line between the first resistor and the second resistor. Both the first capacitor and the second capacitor are grounded.

[0020] According to the battery cell voltage sampling control circuit provided by the present utility model, the branch sampling sub-circuit includes: at least one second magnetic bead;

[0021] The second magnetic bead is respectively connected to the positive electrode of the corresponding battery cell and the second switching module. The second switching module is connected to the line between the first resistor and the first switching module.

[0022] According to the battery cell voltage sampling control circuit provided by the present utility model, the reference voltage sampling sub-circuit includes: a third magnetic bead, a third resistor, a fourth resistor, a third capacitor, and a fourth capacitor;

[0023] The third magnetic bead is respectively connected to the negative electrode end of the battery module composed of the plurality of battery cells and the third resistor. The third resistor is connected to the fourth resistor. The fourth resistor is connected to the negative electrode voltage sampling pin of the front-end analog chip. The third capacitor is connected to the line between the third magnetic bead and the third resistor. The fourth capacitor is connected to the line between the third resistor and the fourth resistor. Both the third capacitor and the fourth capacitor are grounded.

[0024] On the other hand, the present utility model also provides a battery management system, including the battery cell voltage sampling control circuit described in any one of the above.

[0025] On the other hand, the present utility model also provides an energy storage device, including the battery cell voltage sampling control circuit described in any one of the above or the above battery management system.

[0026] The cell voltage sampling control circuit, battery management system, and energy storage device provided by the present utility model, by setting a sampling control sub-circuit, a reference voltage sampling sub-circuit, and at least one group of main sampling sub-circuits and branch sampling sub-circuits, both the main sampling sub-circuit and the branch sampling sub-circuit of the same group are connected to the same cell voltage sampling pin of the front-end analog chip. The main sampling sub-circuit and the branch sampling sub-circuit are respectively connected to the positive electrodes of different cells, and the reference voltage sampling sub-circuit is respectively connected to the negative electrode of the battery module composed of multiple cells and the negative voltage sampling pin of the front-end analog chip. Since the same cell voltage sampling pin of the front-end analog chip can be connected to two different cells respectively through the main sampling sub-circuit and the branch sampling sub-circuit of the same group, and in cooperation with the sampling control sub-circuit and the reference voltage sampling sub-circuit, the function of voltage sampling of two cells by the same cell voltage sampling pin can be realized, improving the utilization rate of the cell voltage sampling pins in the front-end analog chip. When facing the same number of cell voltage sampling requirements, the usage amount of the front-end analog chip can be reduced, thereby reducing the device power consumption and sampling cost in the cell voltage sampling link. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0028] Figure 1 is one of the schematic structural diagrams of the cell voltage sampling control circuit provided by the embodiment of the present utility model;

[0029] Figure 2 is the second schematic structural diagram of the cell voltage sampling control circuit provided by the embodiment of the present utility model;

[0030] Figure 3 is a schematic diagram showing the change relationship of the working state of the main sampling sub-circuit with time under normal working conditions;

[0031] Figure 4 is a schematic diagram showing the change relationship of the working state of the branch sampling sub-circuit with time under normal working conditions;

[0032] Figure 5 is a schematic diagram showing the change relationship of the working state of the main sampling sub-circuit with time when the main sampling sub-circuit is closed under under-voltage fault;

[0033] Figure 6 is a schematic diagram showing the change relationship of the working state of the branch sampling sub-circuit with time when the main sampling sub-circuit is closed under under-voltage fault;

[0034] Figure 7 It is a schematic diagram showing the variation relationship of the working state of the main sampling sub - circuit with time when the branch sampling sub - circuit is closed under undervoltage fault;

[0035] Figure 8 It is a schematic diagram showing the variation relationship of the working state of the branch sampling sub - circuit with time when the branch sampling sub - circuit is closed under undervoltage fault. Detailed implementation manners

[0036] To make the objectives, technical solutions and advantages of the present utility model clearer, the technical solutions in the present utility model will be clearly and completely described below with reference to the accompanying drawings in the present utility model. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present utility model without making creative efforts fall within the protection scope of the present utility model.

[0037] The following combines Figures 1 to 8 to describe the detailed solutions of the cell voltage sampling control circuit, battery management system and energy storage device provided by the embodiments of the present utility model.

[0038] Figure 1 It is one of the structural schematic diagrams of the cell voltage sampling control circuit provided by the embodiments of the present utility model.

[0039] As Figure 1 shown, the cell voltage sampling control circuit provided by the embodiments of the present utility model can be disposed between the analog front - end chip and multiple cells. Specifically, the circuit includes: a sampling control sub - circuit 11, a reference voltage sampling sub - circuit 12, and at least one group of main sampling sub - circuits 13 and branch sampling sub - circuits 14.

[0040] The input end of the sampling control sub - circuit 11 is respectively connected to the first control pin and the second control pin of the analog front - end chip U1, and the output end of the sampling control sub - circuit 11 is respectively connected to each group of the main sampling sub - circuits 13 and branch sampling sub - circuits 14.

[0041] The main sampling sub - circuit 13 and the branch sampling sub - circuit 14 in the same group are both connected to the same cell voltage sampling pin of the front - end analog chip U1, and the main sampling sub - circuit 13 and the branch sampling sub - circuit 14 are respectively connected to the positive electrodes of different cells.

[0042] The reference voltage sampling sub - circuit 12 is respectively connected to the negative electrode of the battery module composed of multiple cells and the negative voltage sampling pin of the front - end analog chip U1.

[0043] In this embodiment, the same battery cell voltage sampling pin of the front-end analog chip U1 can be connected to two different battery cells respectively through the main sampling sub-circuit 13 and the branch sampling sub-circuit 14 of the same group. The sampling control sub-circuit 11 is used to control the on-off of the main sampling sub-circuit 13 and the branch sampling sub-circuit 14. The reference voltage sampling sub-circuit 12 can collect the negative terminal voltage and use it as a reference voltage, and cooperate with the voltage data collected by the main sampling sub-circuit 13 and the branch sampling sub-circuit 14 to obtain the battery cell voltage of each battery cell.

[0044] In one embodiment, referring to Figure 1 , the sampling control sub-circuit 11 specifically includes: a logic gate module 111 and at least one group of a first switch module 112 and a second switch module 113.

[0045] The first input end of the logic gate module 111 is connected to the first control pin of the analog front-end chip U1, the second input end of the logic gate module 111 is connected to the second control pin of the analog front-end chip U1, the first output end of the logic gate module 111 is respectively connected to at least one first switch module 112, and the second output end of the logic gate module 111 is respectively connected to at least one second switch module 113.

[0046] The first switch module 112 is arranged in the main sampling sub-circuit 13, and the second switch module 113 is arranged in the branch sampling sub-circuit 14.

[0047] In this embodiment, the logic gate module 111 can control the on-off of the main sampling sub-circuit 13 by controlling the on-off of the first switch module 112, and the logic gate module 111 can also control the on-off of the branch sampling sub-circuit 14 by controlling the on-off of the second switch module 113.

[0048] In one embodiment, referring to Figure 2 , the logic gate module 111 specifically includes: a first AND gate Y1, a second AND gate Y2, and a NOT gate F1.

[0049] The first input end of the first AND gate Y1 is connected to the NOT gate F1, the first input ends of the NOT gate F1 and the second AND gate Y2 are both connected to the second control pin GPIO2 of the analog front-end chip U1, the second input ends of the first AND gate Y1 and the second AND gate Y2 are both connected to the first control pin GPIO1 of the analog front-end chip U2, the output end of the first AND gate Y1 is respectively connected to at least one first switch module 112, and the output end of the second AND gate Y2 is respectively connected to at least one second switch module 113.

[0050] As Figure 2 shown, the second input ends of the first AND gate Y1 and the second AND gate Y2 are both connected to the ground terminal through a fifth resistor R5, and the first input end of the second AND gate Y2 is also connected to the ground terminal through a sixth resistor R6.

[0051] In one embodiment, referring to Figure 2 , the first switch module 112 specifically includes: a first MOS transistor K1 and a first auxiliary sub-module.

[0052] The first MOS transistor K1 is disposed in the main sampling sub-circuit. The first MOS transistor K1 is connected to the first auxiliary sub-module, and the first auxiliary sub-module is connected to the first output terminal of the logic gate module 111.

[0053] In this embodiment, the first auxiliary sub-module is composed of a plurality of resistors and a triode. As Figure 2 shown, the first auxiliary sub-module specifically includes: a first auxiliary resistor Ra, a second auxiliary resistor Rb, a third auxiliary resistor Rc, a fourth auxiliary resistor Rd, a fifth auxiliary resistor Re, and a first triode Q1.

[0054] Among them, the first auxiliary resistor Ra, the second auxiliary resistor Rb, and the third auxiliary resistor Rc are all connected to the first MOS transistor K1. The third auxiliary resistor Rc, the fourth auxiliary resistor Rd, and the fifth auxiliary resistor Re are all connected to the first triode Q1. The fourth auxiliary resistor Rd is also connected to the first output terminal of the logic gate module 111.

[0055] In one embodiment, referring to Figure 2 , the second switch module 113 specifically includes: a second MOS transistor K2 and a second auxiliary sub-module.

[0056] The second MOS transistor K2 is disposed in the branch sampling sub-circuit. The second MOS transistor K2 is connected to the second auxiliary sub-module, and the second auxiliary sub-module is connected to the second output terminal of the logic gate module 111.

[0057] In this embodiment, the second auxiliary sub-module has the same structure as the first auxiliary sub-module and is also composed of a plurality of resistors and a triode. As Figure 2 shown, the second auxiliary sub-module specifically includes: a sixth auxiliary resistor Rf, a seventh auxiliary resistor Rg, an eighth auxiliary resistor Rh, a ninth auxiliary resistor Ri, a tenth auxiliary resistor Rj, and a second triode Q2.

[0058] Among them, the sixth auxiliary resistor Rf, the seventh auxiliary resistor Rg, and the eighth auxiliary resistor Rh are all connected to the second MOS transistor K2. The eighth auxiliary resistor Rh, the ninth auxiliary resistor Ri, and the tenth auxiliary resistor Rj are all connected to the second triode Q2. The eighth auxiliary resistor Rh is also connected to the second output terminal of the logic gate module 111.

[0059] In one embodiment, referring to Figure 2 , the main sampling sub-circuit specifically includes: a first bead Z1, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2.

[0060] The first magnetic bead Z1 is respectively connected to the positive electrode of the corresponding battery cell and the first switch module 112. The first resistor R1 is respectively connected to the first switch module 112 and the second resistor R2. The second resistor R2 is connected to the battery cell voltage sampling pin CT ( Figure 2 in it is CTn / 2 + 2) of the front-end analog chip U1. The first capacitor C1 is connected to the line between the first resistor R1 and the first switch module 112. The second capacitor C2 is connected to the line between the first resistor R1 and the second resistor R2. Both the first capacitor C1 and the second capacitor C2 are grounded.

[0061] In one embodiment, referring to Figure 2 , the branch sampling sub-circuit 14 specifically includes: at least one second magnetic bead Z2.

[0062] The second magnetic bead Z2 is respectively connected to the positive electrode of the corresponding battery cell and the second switch module 113. The second switch module 113 is connected to the line between the first resistor R1 and the first switch module 112.

[0063] In practical applications, the main sampling sub-circuit and the branch sampling sub-circuit of the same group work alternately, that is, when the main sampling sub-circuit of the same group is turned on, the branch sampling sub-circuit is turned off, and when the branch sampling sub-circuit is turned on, the main sampling sub-circuit is turned off.

[0064] In one embodiment, referring to Figure 2 , the reference voltage sampling sub-circuit 12 specifically includes: a third magnetic bead Z3, a third resistor R3, a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4.

[0065] The third magnetic bead Z3 is respectively connected to the negative electrode of the battery module composed of multiple battery cells and the third resistor R3. The third resistor R3 is connected to the fourth resistor R4. The fourth resistor R4 is connected to the negative electrode voltage sampling pin CT0 of the front-end analog chip U1. The third capacitor C3 is connected to the line between the third magnetic bead Z3 and the third resistor R3. The fourth capacitor C4 is connected to the line between the third resistor R3 and the fourth resistor R4. Both the third capacitor C3 and the fourth capacitor C4 are grounded.

[0066] It can be understood that since the battery module can include multiple battery cells, Figure 2The battery module shown involves multiple cells, and the multiple cells are connected in series. There are n / 2 + 2 cell voltage sampling pins provided on the analog front-end chip U1. Each cell voltage sampling pin is connected to two adjacent cells through its respective main sampling sub-circuit and branch sampling sub-circuit. Since the structures of the main sampling sub-circuit, branch sampling sub-circuit, first switch module, and second switch module corresponding to each cell voltage sampling pin are the same, therefore, in this embodiment, only the circuit structure corresponding to the cell voltage sampling pin CTn / 2 + 2 is described. The circuit structures connected to other cell voltage sampling pins are the same as the circuit structure connected to the cell voltage sampling pin CTn / 2 + 2, and will not be repeated here.

[0067] Since the front-end analog chip U1 also involves VPWER pin, NPNB pin, LDO-IN pin, VSS pin, AVDD pin, REF-VSS pin, REF-CAP pin, and DVDD-CAP pin, there are corresponding peripheral circuits for the above pins.

[0068] Specifically, as Figure 2 shown, the VPWER pin is connected to the first peripheral branch composed of the fourth bead Z4, diode D1, fifth capacitor C5, sixth capacitor C6, and seventh resistor R7, and the fourth bead Z4 is also connected to the positive terminal of the battery module composed of multiple cells.

[0069] The LDO-IN pin is connected to the second peripheral branch composed of the eighth resistor R8, seventh capacitor C7, third triode Q3, and eighth capacitor C8, and the third triode Q3 is also connected to the NPNB pin.

[0070] The VSS pin, AVDD pin, REF-VSS pin, REF-CAP pin, and DVDD-CAP pin are all connected to the ground terminal. Among them, the AVDD pin is grounded through the ninth capacitor C9, the REF-CAP pin is grounded through the tenth capacitor C10, and the DVDD-CAP pin is grounded through the eleventh capacitor C11. At the same time, the negative terminal of the entire battery module is also connected to the GND1 pin of the analog front-end chip and grounded through the GND1 pin.

[0071] Combined with Figure 2 shown, taking the cell voltage sampling of the first four cells cell1, cell2, cell3, and cell4 as an example, the working principle of the cell voltage sampling control circuit provided in this embodiment is described as follows:

[0072] In this case, the cell voltage sampling pins of the analog front-end chip U1 are CT1 and CT2 respectively, and the negative voltage sampling pin is CT0. The collected voltages are represented by u0, u1, and u2 respectively. Since the reference voltage sampling sub-circuit 12 connected to the CT0 pin is not connected to the sampling control sub-circuit 11, the negative terminal voltage of the cell cell1 can be directly measured and used as the reference voltage, denoted as u0.

[0073] During the sampling process, the first control pin GPIO1 defaults to sending a high-level signal, and the second control pin GPIO2 defaults to sending a low-level signal. After being processed by the logic gate module 111, the first MOS transistor K1 closes and the second MOS transistor K2 opens, realizing that the main sampling sub-circuit is normally closed and the branch sampling sub-circuit is normally open. At this time, the voltage values collected by the CT1 pin and the CT2 pin are the positive terminal voltages of the cell cell2 and the cell cell4 respectively, denoted as u1 and u2. Then the difference between u1 and u0 is the sum of the voltages of the cell cell1 and cell2, and the difference between u2 and u1 is the sum of the voltages of the cell cell3 and cell4, denoted as U1 and U2 respectively.

[0074] Subsequently, the first control pin GPIO1 continuously sends a high-level signal. When the second control pin GPIO2 sends a high-level signal, after passing through the logic gate module 111, the first MOS transistor K1 opens. At this time, the main sampling sub-circuit is open, and at the same time the second MOS transistor K2 closes and the branch sampling sub-circuit is connected. At this time, the voltage values u1' and u2' collected by the CT1 pin and the CT2 pin are the positive terminal voltages of the cell cell1 and the cell cell3 respectively.

[0075] Since the circuit sends high and low level signals and the operation of the MOS transistors are all in milliseconds, it can be considered that the switching between the main sampling sub-circuit and the branch sampling sub-circuit is an instantaneous process. By default, the voltage values u1 and u2 do not change before and after the switching. Then the difference between u1 and u1' is the cell voltage of the cell cell2, and the difference between u2 and u2' is the cell voltage of the cell cell4, thus obtaining the cell voltages of the even-numbered cells. Then the cell voltages of the odd-numbered cells can be obtained by subtracting the cell voltages of the even-numbered cells from the total voltage of two cells.

[0076] It should be noted that since the negative terminal of the cell cell1 is the reference point, the cell voltage of the cell cell1 can be directly obtained from the difference between u1' and u0.

[0077] In practical applications, the main sampling sub-circuit and the branch sampling sub-circuit switch periodically. The switching period, that is, the time from when the main sampling sub-circuit closes to when the main sampling sub-circuit closes again, can be set to 500 ms. During this process, the working states of the main sampling sub-circuit and the branch sampling sub-circuit change with time T as followsFigure 3 and Figure 4 As shown in Figure 4 , on the vertical axis, 1 represents the circuit being closed, and 0 represents the circuit being open. Taking a voltage sampling period of 10 ms as an example, the control logic during the entire signal transmission process is as follows:

[0078] After starting to work, the first control pin GPIO1 continuously sends a high-level signal by default, and the second control pin GPIO2 sends a low-level signal by default.

[0079] After working for 450 ms, the second control pin GPIO2 sends a high-level signal and resumes after 50 ms. During this period, the branch sampling sub-circuit is closed and at least 3 cycles of voltage sampling are completed.

[0080] When the second control pin GPIO2 sends a high-level signal, voltage values such as u1 and u2 are locked and calculated with u1' and u2' to obtain the cell voltage of the even-numbered cells, and finally the cell voltage of each cell can be obtained.

[0081] In some embodiments, the above cell voltage sampling control circuit can also implement the cell fault diagnosis function. The fault diagnosis mainly targets over-voltage and under-voltage faults. In practical applications, two types of thresholds need to be set for cell over-voltage and under-voltage, namely the over-voltage and under-voltage thresholds for a single cell and the over-voltage and under-voltage thresholds for two cells. The over-voltage and under-voltage thresholds for two cells can be directly set to twice the over-voltage and under-voltage thresholds for a single cell. Taking the under-voltage fault as an example, the under-voltage threshold for a single cell is θ, and the under-voltage threshold for two cells is 2θ.

[0082] When the main sampling sub-circuit is closed, U1 and U2 are respectively compared with the under-voltage threshold 2θ for two cells. When a certain group of voltage values is less than 2θ, the fault diagnosis mechanism is triggered. At this time, the second control pin GPIO2 will send high-level and low-level signals at an interval of 10 ms. At this time, each cell voltage will be continuously sent at a period of 10 ms and compared with the under-voltage threshold θ for a single cell; if it meets the condition that the single cell voltage is less than the under-voltage threshold θ for a continuous preset duration, such as continuously for 4 s, an under-voltage fault will be reported and the operation will continue at a period of 10 ms until the fault is cleared. During the whole process, the working states of the main sampling sub-circuit and the branch sampling sub-circuit with respect to the change of time T are respectively as shown in Figure 5 and Figure 6 shown.

[0083] When the branch sampling sub - circuit is closed, the voltage of a single battery cell is directly compared with the undervoltage threshold θ of the single battery cell. If it is less than θ, the fault diagnosis mechanism is triggered, and the second control pin GPIO2 sends high - level and low - level signals at an interval of 10 ms. If the single - cell voltage is less than θ for a continuous preset duration, such as 4 s continuously, an undervoltage fault is reported, and it continues to work at a period of 10 ms until the fault is cleared. During the whole process, the working states of the main sampling sub - circuit and the branch sampling sub - circuit with respect to the change of time T are respectively as Figure 7 and Figure 8 shown.

[0084] In summary, the battery cell voltage sampling control circuit provided by the embodiment of the present invention can realize the function of sampling the voltages of two battery cells on the same battery cell voltage sampling pin of the analog front - end chip, improve the utilization rate of the battery cell voltage sampling pins in the front - end analog chip, reduce the usage amount of the front - end analog chips when facing the same number of battery cells, and thus reduce the device power consumption and sampling cost in the battery cell voltage sampling link.

[0085] In addition, the embodiment of the present invention also provides a battery management system, including the battery cell voltage sampling control circuit provided by each of the above - mentioned embodiments.

[0086] Furthermore, the embodiment of the present invention also provides an energy storage device, including the battery cell voltage sampling control circuit provided by each of the above - mentioned embodiments or the above - mentioned battery management system.

[0087] It can be understood that the energy storage device can be a vehicle, a working machine, etc.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cell voltage sampling control circuit, characterized in that: The circuit is arranged between the analog front-end chip and a plurality of battery cells, and includes: a sampling control subcircuit, a reference voltage sampling subcircuit, and at least one group of main sampling subcircuit and branch sampling subcircuit; The input end of the sampling control subcircuit is respectively connected to the first control pin and the second control pin of the analog front-end chip, and the output end of the sampling control subcircuit is respectively connected to the main sampling subcircuit and the branch sampling subcircuit of each group; The main sampling subcircuit and the branch sampling subcircuit of the same group are both connected to the same cell voltage sampling pin of the analog front-end chip, and the main sampling subcircuit and the branch sampling subcircuit are respectively connected to the positive terminals of different cells; The reference voltage sampling subcircuit is respectively connected to the negative terminal of the battery module composed of the multiple battery cells and the negative electrode voltage sampling pin of the analog front-end chip.

2. The cell voltage sampling control circuit according to claim 1, characterized in that: The sampling control subcircuit comprises: a logic gate module and at least one group of first switch modules and second switch modules; The first input end of the logic gate module is connected to the first control pin of the analog front-end chip, the second input end of the logic gate module is connected to the second control pin of the analog front-end chip, the first output end of the logic gate module is respectively connected to at least one of the first switch modules, and the second output end of the logic gate module is respectively connected to at least one of the second switch modules; The first switch module is disposed in the main sampling sub-circuit, and the second switch module is disposed in the branch sampling sub-circuit.

3. The cell voltage sampling control circuit according to claim 2, characterized in that: The logic gate module includes: a first AND gate, a second AND gate and a NOT gate; The first input end of the first AND gate is connected to the NOT gate, the first input ends of the NOT gate and the second AND gate are both connected to the second control pin of the analog front-end chip, the second input end of the first AND gate and the second input end of the second AND gate are both connected to the first control pin of the analog front-end chip, the output end of the first AND gate is respectively connected to at least one of the first switch modules, and the output end of the second AND gate is respectively connected to at least one of the second switch modules.

4. The cell voltage sampling control circuit according to claim 2, characterized in that: The first switch module includes: a first MOS tube and a first auxiliary submodule; The first MOS transistor is arranged in the main sampling sub-circuit, the first MOS transistor is connected to the first auxiliary sub-module, and the first auxiliary sub-module is connected to the first output end of the logic gate module.

5. The cell voltage sampling control circuit according to claim 2, characterized in that: The second switch module includes: a second MOS tube and a second auxiliary submodule; The second MOS transistor is arranged in the branch sampling sub-circuit, the second MOS transistor is connected to the second auxiliary sub-module, and the second auxiliary sub-module is connected to the second output end of the logic gate module.

6. The cell voltage sampling control circuit according to claim 2, characterized in that: The main sampling subcircuit comprises: a first magnetic bead, a first resistor, a second resistor, a first capacitor and a second capacitor; The first magnetic bead is respectively connected to the positive electrode of the corresponding battery cell and the first switch module, the first resistor is respectively connected to the first switch module and the second resistor, the second resistor is connected to the battery cell voltage sampling pin of the analog front-end chip, the first capacitor is connected to the line between the first resistor and the first switch module, the second capacitor is connected to the line between the first resistor and the second resistor, and the first capacitor and the second capacitor are both grounded.

7. The cell voltage sampling control circuit according to claim 6, characterized in that: The branch sampling subcircuit includes: at least one second magnetic bead; The second magnetic bead is respectively connected to the positive electrode of the corresponding battery cell and the second switch module, and the second switch module is connected to the line between the first resistor and the first switch module.

8. The cell voltage sampling control circuit according to claim 1, characterized in that: The reference voltage sampling subcircuit comprises: a third magnetic bead, a third resistor, a fourth resistor, a third capacitor and a fourth capacitor; The third magnetic bead is respectively connected to the negative terminal of the battery module composed of the multiple battery cells and the third resistor, the third resistor is connected to the fourth resistor, the fourth resistor is connected to the negative voltage sampling pin of the analog front-end chip, the third capacitor is connected to the line between the third magnetic bead and the third resistor, the fourth capacitor is connected to the line between the third resistor and the fourth resistor, and the third capacitor and the fourth capacitor are both grounded.

9. A battery management system, characterized in that: Comprising the cell voltage sampling control circuit as described in any one of claims 1 to 8.

10. An energy storage device, characterized in that: It comprises the cell voltage sampling control circuit as described in any one of claims 1 to 8 or the battery management system as described in claim 9.

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