Fingerprint sensor and display device including same

Abstract

The utility model relates to a fingerprint sensor and a display device. The fingerprint sensor includes: a readout line disposed on a substrate and extending in a first direction; a light receiving element disposed on the readout line; a first sensor transistor that controls a sensing current based on a voltage of a sensor node that is a first electrode of the light receiving element; a second sensor transistor providing a reset voltage to the sensor node based on the reset signal; and a third sensor transistor electrically connecting the first electrode of the first sensor transistor with the readout line based on the gate signal. The fingerprint sensor also includes a power line disposed in a layer between the second sensor transistor and the readout line and extending in the first direction. The power line overlaps the read-out line.

Description

Technical Field

[0001] The present disclosure relates to a fingerprint sensor and a display device including the fingerprint sensor. Background Art

[0002] Many forms of electronic devices have a display device. Examples include smart phones, digital cameras, laptop computers, navigators, and smart TVs. Some display devices have pixels with self-luminous elements that display an image without a backlight unit. Some display devices also include an optical sensor for sensing light and a fingerprint sensor for sensing a fingerprint. Attempts have been made to improve display devices, but these attempts have drawbacks. Summary of the Utility Model

[0003] According to an embodiment, the fingerprint sensor includes: a readout line disposed on a substrate and extending in a first direction; a light receiving element disposed on the readout line; a first sensor transistor configured to control a sensing current based on a voltage of a sensor node that is a first electrode of the light receiving element; a second sensor transistor configured to provide a reset voltage to the sensor node based on a reset signal; a third sensor transistor that electrically connects a first electrode of the first sensor transistor to the readout line based on a gate signal; and a power line disposed in a layer between the second sensor transistor and the readout line and extending in the first direction, the power line overlapping the readout line.

[0004] The power line may be a DC power line, and the DC power line includes a reset voltage line that provides a reset voltage or a low potential line that is connected to a second electrode of the light receiving element to provide a low potential voltage.

[0005] A semiconductor region of each of the first sensor transistor and the third sensor transistor may include a silicon-based material, and a semiconductor region of the second sensor transistor may include an oxide-based material.

[0006] The third sensor transistor may include a third-first sensor transistor and a third-second sensor transistor connected in series between a first electrode of the first sensor transistor and the readout line.

[0007] The fingerprint sensor may further include: a first active layer disposed on the substrate; a first gate layer disposed on the first active layer; a second gate layer disposed on the first gate layer; a second active layer disposed on the second gate layer; a third gate layer disposed on the second active layer; a first source metal layer disposed on the third gate layer; a second source metal layer disposed on the first source metal layer, the second source metal layer including the power line; and a third source metal layer disposed on the second source metal layer, the third source metal layer including the readout line.

[0008] The fingerprint sensor may further include a readout electrode disposed in the first source metal layer to electrically connect the readout line to the third sensor transistor.

[0009] The fingerprint sensor may further include: a sensor node electrode disposed in the second source metal layer and corresponding to the sensor node; and a sensor connection electrode disposed in the first source metal layer, the sensor connection electrode electrically connecting the gate electrode of the first sensor transistor to the sensor node electrode.

[0010] The fingerprint sensor may further include a reset voltage line, which includes: a first portion disposed in the second source metal layer and extending in a first direction; a second portion disposed in the first source metal layer and connected to the first portion and extending in a second direction intersecting the first direction; and a third portion disposed in the second source metal layer and electrically connected between the second portion and the first electrode of the second sensor transistor.

[0011] The third portion of the reset voltage line may overlap with the semiconductor region of the second sensor transistor.

[0012] The semiconductor region of the first sensor transistor may be disposed in the first active layer, and the semiconductor region of the second sensor transistor may be disposed in the second active layer.

[0013] The fingerprint sensor may further include: a gate line disposed in the first gate layer to provide a gate signal; and a reset signal line disposed in the third gate layer to provide a reset signal.

[0014] According to an embodiment, the fingerprint sensor includes: a light receiving element disposed on a substrate; a first sensor transistor configured to control a sensing current based on a voltage of a sensor node that is a first electrode of the light receiving element; a second sensor transistor configured to provide a reset voltage to the sensor node based on a reset signal; a third sensor transistor that electrically connects the first electrode of the first sensor transistor to the readout line based on a gate signal; a first active layer disposed on the substrate, the first active layer including a semiconductor region of the first sensor transistor; a first gate layer disposed on the first active layer, the first gate layer including a gate electrode of the first sensor transistor; a second gate layer disposed on the first gate layer; a second active layer disposed on the second gate layer, the second active layer including a semiconductor region of the second sensor transistor; a third gate layer disposed on the second active layer, the third gate layer including a gate electrode of the second sensor transistor; a first source metal layer disposed on the third gate layer; a second source metal layer disposed on the first source metal layer, the second source metal layer including a power line; and a third source metal layer disposed on the second source metal layer, the third source metal layer including a readout line overlapping with the power line.

[0015] The power line can be a DC power line, and the DC power line includes a reset voltage line configured to provide a reset voltage or a low potential line connected to the second electrode of the light receiving element to provide a low potential voltage.

[0016] The semiconductor region of each of the first sensor transistor and the third sensor transistor may include a silicon-based material, and the semiconductor region of the second sensor transistor may include an oxide-based material.

[0017] The third sensor transistor may include a third-first sensor transistor and a third-second sensor transistor connected in series between the first electrode of the first sensor transistor and the readout line.

[0018] The fingerprint sensor may further include a readout electrode disposed in the first source metal layer to electrically connect the readout line and the third sensor transistor.

[0019] The fingerprint sensor may further include: a sensor node electrode disposed in the second source metal layer and corresponding to the sensor node; and a sensor connection electrode disposed in the first source metal layer, the sensor connection electrode electrically connecting the gate electrode of the first sensor transistor and the sensor node electrode.

[0020] According to an embodiment, a display device includes: a fingerprint sensor including a readout line and a light receiving element, the readout line being disposed on a substrate and extending in a first direction, and the light receiving element being disposed on the readout line; and a pixel including a light emitting element, the light emitting element being disposed in the same layer as the light receiving element. The fingerprint sensor further includes: a first sensor transistor configured to control a sensing current based on the voltage of a sensor node that is the first electrode of the light receiving element; a second sensor transistor configured to provide a reset voltage to the sensor node based on a reset signal; a third sensor transistor that electrically connects the first electrode of the first sensor transistor and the readout line based on a gate signal; and a power line disposed in a layer between the second sensor transistor and the readout line and extending in the first direction, the power line overlapping the readout line.

[0021] The display device may further include: a first active layer disposed on the substrate; a first gate layer disposed on the first active layer; a second gate layer disposed on the first gate layer; a second active layer disposed on the second gate layer; a third gate layer disposed on the second active layer; a first source metal layer disposed on the third gate layer; a second source metal layer disposed on the first source metal layer, the second source metal layer including the power line; and a third source metal layer disposed on the second source metal layer, the third source metal layer including the readout line.

[0022] The display device may further include a data line disposed in the second source metal layer and extending in the first direction, the data line supplying a data voltage to the pixel.

[0023] In a fingerprint sensor and a display device including the fingerprint sensor according to an embodiment, the display device may include a low potential line or a reset voltage line, which is disposed below a readout line to overlap with the readout line to avoid connection between a data line and the readout line, thereby improving sensitivity.

[0024] According to one or more embodiments, the fingerprint sensor includes: a readout line; a light receiving element; a reset signal line for resetting a sensor node; and a power line that overlaps with the readout line to shield the readout line from at least one signal line of a pixel disposed adjacent to the fingerprint sensor. The at least one signal line may be a data line of the pixel. The reset signal line may be connected to a reset transistor, and the power line may be disposed in a layer between the reset transistor and the readout line. The power line may be a low potential power line connected to a light receiving element of the pixel and a light emitting element. The power line may be a part of a reset power line connected to a transistor connected to the reset signal line.

[0025] The effects according to embodiments of the present disclosure are not limited to those mentioned above, and more various effects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of the present disclosure will become more apparent by referring to the accompanying drawings in which exemplary embodiments of the present disclosure are described in detail, in the drawings:

[0027] Figure 1 is a perspective view showing a display device according to an embodiment;

[0028] Figure 2 is a cross-sectional view showing a display device according to an embodiment;

[0029] Figure 3 is a plan view showing a display unit of a display device according to an embodiment;

[0030] Figure 4 is a block diagram showing a display panel and a display driver according to an embodiment;

[0031] Figure 5 is a plan view showing a light emitting area and a sensor area of a display device according to an embodiment;

[0032] Figure 6 is a circuit diagram showing a pixel of a display device according to an embodiment;

[0033] Figure 7 is a cross-sectional view showing a pixel of a display device according to an embodiment;

[0034] Figure 8 is a circuit diagram showing a fingerprint sensor of a display device according to an embodiment;

[0035] Figure 9 is a layout diagram showing a fingerprint sensor of a display device according to an embodiment;

[0036] Figure 10 is a cross-sectional view taken along line I-I' according to an embodiment; and Figure 9 of; and

[0037] Figure 11 is a cross-sectional view taken along line II-II' according to an embodiment. Figure 9 of DETAILED DESCRIPTION

[0038] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of a device or method that employs one or more of the disclosures disclosed herein. However, it will be apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Further, the various embodiments may be different, but need not be exclusive or limiting of the present disclosure. For example, without departing from the present disclosure, the specific shapes, configurations, and characteristics of the embodiments may be used or implemented in other embodiments.

[0039] Unless otherwise stated, the illustrated embodiments are to be understood as providing features that may vary in detail some ways of implementing the present disclosure in practice. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and / or rearranged without departing from the present disclosure.

[0040] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for a particular material, material property, dimension, scale, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the element.

[0041] In addition, in the accompanying drawings, for clarity and / or description purposes, the dimensions and relative dimensions of elements may be exaggerated. When an embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Additionally, the same reference numerals denote the same elements.

[0042] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being directly "on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. For this reason, the term "connected" can refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0043] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and thus, the X-axis, Y-axis, and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0044] For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of this disclosure, the first element discussed below can be referred to as the second element.

[0046] For descriptive purposes, spatial relative terms, such as "below", "beneath", "under", "lower", "above", "upper", "on top of", "higher", "side" (e.g., as in "sidewall"), etc., may be used herein and thereby describe the relationship of one element to another (or elements) as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an orientation above and below. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatial relative descriptors used herein should be interpreted accordingly.

[0047] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, when used in this specification, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to account for inherent variations in measured, calculated, and / or provided values that would be recognized by one of ordinary skill in the art.

[0048] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. Accordingly, variations in the shapes of the figures due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the particular shapes shown in the figures, but should include deviations in shapes, for example, resulting from manufacturing. In this manner, the regions shown in the figures are schematic in nature, and the shapes of these regions may not reflect the actual shape of the regions of the device, and are thus not necessarily intended to be limiting.

[0049] As is customary in the art, some embodiments are described and illustrated in the drawings for functional blocks, units, parts, and / or modules. Those skilled in the art will understand that these blocks, units, parts, and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connectors, etc., which can be formed by semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where the blocks, units, parts, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled by software (e.g., microcode) to perform the various functions discussed herein, and optionally driven by firmware and / or software. It is also contemplated that each block, unit, part, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Additionally, without departing from the scope of the present disclosure, each block, unit, part, and / or module in some embodiments can be physically separated into two or more interacting and discrete blocks, units, parts, and / or modules. Additionally, without departing from the scope of the present disclosure, the blocks, units, parts, and / or modules in some embodiments can be physically combined into more complex blocks, units, parts, and / or modules.

[0050] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Hereinafter, detailed embodiments of the present disclosure will be described with reference to the drawings.

[0052] Figure 1 is a perspective view showing a display device 10 according to an embodiment. The display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic diaries, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs). The display device 10 can also be applied to televisions, laptop computers, monitors, signboards, or the display units of Internet of Things (IoT) devices. The display device 10 can also be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0053] The display device 10 can be formed to have a planar shape such as a rectangular shape. For example, the display device 10 can have a planar shape similar to a rectangular shape, which has a short side in the X-axis direction and a long side in the Y-axis direction. The corners where the short side in the X-axis direction and the long side in the Y-axis direction intersect can be rounded to have a predetermined curvature, or in other cases, the corners can be formed as right angles. In some embodiments, the planar shape of the display device 10 can have other polygonal shapes, circular shapes, or elliptical shapes.

[0054] Reference Figure 1 , the display device 10 can include a display panel 100, a display driver 200, a circuit board 300, a touch driver 400, and a power supply unit 500.

[0055] The display panel 100 can include a main area MA and a sub-area SBA. The main area MA can include a display area DA having pixels for displaying an image and a non-display area NDA provided near (or adjacent to) the display area DA. The display area DA can include pixels that emit light from a plurality of emission areas or a plurality of opening areas. For example, each pixel of the display panel 100 can include a pixel circuit having a switching element, a pixel defining layer that defines an emission area or an opening area, and a self-luminous element. For example, the self-luminous element can include at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode (micro LED), but is not limited thereto.

[0056] The non-display area NDA can be an external area of the display area DA. The non-display area NDA can be an edge area of the main area MA of the display panel 100. The non-display area NDA can include a gate driver for supplying a gate signal to a gate line and a fan-out line that connects the display driver 200 to the display area DA.

[0057] The sub-area SBA can extend from one side of the main area MA. The sub-area SBA can include a flexible material that can be bent, folded, curled, etc. For example, when the sub-area SBA is bent, the sub-area SBA can overlap with the main area MA in the thickness direction (Z-axis direction). The sub-area SBA can include the display driver 200 and a pad portion connected to the circuit board 300. Optionally, the sub-area SBA can be omitted, and the display driver 200 and the pad portion can be provided in the non-display area NDA.

[0058] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to data lines. The display driver 200 can supply power voltages to power lines and supply gate control signals to the gate driver. The display driver 200 can receive sensing signals through sense lines. The display driver 200 can be formed of an integrated circuit (IC) and can be packaged on the display panel 100 in any one of a variety of methods, including the chip on glass (COG) method, the chip on plastic (COP) method, and the ultrasonic bonding method. For example, the display driver 200 can be disposed in the sub-region SBA and can overlap with the main region MA in the thickness direction (Z-axis direction) by bending the sub-region SBA. For another example, the display driver 200 can be packaged on the circuit board 300.

[0059] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0060] The touch driver 400 can be packaged on the circuit board 300. The touch driver 400 can be connected to the touch sensing unit of the display panel 100. The touch driver 400 can supply touch drive signals to a plurality of touch electrodes of the touch sensing unit and can sense a change amount of capacitance between the plurality of touch electrodes. For example, the touch drive signal can be a pulse signal having a predetermined frequency. The touch driver 400 can calculate an input and input coordinates based on the change amount of capacitance between the plurality of touch electrodes, for example, to perform an operation corresponding to the input and input coordinates. The touch driver 400 can be formed of an integrated circuit (IC).

[0061] The power supply unit 500 can be disposed on the circuit board 300 to supply power voltages to the display driver 200 and the display panel 100. For example, the power supply unit 500 can generate a drive voltage to supply the drive voltage to the drive voltage line and supply a common voltage to a common electrode commonly provided for a plurality of light emitting elements. For example, the drive voltage can be a high potential voltage for driving the light emitting elements, and the common voltage can be a low potential voltage for driving the light emitting elements. The power supply unit 500 can generate an initialization voltage to be supplied to the initialization voltage line, generate a reference voltage to be supplied to the reference voltage line, generate a bias voltage to be supplied to the bias voltage line, and generate a reset voltage to be supplied to the reset voltage line.

[0062] Figure 2 is a cross-sectional view showing the display device 10 in a folded state according to an embodiment of the present disclosure.

[0063] Reference Figure 2 As shown in

[0063] , the display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a transistor layer TFTL, a light emitting element layer EDL, and a packaging layer TFEL. These layers may be arranged in the above order, or in another embodiment, one or more layers may be arranged in a different order.

[0064] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate capable of being bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0065] The transistor layer TFTL may be disposed on the substrate SUB. The transistor layer TFTL may include a plurality of thin film transistors to be included in pixels and fingerprint sensors. The transistor layer TFTL may further include gate lines, data lines, power lines, readout lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include transistors.

[0066] The transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines, power lines, and readout lines of the transistor layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the transistor layer TFTL may be disposed in the non-display area NDA. The leads of the transistor layer TFTL may be disposed in the sub-area SBA.

[0067] The light emitting element layer EDL may be disposed on the transistor layer TFTL. The light emitting element layer EDL may include light emitting elements of pixels, light receiving elements of fingerprint sensors, and pixel defining layers for pixels and fingerprint sensors. The light emitting elements may include a pixel electrode, a light emitting layer, and a common electrode stacked in sequence to emit light. The light receiving elements may include a sensor electrode, a light receiving layer, and a common electrode stacked in sequence to receive light. The light emitting elements and light receiving elements of the light emitting element layer EDL may be disposed in the display area DA.

[0068] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the transistor of the transistor layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer and electrons may move to the organic light-emitting layer through the electron transport layer. The holes and electrons may recombine in the organic light-emitting layer to cause light emission. For example, the pixel electrode may be an anode electrode and the common electrode may be a cathode electrode, but they are not limited thereto. In another example, the plurality of light-emitting elements may include quantum dot light-emitting diodes including quantum dot light-emitting layers, inorganic light-emitting diodes including inorganic semiconductors, or micro light-emitting diodes.

[0069] The light-receiving element may receive light and convert the light energy into an electrical signal. When the user's finger touches the display panel 100, the light emitted from the light-emitting element may be reflected by the finger, and the light-receiving element may receive the reflected light. The fingerprint of the finger has ridges and valleys that differently affect the reflected light. The sensing signal of the fingerprint sensor that receives the light reflected by the ridge of the finger may be different from the sensing signal of the fingerprint sensor that receives the light reflected by the valley of the finger. The processor may generate sensing data by distinguishing the differences between the sensing signals, and may determine whether the ridge or valley of the finger has touched the display panel 100 based on the sensing data. Therefore, the display device 10 may identify the pattern of the user's fingerprint based on the sensing data. For example, the light-receiving element may be an organic photodiode, but it is not limited thereto.

[0070] The encapsulation layer TFEL may cover the upper surface and the side surfaces of the light-emitting element layer EDL, and may protect the light-emitting element layer EDL. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer designed to encapsulate the light-emitting element layer EDL.

[0071] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes that sense the user's touch based on a change in capacitance and touch lines that connect the plurality of touch electrodes to the touch driver 400. The plurality of touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping the non-display area NDA. For example, the touch sensing unit TSU may sense the user's touch in a mutual capacitance manner or a self-capacitance manner.

[0072] In another example, the touch sensing unit TSU may be disposed on a separate substrate disposed on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a basic member for encapsulating the display unit DU.

[0073] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters respectively corresponding to a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength and may block or absorb light of one or more other wavelengths. The color filter layer CFL may absorb a part of the light incident from the outside of the display device 10 to reduce the reflected light caused by the external light. Accordingly, the color filter layer CFL may prevent color distortion caused by the occurrence of external light reflection.

[0074] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Accordingly, the thickness of the display device 10 may be significantly reduced.

[0075] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material capable of withstanding bending, folding, curling, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction (Z-axis direction). The sub-region SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0076] Figure 3 is a plan view showing a display unit DU of a display device according to an embodiment, and Figure 4 is a block diagram showing a display panel and a display driver according to an embodiment.

[0077] Reference Figure 3 and Figure 4 , the display unit DU includes a display panel 100, and the display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include a plurality of pixels SP, a fingerprint sensor OPD, a power line VL, a data line DL, a readout line ROL, a gate line GL, and an emission control line EML. The pixel SP is shown as a representative sample of the pixels of the display panel 100.

[0078] Each of the plurality of pixels SP may be connected to the gate line GL, the emission control line EML, the data line DL, and the power line VL. Each of the plurality of pixels SP may include at least one transistor, a light emitting element, and a capacitor.

[0079] Each of the plurality of fingerprint sensors OPD may be connected to the gate line GL, the power line VL, and the readout line ROL. Each of the plurality of fingerprint sensors OPD may include at least one transistor and a light receiving element.

[0080] The gate lines GL can extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction that intersects the X-axis direction. The gate lines GL can sequentially supply gate signals to the pixels SP and the fingerprint sensor OPD.

[0081] The emission control lines EML can also extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction. The emission control lines EML can sequentially supply emission signals to the pixels SP.

[0082] The data lines DL can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction. The data lines DL can supply data voltages to corresponding pixels in the pixels SP. The data voltages can determine the brightness of light emitted from the corresponding pixels in the pixels SP.

[0083] The power lines VL can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction. The power lines VL can supply power voltages to the pixels SP and the fingerprint sensor OPD. The power voltages can be predetermined voltages such as a driving voltage, a common voltage, an initialization voltage, a reference voltage, a bias voltage, or a reset voltage. The driving voltage can be a high-potential voltage for driving a light-emitting element, and the common voltage can be a low-potential voltage for driving a light-emitting element and a light-receiving element.

[0084] The non-display area NDA can surround the display area DA. The non-display area NDA can include a gate driver 610, an emission control driver 620, fan-out lines FL, a first gate control line GSL1, and a second gate control line GSL2. The fan-out lines FL can extend from the display driver 200 to the display area DA. The fan-out lines FL can supply the data voltages received from the display driver 200 to the data lines DL, supply the power voltages received from the display driver 200 to the power lines VL, and supply the sensing signals received from the readout lines ROL to the display driver 200. Accordingly, the display driver 200 can drive the pixels SP and the fingerprint sensor OPD.

[0085] The first gate control line GSL1 can extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 can supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0086] The second gate control line GSL2 can extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 can supply the emission control signal ECS received from the display driver 200 to the emission control driver 620.

[0087] The sub-region SBA can extend from one side of the non-display region NDA. The sub-region SBA can include a display driver 200 and a pad portion DP. The pad portion DP can be arranged closer to the edge of one side of the sub-region SBA than the display driver 200. The pad portion DP can be electrically connected to the circuit board 300, for example, through an anisotropic conductive film (ACF).

[0088] Reference Figure 3 and Figure 4 , the display driver 200 can include a timing controller 210 and a data driver 220. The timing controller 210 can receive digital video data DATA and timing signals from the circuit board 300. The timing controller 210 can generate a data control signal DCS based on the timing signals to control the operation timing of the data driver 220, can generate a gate control signal GCS to control the operation timing of the gate driver 610, and can generate an emission control signal ECS to control the operation timing of the emission control driver 620. The timing controller 210 can provide the gate control signal GCS to the gate driver 610 through a first gate control line GSL1. The timing controller 210 can provide the emission control signal ECS to the emission control driver 620 through a second gate control line GSL2. The timing controller 210 can provide the digital video data DATA and the data control signal DCS to the data driver 220.

[0089] The data driver 220 can convert the digital video data DATA into an analog data voltage and provide the analog data voltage to the data lines DL through fan-out lines FL. The gate signal of the gate driver 610 can select the pixels SP to which the data voltage is provided, and the selected pixels SP can receive the data voltage through the data lines DL. The data driver 220 can provide the sensing signals received through the read-out lines ROL to the processor.

[0090] The power supply unit 500 can be arranged on the circuit board 300 to provide a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 can generate a power voltage and provide the power voltage to the power line VL, and can generate a common voltage and provide the common voltage to a common electrode common to the pixels SP and the fingerprint sensor OPD. The power supply unit 500 can generate an initialization voltage and provide the initialization voltage to the initialization voltage line, generate a reference voltage and provide the reference voltage to the reference voltage line, generate a bias voltage and provide the bias voltage to the bias voltage line, and generate a reset voltage and provide the reset voltage to the reset voltage line.

[0091] The gate driver 610 may be disposed adjacent to one side of the display area DA or at one side of the non-display area NDA. The emission control driver 620 may be disposed adjacent to the other side (e.g., the opposite side) of the display area DA or at the other side (e.g., the opposite side) of the non-display area NDA, but the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver 620 may be disposed at the same side of the non-display area NDA, e.g., either one of one side and its opposite side of the non-display area NDA.

[0092] The gate driver 610 may include a plurality of transistors that generate a gate signal based on a gate control signal GCS. The emission control driver 620 may include a plurality of transistors that generate an emission signal based on an emission control signal ECS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed on the same layer as the transistors of the corresponding pixels SP. The gate driver 610 may provide a gate signal to the gate line GL, and the emission control driver 620 may provide an emission signal to the emission control line EML.

[0093] Figure 5 is a plan view showing an emission area and a sensor area of a display device according to an embodiment.

[0094] Reference Figure 5 , the display area DA may include an emission area EA and a non-emission area NEA. The emission area EA may emit light of a light-emitting element. As shown, the light-emitting element may not be provided in the non-emission area NEA. The non-emission area NEA may include sensor areas PDA spaced apart from each other, and at least one emission area EA may be interposed therebetween. The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3. For example, the first emission area EA1 may emit light of a first color (e.g., red light), the second emission area EA2 may emit light of a second color (e.g., green light), and the third emission area EA3 may emit light of a third color (e.g., blue light). In other embodiments, the first color to the third color may correspond to different combinations of the colors of light. In one embodiment, the first emission area EA1 to the third emission area EA3 may be regarded as sub-pixels.

[0095] As Figure 5As further shown, a unit pixel UP may include a first emission area EA1, two second emission areas EA2, and a third emission area EA3, which together emit light presenting a gray level of a predetermined value (e.g., the color of light generated by the combination of light from the emission areas EA), but the configuration of the unit pixel UP is not limited thereto. For example, the white gray level value may be presented based on the combination of light emitted from one first emission area EA1, light emitted from two second emission areas EA2, and light emitted from one third emission area EA3.

[0096] The areas of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different from each other. For example, the area of the third emission area EA3 may be larger than the area of the first emission area EA1, and the area of the first emission area EA1 may also be larger than the area of the second emission area EA2. In one embodiment, the areas of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be the same as each other.

[0097] The sensor area PDA may be placed at a predetermined position within the display area DA. For example, the sensor area PDA may be surrounded by the first emission area EA1, the second emission area EA2, and the third emission area EA3. The sensor area PDA may be adjacent to the first emission area EA1 or the third emission area EA3 in the X-axis direction, and may be adjacent to the second emission area EA2 in the Y-axis direction. The sensor areas PDA may be spaced apart from each other, and at least one emission area EA may be interposed therebetween. The sensor area PDA may receive light reflected by a finger or a stylus.

[0098] Figure 6 is a circuit diagram showing a pixel SP of a display device according to an embodiment.

[0099] Refer to Figure 6 , the pixel SP may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line GBL, an emission control line EML, a data line DL, a drive voltage line VDDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a low potential line VSSL. One or more of these lines may also be connected to a fingerprint sensor as described in more detail below.

[0100] The pixel SP may include a light-emitting element ED and a pixel circuit for driving the light-emitting element ED. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, and a seventh transistor ST7, and a capacitor CST.

[0101] The first transistor ST1 may be a driving transistor that controls a driving current supplied to the light-emitting element ED. The first transistor ST1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor ST1 may be connected to the third node N3, the first electrode of the first transistor ST1 may be connected to the first node N1, and the second electrode of the first transistor ST1 may be connected to the second node N2. For example, the first electrode of the first transistor ST1 may be a source electrode, and the second electrode may be a drain electrode, but the present disclosure is not limited thereto.

[0102] The first transistor ST1 may control the source-drain current Isd (hereinafter referred to as "driving current") according to a data voltage applied to the gate electrode. The driving current Isd flowing through the channel of the first transistor ST1 may be proportional to the square of the difference between the voltage Vsg between the source electrode and the gate electrode of the first transistor ST1 and the threshold voltage Vth, for example, Isd = k×(Vsg - Vth) 2 . In this case, k represents a proportionality coefficient determined by the structure and physical characteristics of the first transistor ST1, Vsg represents the source-gate voltage of the first transistor ST1, and Vth represents the threshold voltage of the first transistor ST1.

[0103] The light-emitting element ED may emit light based on the driving current Isd. The amount or brightness of the light emitted from the light-emitting element ED may be proportional to the magnitude of the driving current Isd. The light-emitting element ED may include a first electrode, a second electrode, and a light-emitting layer provided between the first electrode and the second electrode. The first electrode of the light-emitting element ED may be connected to the fourth node N4. The first electrode of the light-emitting element ED may be connected to the second electrode of the sixth transistor ST6 and the first electrode of the seventh transistor ST7 through the fourth node N4. For example, the first electrode of the light-emitting element ED may be an anode electrode or a pixel electrode, and its second electrode may be a cathode electrode or a common electrode, but the present disclosure is not limited thereto.

[0104] The second transistor ST2 can be turned on by a first gate signal of the first gate line GWL to electrically connect the data line DL to the first node N1 that is the first electrode of the first transistor ST1. The second transistor ST2 can be turned on based on the first gate signal to supply a data voltage to the first node N1. The gate electrode of the second transistor ST2 can be connected to the first gate line GWL, the first electrode of the second transistor ST2 can be connected to the data line DL, and the second electrode of the second transistor ST2 can be connected to the first node N1. The second electrode of the second transistor ST2 can be connected to the first electrode of the first transistor ST1 and the second electrode of the fifth transistor ST5 through the first node N1. For example, the first electrode of the second transistor ST2 can be a source electrode, and the second electrode of the second transistor ST2 can be a drain electrode, but the present disclosure is not limited thereto. The first gate line GWL can also be coupled to a third sensor transistor PT3 as described below (see Figure 8 ).

[0105] The third transistor ST3 can be turned on by a second gate signal of the second gate line GCL to electrically connect the second node N2 that is the second electrode of the first transistor ST1 to the third node N3 coupled to the gate electrode of the first transistor ST1. The first electrode of the third transistor ST3 can be connected to the second electrode of the first transistor ST1 and the first electrode of the sixth transistor ST6 through the second node N2. The second electrode of the third transistor ST3 can be connected to the gate electrode of the first transistor ST1, the first electrode of the fourth transistor ST4, and the first capacitor electrode of the capacitor CST through the third node N3. For example, the first electrode of the third transistor ST3 can be a drain electrode, and the second electrode of the third transistor ST3 can be a source electrode, but the present disclosure is not limited thereto.

[0106] The fourth transistor ST4 can be turned on by a third gate signal of the third gate line GIL to electrically connect the third node N3 coupled to the gate electrode of the first transistor ST1 to the first initialization voltage line VIL1. The fourth transistor ST4 can be turned on based on the third gate signal to discharge the gate electrode of the first transistor ST1 with a first initialization voltage. The gate electrode of the fourth transistor ST4 can be connected to the third gate line GIL, the first electrode of the fourth transistor ST4 can be connected to the third node N3, and the second electrode of the fourth transistor ST4 can be connected to the first initialization voltage line VIL1. The first electrode of the fourth transistor ST4 can be connected to the gate electrode of the first transistor ST1, the second electrode of the third transistor ST3, and the first capacitor electrode of the capacitor CST through the third node N3. For example, the first electrode of the fourth transistor ST4 can be a drain electrode, and the second electrode of the fourth transistor ST4 can be a source electrode, but the present disclosure is not limited thereto.

[0107] The fifth transistor ST5 can be turned on by the emission signal of the emission control line EML to electrically connect the drive voltage line VDDL to the first node N1 connected to the source electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 can be connected to the emission control line EML, the first electrode of the fifth transistor ST5 can be connected to the drive voltage line VDDL, and the second electrode of the fifth transistor ST5 can be connected to the first node N1. The second electrode of the fifth transistor ST5 can be connected to the first electrode of the first transistor ST1 and the second electrode of the second transistor ST2 through the first node N1. For example, the first electrode of the fifth transistor ST5 can be the source electrode, and the second electrode of the fifth transistor ST5 can be the drain electrode, but the present disclosure is not limited thereto.

[0108] The sixth transistor ST6 can be turned on by the emission signal of the emission control line EML to electrically connect the second node N2, which is the second electrode of the first transistor ST1, to the fourth node N4 connected to the first electrode of the light-emitting element ED. The gate electrode of the sixth transistor ST6 can be connected to the emission control line EML, the first electrode of the sixth transistor ST6 can be connected to the second node N2, and the second electrode of the sixth transistor ST6 can be connected to the fourth node N4. The second electrode of the sixth transistor ST6 can be connected to the first electrode of the light-emitting element ED and the first electrode of the seventh transistor ST7 through the fourth node N4. For example, the first electrode of the sixth transistor ST6 can be the source electrode, and the second electrode of the sixth transistor ST6 can be the drain electrode, but the present disclosure is not limited thereto.

[0109] In operation, when the fifth transistor ST5, the first transistor ST1, and the sixth transistor ST6 are all turned on, the drive current Isd can be supplied to the light-emitting element ED.

[0110] The seventh transistor ST7 can be turned on by the fourth gate signal of the fourth gate line GBL to electrically connect the second initialization voltage line VIL2 to the fourth node N4 connected to the first electrode of the light-emitting element ED. The seventh transistor ST7 can be turned on based on the fourth gate signal to discharge the first electrode of the light-emitting element ED with the second initialization voltage. The gate electrode of the seventh transistor ST7 can be connected to the fourth gate line GBL, the first electrode of the seventh transistor ST7 can be connected to the fourth node N4, and the second electrode of the seventh transistor ST7 can be connected to the second initialization voltage line VIL2. The first electrode of the seventh transistor ST7 can be connected to the first electrode of the light-emitting element ED and the second electrode of the sixth transistor ST6 through the fourth node N4.

[0111] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may include a silicon-based semiconductor region. For example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may include a semiconductor region made of low-temperature polycrystalline silicon (LTPS). The semiconductor region made of low-temperature polycrystalline silicon may have a high electron mobility and excellent conduction characteristics. Accordingly, each pixel SP of the display device 10 includes the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 having excellent conduction characteristics, thereby stably and effectively driving the plurality of pixels SP.

[0112] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may be a p-type transistor. For example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may output the current flowing into the first electrode to the second electrode based on a low gate voltage applied to their gate electrodes.

[0113] Each of the third transistor ST3 and the fourth transistor ST4 may include an oxide-based semiconductor region. For example, each of the third transistor ST3 and the fourth transistor ST4 may have a coplanar structure in which a gate electrode is disposed on the oxide-based semiconductor region. The transistor having the coplanar structure has excellent leakage current characteristics and can achieve low-frequency driving, thereby reducing power consumption. Accordingly, the display device 10 includes the third transistor ST3 and the fourth transistor ST4 having excellent leakage current characteristics, thereby preventing leakage current from flowing into the pixel SP and stably maintaining the voltage within the pixel SP.

[0114] Each of the third transistor ST3 and the fourth transistor ST4 may be an n-type transistor. For example, each of the third transistor ST3 and the fourth transistor ST4 may output the current flowing into the first electrode to the second electrode based on a high gate voltage applied to the gate electrode.

[0115] The capacitor CST may be connected between a third node N3 coupled to the gate electrode of the first transistor ST1 and a driving voltage line VDDL. For example, a first capacitor electrode of the capacitor CST may be connected to the third node N3, and a second capacitor electrode of the capacitor CST may be connected to the driving voltage line VDDL, thereby maintaining the potential difference between the driving voltage line VDDL and the gate electrode of the first transistor ST1.

[0116] Figure 7It is a cross-sectional view showing a pixel SP of a display device 10 according to an embodiment.

[0117] Reference Figure 7 , the display panel 100 may sequentially include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, a first interlayer insulating layer ILD1, a second active layer ACTL2, a third gate insulating layer GI3, a third gate layer GTL3, a second interlayer insulating layer ILD2, a first source metal layer SDL1, a first passivation layer PAS1, a second source metal layer SDL2, a second passivation layer PAS2, a third passivation layer PAS3, a planarization layer OC, a pixel defining layer PDL, a light-emitting element ED, and a packaging layer TFEL. In other embodiments, one or more of the above features may be arranged in a different order or may be omitted. In still other embodiments, one or more additional layers may be included in the pixel SP.

[0118] The substrate SUB may be a base substrate or a base member. In one embodiment, the substrate SUB may be a flexible substrate capable of being bent, folded, curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0119] The buffer layer BF may be disposed on the substrate SUB. For example, the buffer layer BF may include an inorganic layer capable of preventing air or moisture from penetrating into the interior of the pixel SP. For example, the buffer layer BF may include a plurality of inorganic layers stacked alternately.

[0120] The first active layer ACTL1 may be disposed on the buffer layer BF. The first active layer ACTL1 may include a semiconductor (e.g., silicon-based) material. For example, the first active layer ACTL1 may be formed of low-temperature polycrystalline silicon (LTPS). The first active layer ACTL1 may include a semiconductor region ACT1, a first electrode SE1, and a second electrode DE1 of the first transistor ST1, and a semiconductor region ACT2, a first electrode SE2, and a second electrode DE2 of the second transistor ST2.

[0121] The first gate insulating layer GI1 may be disposed on the first active layer ACTL1. The first gate insulating layer GI1 may insulate the first active layer ACTL1 from the first gate layer GTL1.

[0122] The first gate layer GTL1 can be disposed on the first gate insulating layer GI1. The first gate layer GTL1 can include the gate electrode GE1 of the first transistor ST1, the gate electrode GE2 of the second transistor ST2, and the first capacitor electrode CPE1. The gate electrode GE1 of the first transistor ST1 can be a part of the first capacitor electrode CPE1, and the gate electrode GE2 of the second transistor ST2 can be a part of the first gate line GWL.

[0123] The second gate insulating layer GI2 can be disposed on the first gate layer GTL1. The second gate insulating layer GI2 can insulate the first gate layer GTL1 from the second gate layer GTL2.

[0124] The second gate layer GTL2 can be disposed on the second gate insulating layer GI2. The second gate layer GTL2 can include the second capacitor electrode CPE2. The second capacitor electrode CPE2 can overlap with the first capacitor electrode CPE1.

[0125] The first interlayer insulating layer ILD1 can be disposed on the second gate layer GTL2. The first interlayer insulating layer ILD1 can insulate the second gate layer GTL2 from the second active layer ACTL2.

[0126] The second active layer ACTL2 can be disposed on the first interlayer insulating layer ILD1. The second active layer ACTL2 can include an oxide-based material. The second active layer ACTL2 can include the semiconductor region ACT3 of the third transistor ST3, the first electrode DE3, and the second electrode SE3.

[0127] The third gate insulating layer GI3 can be disposed on the second active layer ACTL2. The third gate insulating layer GI3 can insulate the second active layer ACTL2 from the third gate layer GTL3.

[0128] The third gate layer GTL3 can be disposed on the third gate insulating layer GI3. The third gate layer GTL3 can include the gate electrode GE3 of the third transistor ST3. The gate electrode GE3 of the third transistor ST3 can be a part of the second gate line GCL.

[0129] The second interlayer insulating layer ILD2 can be disposed on the third gate layer GTL3. The second interlayer insulating layer ILD2 can insulate the third gate layer GTL3 from the first source metal layer SDL1.

[0130] The first source metal layer SDL1 can be disposed on the second interlayer insulating layer ILD2. The first source metal layer SDL1 can include a first connection electrode CE1, a second connection electrode CE2, and a third connection electrode CE3. The first connection electrode CE1 can electrically connect the data line DL to the first electrode SE2 of the second transistor ST2. The second connection electrode CE2 can electrically connect the first capacitor electrode CPE1 to the second electrode SE3 of the third transistor ST3. The third connection electrode CE3 can electrically connect the first electrode DE3 of the third transistor ST3 to the second electrode DE1 of the first transistor ST1.

[0131] The first passivation layer PAS1 can be disposed on the first source metal layer SDL1. The first passivation layer PAS1 can insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0132] The second source metal layer SDL2 can be disposed on the first passivation layer PAS1. The second source metal layer SDL2 can include the data line DL. The driving voltage line VDDL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the low potential line VSSL can be disposed in the second source metal layer SDL2.

[0133] The second passivation layer PAS2 can be disposed on the second source metal layer SDL2. The second passivation layer PAS2 can insulate the second source metal layer SDL2 from the third source metal layer.

[0134] The third passivation layer PAS3 can be disposed on the second passivation layer PAS2. The planarization layer OC can be disposed on the third passivation layer PAS3. The planarization layer OC can planarize the upper end of the transistor layer TFTL. The planarization layer OC can include an organic insulating material such as polyimide (PI).

[0135] The pixel definition layer PDL can be disposed on the planarization layer OC. The pixel definition layer PDL can define a plurality of emission regions EA. The pixel definition layer PDL can include, for example, an organic insulating material such as polyimide (PI).

[0136] The light-emitting element ED can include a first (anode) electrode AE, a light-emitting layer EL, and a second (cathode) electrode CAT. The first electrode AE can be disposed on the planarization layer OC. The first electrode AE can overlap with one of the plurality of emission regions EA defined by the pixel definition layer PDL. The first electrode AE can receive a driving current from the pixel circuit of the pixel SP.

[0137] The light-emitting layer EL may be disposed on the first electrode AE. For example, the light-emitting layer EL may be an organic light-emitting layer made of an organic material, but is not limited thereto. In the case where the light-emitting layer EL corresponds to the organic light-emitting layer, when the pixel circuit of the pixel SP applies a predetermined voltage to the first electrode AE and the second electrode CAT receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer. When the holes and electrons recombine with each other in the light-emitting layer EL, the pixel SP may cause light emission.

[0138] The second electrode CAT may be disposed on the light-emitting layer EL. For example, the second electrode CAT may be implemented in the form of an electrode common to a plurality of pixels SP without being distinguished for each of the plurality of pixels SP. The second electrode CAT may be disposed on the light-emitting layer EL in a plurality of emission regions EA, and may be disposed on the pixel defining layer PDL in a region other than the plurality of emission regions EA.

[0139] The encapsulation layer TFEL may be disposed on the second electrode CAT to cover the plurality of light-emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the plurality of light-emitting elements ED. The encapsulation layer TFEL may include at least one organic layer to protect the plurality of light-emitting elements ED from particles such as dust.

[0140] Figure 8 is a circuit diagram showing the fingerprint sensor OPD of the display device 10 according to one embodiment.

[0141] Reference Figure 8 , the fingerprint sensor OPD may be connected to the first gate line GWL, the reset signal line GRL, the reset voltage line VRL, the second initialization voltage line VIL2, and the readout line ROL. The fingerprint sensor OPD may include a light-receiving element PD and a sensor circuit for driving the light-receiving element PD. The sensor circuit may include a first sensor transistor PT1, a second sensor transistor PT2, and a third sensor transistor PT3.

[0142] The first sensor transistor PT1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first sensor transistor PT1 may be connected to the sensor node NS, the first electrode of the first sensor transistor PT1 may be connected to the third sensor transistor PT3, and the second electrode of the first sensor transistor PT1 may be connected to the second initialization voltage line VIL2. The first sensor transistor PT1 may control the source-drain current Isd (hereinafter referred to as "sensing current") based on the voltage of the sensor node NS, which is the first electrode of the light receiving element PD. The sensing current flowing through the channel of the first sensor transistor PT1 may be proportional to the square of the difference between the voltage Vsg between the source electrode and the gate electrode of the first sensor transistor PT1 and the threshold voltage Vth. For example, Isd = k′ × (Vsg - Vth). 2 In this case, k' represents a proportionality coefficient determined by the structure and physical characteristics of the first sensor transistor PT1, Vsg represents the source-gate voltage of the first sensor transistor PT1, and Vth represents the threshold voltage of the first sensor transistor PT1. The first electrode of the first sensor transistor PT1 may be the source electrode, and the second electrode of the first sensor transistor PT1 may be the drain electrode, but they are not limited thereto.

[0143] The second sensor transistor PT2 (or reset transistor) may be turned on by the reset signal of the reset signal line GRL to provide a reset voltage to the sensor node NS. The gate electrode of the second sensor transistor PT2 may be connected to the reset signal line GRL, the first electrode of the second sensor transistor PT2 may be connected to the reset voltage line VRL, and the second electrode of the second sensor transistor PT2 may be connected to the sensor node NS. The second electrode of the second sensor transistor PT2 may be connected to the first electrode of the light receiving element PD and the gate electrode of the first sensor transistor PT1 through the sensor node NS. The first electrode of the second sensor transistor PT2 may be the drain electrode, and the second electrode of the second sensor transistor PT2 may be the source electrode, but they are not limited thereto.

[0144] The third sensor transistor PT3 can be turned on by the first gate signal of the first gate line GWL to electrically connect the first electrode of the first sensor transistor PT1 to the readout line ROL. The third sensor transistor PT3 can include a third-first sensor transistor PT3-1 and a third-second sensor transistor PT3-2 connected in series. The third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 can be connected in series between the first electrode of the first sensor transistor PT1 and the readout line ROL. The gate electrodes of the third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 can be integrally formed and electrically connected to the first gate line GWL. The first electrode of the third-first sensor transistor PT3-1 can be connected to the readout line ROL, and the second electrode of the third-second sensor transistor PT3-2 can be connected to the first electrode of the first sensor transistor PT1. The second electrode of the third-first sensor transistor PT3-1 and the first electrode of the third-second sensor transistor PT3-2 can be integrally formed. The first electrode of each of the third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 can be a source electrode, and its second electrode can be a drain electrode, but they are not limited thereto.

[0145] The light receiving element PD can identify a part of the pattern of the user's fingerprint (e.g., a ridge or a valley) based on the light reflected from the user's finger. The first electrode of the light receiving element PD can be connected to the sensor node NS that serves as the gate electrode of the first sensor transistor PT1. The second electrode of the light receiving element PD can be connected to the low potential line VSSL. The second electrode of the light receiving element PD can receive a low potential voltage from the low potential line VSSL.

[0146] In operation, when the user's finger touches the display panel 100, the light receiving element PD can receive the light reflected by the ridge or valley of the finger. The light output from the light emitting element ED can be reflected by the ridge or valley of the finger, and the reflected light can reach the light receiving element PD. The light receiving element PD can convert the energy of the reflected light into an electrical signal (current or voltage) formed between the first electrode and the second electrode. The converted electrical signal can flow from the sensor node NS to the low potential line VSSL. For example, when the light receiving element PD receives light, an electric field is formed between the first electrode and the second electrode of the light receiving element PD. Therefore, a current can flow into the light receiving element PD in proportion to the amount of light, and the voltage of the sensor node NS can decrease. When the light receiving element PD receives light, the voltage of the sensor node NS can decrease, and the magnitude of the sensing current (or source-drain current) of the first sensor transistor PT1 can decrease. The sensing current of the first sensor transistor PT1 can be applied to the display driver 200 as a sensing signal through the third sensor transistor PT3 and the readout line ROL.

[0147] Figure 9 is a layout diagram showing the fingerprint sensor OPD of the display device 10 according to an embodiment. Figure 10 is according to an embodiment along Figure 9 a cross-sectional view taken along line I-I'.

[0148] Figure 11 is according to an embodiment along Figure 9 a cross-sectional view taken along line II-II'. Hereinafter, elements identical to the above elements will be briefly described or omitted.

[0149] Referring to Figures 8 to 11 , the fingerprint sensor OPD can be connected to a first gate line GWL, a reset signal line GRL, a reset voltage line VRL, a second initialization voltage line VIL2, and a readout line ROL. As will be discussed in more detail below, a power line can shield the readout line ROL from the reset signal line GRL and / or one or more other lines, the other lines including lines connected to pixels SP, such as data lines DL. This can increase the sensitivity of the fingerprint sensor OPD. The first gate line GWL can be disposed in a first gate layer GTL1 and extend in the X-axis direction. The first gate line GWL can provide a first gate signal to a third sensor transistor PT3.

[0150] The reset signal line GRL can be disposed in a third gate layer GTL3 and extend in the X-axis direction. The reset signal line GRL can provide a reset signal to a second sensor transistor PT2 to reset the sensor node NS.

[0151] The reset voltage line VRL can provide a reset voltage to a first electrode PDE2 of the second sensor transistor PT2. The reset voltage line VRL can include a first portion VRLa, a second portion VRLb, and a third portion VRLc. According to one embodiment, the first portion VRLa of the reset voltage line VRL can form a part of the power line that shields the readout line. In other embodiments, the power line can include a low-potential line VSSL. The first portion VRLa of the reset voltage line VRL can be disposed in a second source metal layer SDL2 and extend in the Y-axis direction. The first portion VRLa of the reset voltage line VRL can be disposed in parallel with the data line DL. The first portion VRLa of the reset voltage line VRL can be connected to the second portion VRLb.

[0152] The second portion VRLb of the reset voltage line VRL can be disposed in a first source metal layer SDL1 and extend in the X-axis direction. The second portion VRLb of the reset voltage line VRL can be connected between the first portion VRLa and the third portion VRLc.

[0153] The third portion VRLc of the reset voltage line VRL may be disposed in the second source metal layer SDL2 to overlap with the semiconductor region PACT2 of the second sensor transistor PT2. The third portion VRLc of the reset voltage line VRL may be connected to the first electrode PDE2 of the second sensor transistor PT2 to provide a reset voltage. The third portion VRLc of the reset voltage line VRL may block light incident from the upper portion of the second sensor transistor PT2.

[0154] The second initialization voltage line VIL2 may be disposed in the first source metal layer SDL1 and extend in the X-axis direction. A portion of the second initialization voltage line VIL2 may protrude in the Y-axis direction and may be connected to the second electrode of the first sensor transistor PT1. The second initialization voltage line VIL2 may provide a second initialization voltage to the second electrode of the first sensor transistor PT1.

[0155] The drive voltage line VDDL may be disposed in the first source metal layer SDL1 and extend in the X-axis direction. The drive voltage line VDDL may extend to the pixel SP and may provide a drive voltage to the pixel SP.

[0156] The fingerprint sensor OPD may include a first sensor transistor PT1, a second sensor transistor PT2, and a third sensor transistor PT3, as well as a light receiving element PD (for example, also see Figure 8 ). The first sensor transistor PT1 may include a semiconductor region PACT1 and a gate electrode PGE1. The semiconductor region PACT1 of the first sensor transistor PT1 may be disposed in the first active layer ACTL1, and the gate electrode PGE1 of the first sensor transistor PT1 may be disposed in the first gate layer GTL1. The gate electrode PGE1 of the first sensor transistor PT1 may overlap with the semiconductor region PACT1 of the first sensor transistor PT1. The semiconductor region PACT1 of the first sensor transistor PT1 may include a silicon-based material. For example, the semiconductor region PACT1 of the first sensor transistor PT1 may include low-temperature polycrystalline silicon (LTPS).

[0157] The gate electrode PGE1 of the first sensor transistor PT1 may be electrically connected to the sensor node electrode NSE of the second source metal layer SDL2 through a sensor connection electrode PCE disposed in the first source metal layer SDL1. The sensor node electrode NSE may correspond to Figure 8 the sensor node NS (reset by the reset signal line GRL), and may be electrically connected to the first electrode of the light receiving element PD. The gate electrode PGE1 of the first sensor transistor PT1 may be electrically connected to the second electrode PSE2 of the second sensor transistor PT2 disposed in the second active layer ACTL2 through the sensor connection electrode PCE.

[0158] The second sensor transistor PT2 may include a semiconductor region PACT2, a gate electrode PGE2, a first electrode PDE2, and a second electrode PSE2. The semiconductor region PACT2, the first electrode PDE2, and the second electrode PSE2 of the second sensor transistor PT2 may be disposed in the second active layer ACTL2, and the gate electrode PGE2 of the second sensor transistor PT2 may be disposed in the third gate layer GTL3. The gate electrode PGE2 of the second sensor transistor PT2 may be a part of the reset signal line GRL of the third gate layer GTL3 and may overlap with the semiconductor region PACT2 of the second sensor transistor PT2. For example, the semiconductor region PACT2 of the second sensor transistor PT2 may include an oxide-based material. A light blocking layer BML may be disposed in the second gate layer GTL2 to overlap with the semiconductor region PACT2 of the second sensor transistor PT2. Accordingly, the light blocking layer BML may block light incident from the lower portion of the second sensor transistor PT2.

[0159] The third sensor transistor PT3 may include a third-first sensor transistor PT3-1 and a third-second sensor transistor PT3-2 connected in series. The third-first sensor transistor PT3-1 may include a semiconductor region PACT3-1, a gate electrode PGE3-1, a first electrode PSE3-1, and a second electrode PDE3-1. The semiconductor region PACT3-1, the first electrode PSE3-1, and the second electrode PDE3-1 of the third-first sensor transistor PT3-1 may be disposed in the first active layer ACTL1, and the gate electrode PGE3-1 may be disposed in the first gate layer GTL1. The gate electrode PGE3-1 of the third-first sensor transistor PT3-1 may overlap with the semiconductor region PACT3-1 of the third-first sensor transistor PT3-1. The semiconductor region PACT3-1 of the third-first sensor transistor PT3-1 may include low-temperature polycrystalline silicon (LTPS). Each of the gate electrode PGE3-1 of the third-first sensor transistor PT3-1 and the gate electrode of the third-second sensor transistor PT3-2 may be a part of the first gate line GWL of the first gate layer GTL1.

[0160] The first electrode PSE3-1 of the third-first sensor transistor PT3-1 can be electrically connected to the readout line ROL of the third source metal layer SDL3 through the readout electrode ROE of the first source metal layer SDL1. The third source metal layer SDL3 can be disposed on the second passivation layer PAS2. The readout line ROL can extend in the Y-axis direction and can overlap with a power line formed by the low potential line VSSL of the second source metal layer SDL2 or the first portion VRLa of the reset voltage line VRL. For example, a part of the readout line ROL can overlap with the low potential line VSSL, and another part of the readout line ROL can overlap with the first portion VRLa of the reset voltage line VRL, but the present disclosure is not limited thereto. This arrangement of the power line can be used to shield the readout line ROL from the data line DL and / or other lines, which will be described in more detail below.

[0161] More specifically, a DC power line (such as the first portion VRLa of the reset voltage line VRL or the low potential line VSSL) can shield the readout line ROL from the reset signal line GRL, the emission control line EML, the first gate line GWL, and the second gate line GCL. The data line DL can be coupled to the reset signal line GRL, the emission control line EML, the first gate line GWL, and the second gate line GCL, but the data line DL may not be coupled to the readout line ROL through a DC power line (e.g., the first portion VRLa of the reset voltage line VRL or the low potential line VSSL). Accordingly, the display device 10 can include a DC power line (such as the first portion VRLa of the reset voltage line VRL or the low potential line VSSL) that overlaps with the readout line ROL, thereby preventing a connection between the readout line ROL and the data line DL and improving the sensitivity of the fingerprint sensor OPD.

[0162] The effects of the present disclosure are not limited to the effects set forth herein. Through reference to the claims, the above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains. Embodiments can be combined to form additional embodiments.

Claims

1. A fingerprint sensor, characterized in that The fingerprint sensor comprises: a readout line disposed on the substrate and extending in a first direction; A light receiving element is arranged on the readout line; a first sensor transistor configured to control a sensing current based on a voltage of a sensor node coupled to a first electrode of the light receiving element; a second sensor transistor configured to provide a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting the first electrode of the first sensor transistor to the readout line based on a gate signal; and A power line is provided in a layer between the second sensor transistor and the readout line and extends in the first direction, the power line overlapping the readout line.

2. The fingerprint sensor according to claim 1, characterized in that: The power line is a DC power line including a reset voltage line configured to supply the reset voltage or a low potential line connected to the second electrode of the light receiving element to supply a low potential voltage.

3. The fingerprint sensor according to claim 1, characterized in that: The semiconductor region of each of the first sensor transistor and the third sensor transistor includes a silicon-based material, and The semiconductor region of the second sensor transistor includes an oxide-based material.

4. The fingerprint sensor according to claim 1, characterized in that: The third sensor transistor includes a third-first sensor transistor and a third-second sensor transistor connected in series between the first electrode of the first sensor transistor and the readout line.

5. The fingerprint sensor according to claim 1, characterized in that: The fingerprint sensor further comprises: A first active layer is disposed on the substrate; A first gate layer, disposed on the first active layer; A second gate layer, disposed on the first gate layer; A second active layer, disposed on the second gate layer; a third gate layer, disposed on the second active layer; A first source metal layer, disposed on the third gate layer; a second source metal layer disposed on the first source metal layer, the second source metal layer including the power line; and A third source metal layer is disposed on the second source metal layer, and the third source metal layer includes the readout line.

6. The fingerprint sensor according to claim 5, characterized in that: The fingerprint sensor further comprises: A readout electrode is disposed in the first source metal layer to electrically connect the readout line with the third sensor transistor.

7. The fingerprint sensor according to claim 5, characterized in that: The fingerprint sensor further comprises: a sensor node electrode, disposed in the second source metal layer, the sensor node electrode corresponding to the sensor node; and A sensor connection electrode is disposed in the first source metal layer, and the sensor connection electrode electrically connects the gate electrode of the first sensor transistor with the sensor node electrode.

8. The fingerprint sensor according to claim 5, characterized in that: The fingerprint sensor further comprises: Reset voltage line, including: a first portion, disposed in the second source metal layer and extending in the first direction, a second portion disposed in the first source metal layer and connected to the first portion and extending in a second direction crossing the first direction, and A third portion is disposed in the second source metal layer and is electrically connected between the second portion and the first electrode of the second sensor transistor.

9. The fingerprint sensor according to claim 8, characterized in that: The third portion of the reset voltage line overlaps a semiconductor region of the second sensor transistor.

10. A display device, characterized in that The display device comprises: A fingerprint sensor including a readout line and a light receiving element, the readout line being provided on a substrate and extending in a first direction, the light receiving element being provided on the readout line; and A pixel comprising a light emitting element, wherein the light emitting element is disposed in the same layer as the light receiving element, wherein the fingerprint sensor further comprises: a first sensor transistor configured to control a sensing current based on a voltage of a sensor node which is a first electrode of the light receiving element; a second sensor transistor configured to provide a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting the first electrode of the first sensor transistor to the readout line based on a gate signal; and A power line is provided in a layer between the second sensor transistor and the readout line and extends in the first direction, and the power line overlaps the readout line.

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