Chip power supply time sequence control circuit
By designing the chip power supply timing control circuit, using components such as resistors, capacitors and transistors to achieve delayed power supply to the 5V power supply, solving the chip's requirements for power supply timing, eliminating high-level pulses and reducing hardware costs.
Patent Information
- Application Number
- CN202421982438.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-15
- Publication Date
- 2025-06-13
- Estimated Expiration
- 2034-08-15
AI Technical Summary
Some chips have special requirements for the timing of power supply. The prior art is difficult to ensure that the 3.3V level is stable without increasing the circuit cost, and then power the 5V level is supplied to avoid high-level pulses output instantly when powering on the VCCB side.
A chip power supply timing control circuit is designed, and the delayed power supply to the 5V power supply is achieved by using a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a first transistor and a three-terminal voltage stabilization chip to ensure that the 3.3V level is stable and then power is supplied to the VCCB side.
Without changing the power supply circuit required by the original chip, flexible control of the chip power supply with time-series requirements is achieved, eliminating the high-level pulse output instantly on the VCCB side and reducing hardware costs.
Smart Images
Figure CN222981411U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of power supply circuits, and particularly to a chip power supply timing control circuit. Background Art
[0002] Some chips have special requirements for the power supply timing, such as 74LVX3245, 74LVX4245, etc. As Figure 1 shown, such chips are usually used to convert the 3.3V level signal output by the MCU (microcontroller, such as a single-chip microcomputer) into a 5V level signal. However, it is found in actual use that no matter how such chips are configured, as long as VCCB (usually 5V) is powered on first, there will be a high-level pulse signal with a duration greater than 1ms on the output side (i.e., side B). If VCCA (usually 3.3V) is powered on first, there is no such phenomenon.
[0003] To solve this problem, if 3.3V is established earlier than 5V and 5V level is connected after 3.3V is stable, the output is normal and there is no high-level pulse phenomenon. This requires that the VCCA side of chips such as 74LVX3245 and 74LVX4245 be powered on earlier than the VCCB side, and the VCCB side be powered on after the power supply level on the VCCA side is stable. However, in actual engineering, the 3.3V level on the VCCA side is often generated by converting the 5V level, that is, 5V is almost always established earlier than 3.3V in the actual circuit. Therefore, a circuit needs to be designed to ensure that the 5V level supplies power to the chip only after the 3.3V level is stable.
[0004] A common solution is that the 5V power supply on the VCCB side is generated by another controllable LDO or DC / DC circuit. After the 3.3V power supply on the VCCA side is established and stable, the LDO or DC / DC is controlled to generate the 5V power supply on the VCCB side. However, this requires generating two 5V power supplies, increasing the circuit cost. Another solution is to let the auxiliary power supply generate 3.3V first, and then control the DC / DC circuit to generate 5V after 3.3V is stable. For example, both 3.3V and 5V are converted from the pre-stage power supply through DC / DC, but the DC / DC power supply chip that generates 5V is controlled by the 3.3V voltage, that is, the power supply chip that generates 5V starts to work only when the 3.3V power supply is normal. This can ensure that 3.3V is generated earlier than 5V, but it will inevitably cause a delay in the 5V power supply of the entire circuit, which may lead to power supply timing problems in other parts of the circuit. Content of the Utility Model
[0005] The utility model provides a chip power supply timing control circuit to solve the above problems.
[0006] The utility model adopts the following technical solutions:
[0007] A chip power supply timing control circuit, comprising: a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a first triode, and a three-terminal voltage regulator chip;
[0008] One end of the first capacitor is grounded, and the other end is connected to a 5V power supply;
[0009] The emitter of the first triode is connected to a 5V power supply, and the collector serves as a 5V output terminal;
[0010] One end of the second capacitor is grounded, and the other end is connected to the collector of the first triode;
[0011] One end of the first resistor is connected to the emitter of the first triode, and the other end is connected to the base of the first triode;
[0012] The third resistor and the third capacitor are connected in parallel, one end is grounded, and the other end is connected to the input terminal of the three-terminal voltage regulator chip;
[0013] One end of the second resistor is connected to a 3.3V power supply, and the other end is connected to the input terminal of the three-terminal voltage regulator chip;
[0014] The output terminal of the three-terminal voltage regulator chip is connected to the base of the first triode.
[0015] A chip power supply timing control circuit, characterized in that it comprises: a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a first triode, and a second triode;
[0016] One end of the first capacitor is grounded, and the other end is connected to a 5V power supply;
[0017] The collector of the first triode is connected to a 5V power supply, and the emitter serves as a 5V output terminal;
[0018] One end of the second capacitor is grounded, and the other end is connected to the emitter of the first triode;
[0019] One end of the first resistor is connected to the collector of the first triode, and the other end is connected to the base of the first triode;
[0020] The third resistor and the third capacitor are connected in parallel, one end is grounded, and the other end is connected to the base of the second triode;
[0021] One end of the second resistor is connected to a control signal, and the other end is connected to the base of the second triode;
[0022] The collector of the second triode is connected to the base of the first triode, and the emitter is grounded.
[0023] Further, the model of the three-terminal voltage regulator chip is TL431.
[0024] With the above technical solution, the utility model can flexibly and conveniently control the power supply of chips with timing requirements through software or hardware without changing the original power supply circuit required by the chips, and the hardware cost is relatively low. Brief Description of the Drawings
[0025] Figure 1 The figure shows the interface circuit diagram of the 74LVX3245 chip.
[0026] Figure 2 The figure shows the circuit diagram of the hardware control adopted in the embodiment of the utility model.
[0027] Figure 3 The figure shows the circuit diagram of the MCU control adopted in the embodiment of the utility model. Detailed Embodiments
[0028] To further illustrate each embodiment, the utility model provides drawings. These drawings are part of the disclosure of the utility model, mainly used to illustrate the embodiments, and can be combined with the relevant descriptions in the specification to explain the operation principle of the embodiments. With reference to these contents, those of ordinary skill in the art should be able to understand other possible implementation manners and the advantages of the utility model. The components in the figures are not drawn to scale, and similar component symbols are usually used to represent similar components.
[0029] Now, the utility model will be further described in combination with the drawings and specific embodiments.
[0030] This embodiment discloses a chip power supply timing control circuit, which can, without changing the original power supply circuit, only delay the power supply time of the VCCB side of chips such as 74LVX3245 and 74LVX4245, so as to eliminate the high-level pulse output at the moment of power-on of the VCCB side.
[0031] The chip power supply timing control circuit is as Figure 2As shown in the figure, it includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first triode Q1, and a three-terminal voltage regulator chip U1. Among them, one end of the first capacitor C1 is grounded and the other end is connected to the input 5V power supply; the emitter of the first triode Q1 is connected to the input 5V power supply, and the collector is used as the 5V output terminal and input to the VCCB pin of the above chip; one end of the second capacitor C2 is grounded and the other end is connected to the collector of the first triode Q1; one end of the first resistor R1 is connected to the emitter of the first triode Q1 and the other end is connected to the base of the first triode; after the third resistor R3 and the third capacitor C3 are connected in parallel, one end is grounded and the other end is connected to the input end of the three-terminal voltage regulator chip U1; one end of the second resistor R2 is connected to the input 3.3V power supply and the other end is connected to the input end of the three-terminal voltage regulator chip U1; the output end of the three-terminal voltage regulator chip U1 is connected to the base of the first triode Q1, and the ground end is grounded. In this embodiment, the three-terminal voltage regulator chip U1 is preferably TL431, and other comparators can also be used in other embodiments, which are not limited here.
[0032] Figure 2 The working principle of the chip power supply timing control circuit shown is as follows: When the 5V is established but the 3.3V level is not established, the level at the pin1 end (i.e., the input end) of TL431 is lower than 2.5V, TL431 is not turned on, and the triode Q1 is also not turned on, and the level output to VCCB is 0V. When the 3.3V is established, the capacitor C3 is charged through the resistor R2, and the level at both ends of C3 gradually increases. When the level at both ends of C3 exceeds 2.5V, TL431 is turned on, the base of Q1 is pulled low, Q1 is turned on, and VCCB outputs 5V. Therefore, as long as the parameters of the resistors R2, R3, and the capacitor C3 are reasonably selected, it can be ensured that after the 3.3V level is established, VCCB is generated after an appropriate delay. Usually, R3>>R2, so R3 can be ignored. Then there is (3.3V - 2.5V) / (2×R2)×t = C3×2.5V, from which the time when VCCB needs to lag behind the 3.3V level can be calculated. The time selection does not need to be too large, as long as it can ensure that the 3.3V is stable.
[0033] Figure 2 The circuit shown adopts pure hardware control, and the advantage is that it does not require software participation and does not occupy MCU resources. However, the flexibility is relatively poor. Once the hardware parameters are determined, the delay time cannot be flexibly adjusted as needed. On this basis, this embodiment also provides Figure 3 The chip power supply timing control circuit shown, which is Figure 2 only different in that the three-terminal voltage regulator chip U1 therein is replaced by a second triode Q2, and the 3.3V power supply input is replaced by the control signal PZ (high level is 3.3V, low level is 0V) output by the MCU.
[0034] Figure 2 The circuit working principle in Figure 2 is the same, but it uses an MCU to control the power-on delay time of VCCB, and can flexibly configure the time when VCCB lags behind VCCA. It can also supply power to VCCB only when chips such as 74LVX3245 and 74LVX4245 need to work.
[0035] Based on not changing the power supply circuit required by the original chip, this embodiment can flexibly and conveniently control the power supply of chips with timing requirements through software or hardware, and the hardware cost is relatively low.
[0036] Although the present invention is specifically shown and described in combination with the preferred embodiments, those skilled in the art should understand that various changes can be made to the present invention in terms of form and details without departing from the spirit and scope of the present invention defined by the appended claims, and all of them are within the protection scope of the present invention.
Claims
1. A chip power timing control circuit, characterized in that: include: A first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a first transistor and a three-terminal voltage stabilizing chip; One end of the first capacitor is grounded and the other end is connected to a 5V power supply; The emitter of the first transistor is connected to a 5V power supply, and the collector serves as a 5V output terminal; One end of the second capacitor is grounded, and the other end is connected to the collector of the first transistor; One end of the first resistor is connected to the emitter of the first transistor, and the other end is connected to the base of the first transistor; A third resistor and a third capacitor are connected in parallel, one end of which is grounded and the other end is connected to the input end of a three-terminal voltage regulator chip; One end of the second resistor is connected to a 3.3V power supply, and the other end is connected to the input end of a three-terminal voltage regulator chip; The output end of the three-terminal voltage regulator chip is connected to the base of the first transistor.
2. The chip power timing control circuit according to claim 1, characterized in that: The model of the three-terminal voltage regulator chip is TL431.
3. A chip power timing control circuit, characterized in that: include: A first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a first transistor and a second transistor; One end of the first capacitor is grounded and the other end is connected to a 5V power supply; The collector of the first transistor is connected to a 5V power supply, and the emitter serves as a 5V output terminal; One end of the second capacitor is grounded, and the other end is connected to the emitter of the first transistor; One end of the first resistor is connected to the collector of the first transistor, and the other end is connected to the base of the first transistor; A third resistor and a third capacitor are connected in parallel, one end of which is grounded and the other end is connected to the base of the second transistor; One end of the second resistor is connected to the control signal, and the other end is connected to the base of the second transistor; The collector of the second transistor is connected to the base of the first transistor, and the emitter of the second transistor is grounded.